Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 1-17 are rejected under 35 U.S.C. 103 as being unpatentable over Goo et al. (US 7,012,007; hereinafter Goo) in view of Saito (US 2009/0310431).
Regarding claim 1, Goo, in fig. 3m, discloses a semiconductor device comprising: a semiconductor substrate 10 including a first semiconductor material (Si 10); a gate structure 60/62 on the semiconductor substrate; and a semiconductor pattern 40 including a second semiconductor material (SiGe 40), between the semiconductor substrate 10 and the gate structure 60/62, wherein the semiconductor pattern 40 is in contact with the semiconductor substrate 10, wherein the gate structure 60/62 is spaced apart from the semiconductor substrate 10, and wherein the first semiconductor material (Si 10) is different from the second semiconductor material (SiGe 40).
Goo discloses a semiconductor device as above but fails to disclose the gate structure passes through a portion of the semiconductor pattern.
However, Saito, in fig. 6A, discloses a trench gate structure (5/7-1/7-2/7-3/7-5) passes through a portion of the semiconductor pattern (SiGe 3). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form trench gate structure as taught by Saito in order to overcome the short channel effect and also downscale the transistor.
Regarding claim 2, Goo discloses wherein the first semiconductor material 10 is Si, and wherein the second semiconductor material 40 is SiGe (fig. 3m, col. 4, lines 13-15).
Regarding claim 3, Saito discloses wherein the gate structure includes a first part (7-1/7-2/7-3/7-5) and a second part (7-1) protruding from the first part (7-1/7-2/7-3/7-5), wherein a first part of the gate structure (7-1/7-2/7-3/7-5) is disposed on the first surface (top surface) of the semiconductor pattern 3, and wherein the second part (7-1) is disposed under the first surface (top surface) of the semiconductor pattern 3 (Saito, fig. 6A); and Goo discloses wherein the second surface (bottom surface) of the semiconductor pattern 40 is in contact with the semiconductor substrate 10 (Goo, fig. 3m).
Regarding claim 4, Saito discloses wherein the second part (7-1) is spaced apart from the second surface (bottom surface) of the semiconductor pattern 3 (fig. 6A).
Regarding claim 5, Saito discloses wherein the first part (7-1/7-2/7-3/7-5) has a first width in a second direction parallel to a top surface of the semiconductor substrate, wherein the second part (7-1) has a second width in the second direction, and wherein the second width (7-1) is narrower than the first width (7-1/7-2/7-3/7-5) (fig. 6A).
Regarding claim 6, Saito discloses further comprising: spacers 9 disposed on opposite sides of the first part (7-1/7-2/7-3/7-5) of the gate structure (fig. 6A).
Regarding claim 7, Saito discloses further comprising: an isolation layer 4 on the semiconductor substrate 1, wherein the isolation layer 4 has a portion in which a level of a top surface of the isolation layer 4 is the same as a level of a top surface of the semiconductor pattern 3 (fig. 6A).
Regarding claim 8, Saito discloses further comprising: an isolation layer 4 on the semiconductor substrate 1, wherein a sidewall of the isolation layer 4 is in contact with a lateral surface of the semiconductor pattern 3 (fig. 6A).
Regarding claim 9, although the thickness of the semiconductor pattern is not exactly as claimed, this claim is prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688(Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller,105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding claim 10, Saito discloses wherein the gate structure includes: a gate insulating pattern (5/4-2), a conductive pattern (7-2/7-3), a gate pattern 7-1, a metal-containing pattern 7-5, and a capping pattern 8 which are sequentially stacked (fig. 6A).
Regarding claim 11, Saito discloses further comprising: an interlayer insulating layer 11 disposed on the isolation layer 4 and on the semiconductor pattern 3, including the second semiconductor material, and covering the gate structure (7-1/7-2/7-3/7-5) (fig. 6A).
Regarding claim 12, Goo, in fig. 3m, discloses semiconductor device comprising: a semiconductor substrate 10 including a fin part 10 defined by an isolation layer 50; a gate structure (60/62) on the fin part; and a silicon-germanium (SiGe) pattern 40 interposed between the fin part 10 and the gate structure (60/62), wherein the silicon-germanium (SiGe) pattern 40 includes: a pair of dopant regions 72; and a pair of contacts 74 making contact with the pair of dopant regions 72, respectively, wherein the dopant regions 72 are disposed at an upper portion of the silicon-germanium (SiGe) pattern 40, and wherein the pair of contacts 74 are spaced apart from the semiconductor substrate 10.
Goo discloses a semiconductor device as above but fails to disclose the gate structure the silicon-germanium pattern includes a recessed part.
However, Saito, in fig. 6A, discloses a trench gate structure (5/7-1/7-2/7-3/7-5), wherein the silicon-germanium (SiGe) pattern 3 includes a recessed part at an upper portion of the silicon-germanium (SiGe) pattern 3, wherein a portion of the gate structure (5/7-1) fills the recessed part. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form trench gate structure as taught by Saito in order to overcome the short channel effect and also downscale the transistor.
Regarding claim 13, Goo discloses wherein the pair of dopant regions 72 are spaced apart from the semiconductor substrate 10 (fig. 3m).
Regarding claim 14, Goo discloses wherein the isolation layer 50 is based on a silicon oxide (fig. 3m).
Regarding claim 15, Saito discloses wherein each of the pair of contacts includes a through plug 12 and a contact pad 12-5, and wherein the contact pad 12-5 is connected to the through plug 12 (fig. 6A). Goo discloses the contact pad 74 interposed between a top surface and a bottom surface of the silicon-germanium (SiGe) pattern 40 (fig. 3m).
Regarding claim 16, Goo discloses wherein the contact pad 74 includes silicide (fig. 3m and col. 6, line 40).
Regarding claim 17, although the thickness of the SiGe pattern is not exactly as claimed, this claim is prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688(Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller,105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Allowable Subject Matter
2. Claims 18-20 are allowed.
The following is an examiner's statement of reason for allowance: the prior art of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of " a capacitor on the landing pad; a gate structure on the semiconductor substrate; and a peripheral active pattern disposed between the semiconductor substrate and the gate structure, wherein the peripheral active pattern includes a pair of dopant regions, wherein a pair of contacts connected to the pair of dopant regions, respectively, wherein the pair of contacts includes a through plug and a contact pad, wherein the peripheral active pattern includes a recessed part at an upper portion of the peripheral active pattern, wherein a portion of the gate structure fills the recessed part, wherein the dopant regions are disposed at an upper portion of the peripheral active pattern, wherein the pair of contacts are spaced apart from the semiconductor substrate, wherein the cell active patterns include a first semiconductor material, and wherein the peripheral active pattern includes a second semiconductor material” (claim 18) as instantly claimed and in combination with the remaining elements.
Conclusion
3. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Vu whose telephone number is (571) 272-1798. The examiner can normally be reached on Monday-Friday from 8:00am to 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempt to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke H can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/DAVID VU/
Primary Examiner, Art Unit 2818