DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/07/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 2 is objected to because of the following informalities:
In claim 2, the recitation of “the n-th bit resistor unit circuit” should change to read as ---n-th bit resistor unit circuit---.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3 & 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Otsuka et al. (US 20010019288 A1) in view of Voo et al. (US 7558014 B1), hereinafter called Otsuka and Voo.
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Fig. 7 of Otasuka et al.
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Fig. 7A of Voo et al.
Regarding claim 1, Otsuka (Fig. 7) discloses variable resistor circuit comprising:
a plurality of resistor unit circuits (S1, T1 to S8, T8) that are each configured with a first resistor (resistor T1) connected in parallel with a MOS switch (Par. 0053, witches are preferably formed by CMOS switches) and
and a third resistor (resistor T0) connected in series with the plurality of resistor unit circuits connected in series except for a second resistor connected in series with the MOS switch.
Voo (Fig. 7A) discloses a well-known switch or transistor 200 being connected in series with resistor 202, i.e. second resistor, (Col. 4, lines 42-44).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have replaced each switch S1-S8 of Otsuka with well-known transistor 200 in series with resistor of Voo as an art recognized switchable resistance of providing programmable gain and allowing adjusting precise control of amplification (Fig. 7A of Voo), as commonly known in the art.
As a result of the combination, it is noted that the combination of Fig. 7 of Otsuka and Fig. 7A of Voo, having analogous art to the Fig. 5 of the application, the combination further discloses wherein when Δ represents a resistance value change in each resistor unit circuit (S1, T1 to S S8, T8) between a first combined resistance value of said resistor unit circuit including at least a resistance value of the resistor unit circuit with the MOS switch off and a second combined resistance value of said resistor unit circuit including at least a resistance value of the resistor unit circuit with the MOS switch on, and RA represents a sum of the total combined resistance values of the plurality of resistor unit circuits with the MOS switches in all the resistor unit circuits off and a resistance value of the third resistor, the variable resistor circuit is configured to change a resistance value thereof based on a resistance value change ratio given by (Δ / RA) × 100 % in each resistor unit circuit (Fig. 7 of Otsuka in view of Fig. 7A of Voo, meeting the claimed 1 invention).
Regarding claim 3, the combination (Otsuka in view of Voo) further discloses wherein the first (resistor T1, Fig. 7 of Otsuka), second (resistor T2), and third (resistor T0) resistors are each configured with a single unit resistive element or a combination of a plurality of unit resistive elements.
Regarding claim 5, the combination (Otsuka in view of Voo) further discloses wherein the combined resistance values of the plurality of resistor unit circuits (switch S1 and resistor T1 to switch 8, resistor T8) with the MOS switches on are different from each other (Par 0015, control signal D1 to D8 of eight bits setting resistance values corresponding to data expressed by the control signals d1 to d8 of eight bits).
Regarding claim 6, the combination (Otsuka in view of Voo) further discloses wherein in at least one of the resistor unit circuits (Resistor 8, Fig. 7 of Otsuka, switch 200 in series with resistor 202, Fig. 7A of Voo), the first and second combined resistance values include a resistance component connected in series with said resistor unit circuit, and the third resistor (resistor T0, Fig. 7 of Otsuka) includes the resistance component.
Allowable Subject Matter
Claims 2, 4 & 7-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Reference US-20190155323, Kim et al. discloses in Fig. 5 a variable circuit having switch S11 in series with resistor R11.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843