DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in the COUNTRY OF KOREA on 09/13/2022.
Election/Restrictions
Applicant's election without traverse of “Species A (Claims 1-5 and 7-20)” in the reply filed on February 09, 2026, is acknowledged. Claim 6 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Objections
Claim 19 is objected to because of the following informality: typographical error consisting of a repetition of word “and” within first paragraph of claim 19. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 8-13 are rejected under 35 U.S.C. 103 as being obvious over US 2019/0131273 A1; Chen et al.; 05/2019; (“273”) in view of US 2016/0079207; Yamaguchi et al.; 03/2016; (“207”).
Regarding Claim 1. 273 teaches in Fig. 9 about a semiconductor package, comprising:
a redistribution substrate (item RDL1) including a first surface (upper surface of item RDL1) and a second surface opposite to the first surface (bottom surface of item RDL1 is opposite to the first surface), the first surface having a first region (region of the first surface of item RDL1 below item CM) and a second region extending around at least a portion of the first region (other region of the first surface of item RDL1 not below item CM), the redistribution substrate including a plurality of first insulating layers (layer items 102) and a plurality of first redistribution layers (layer items 104) that are sequentially stacked and electrically connected to each other (layer items 104 are sequentially stacked and electrically connected to each other);
a first lower semiconductor chip (item 101) and a second lower semiconductor chip (item 201) positioned in a first direction (left-to-right direction) on the first region of the first surface of the redistribution substrate (items 101 and 201 are on the first region of item RDL1), each of the first and second lower semiconductor chips having a plurality of first contact pads (see Examiner annotated Fig. 9) electrically connected to the plurality of first redistribution layers (fist contact pads and items 104 are electrically connected through solder bumps);
a plurality of conductive posts (items TIV) positioned at least on the left and right sides of the first and second lower semiconductor chips on the first region of the first surface of the redistribution substrate (items TIV are positioned at least on the left and right sides of the semiconductor chip items 101 and 201 on the first region of item RDL1);
a first molding layer (item E1) on the first region of the first surface of the redistribution substrate and on the plurality of conductive posts and the first and second lower semiconductor chips (item E1 is positioned on the first region of item RDL1, on items TIV, and on semiconductor items 101 and 201);
a redistribution structure on the first molding layer (item RDL2 is on item E1) and including a plurality of second insulating layers (items 106) and a plurality of second redistribution layers (items 108) that are sequentially stacked and electrically connected to the plurality of first redistribution layers by the plurality of conductive posts (items 108 are sequentially stacked and electrically connected to items 104 by the plurality of items TIV);
a first upper semiconductor chip (item 300) and a second upper semiconductor chip (item 400) positioned in a first direction, and overlapping a region between the first and second lower semiconductor chips on the redistribution structure (semiconductor items 300 and 400 overlap a region between semiconductor items 101 and 201 on item RDL1), each of the first and second upper semiconductor chips having a plurality of second contact pads (see Examiner annotated Fig. 9) electrically connected to the plurality of second redistribution layers (second contact pads and items 108 are electrically connected through solder bumps); and
a second molding layer (item E2) on the second region of the first surface of the redistribution substrate (see Examiner annotated Fig. 9, item E2 is on the second region of the first surface of item RDL1) and on the redistribution structure and the first and second upper semiconductor chips (item E2 is on item RDL2 and semiconductor items 300 and 400).
273 does not teach about a semiconductor package, comprising:
a plurality of conductive posts positioned around the first and second lower semiconductor chips on the first region of the first surface of the redistribution substrate;
a first upper semiconductor chip and a second upper semiconductor chip positioned in a second direction, intersecting the first direction.
207 teaches in Figs. 1 and 5 about a semiconductor package, comprising:
a plurality of conductive posts (Fig. 5, items 44) positioned around a first semiconductor chip (Fig. 1, item 20).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the plurality of conductive post around a semiconductor chip of 207 to electrically couple the redistribution substrate and the redistribution structure in 273 in order to provide a “Package-on-Package (PoP) structure” as taught by 207 in Fig. 7 and [0044].
273 in view of 207 does not teach about a semiconductor package, comprising:
a first upper semiconductor chip and a second upper semiconductor chip positioned in a second direction, intersecting the first direction.
It would have been also obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to re-orientate the side-by-side layout of the first and second upper semiconductor chips in any direction within the same plane, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
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Fig. 9, annotated by Examiner from Chen et al., “273”
Regarding Claim 2. 273 teaches in Fig. 9 about a semiconductor package, wherein the first and second lower semiconductor chips (“first and second semiconductor chips 100 and 200 includes an integrated passive device, such as a capacitor, an inductor or a resistor”, [0020], Ln. 1-3) and the first and second upper semiconductor chips (“third and fourth semiconductor chips 300 and 400 includes an integrated active device”, [0027, Ln. 1-3]) are a different type of semiconductor chips.
273 does not teach about a semiconductor package, wherein the first and second lower semiconductor chips and the first and second upper semiconductor chips are a same type of semiconductor chips.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to duplicate a semiconductor chip type and use it in an upper or lower level to replace a different type of semiconductor chip, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04.
Regarding Claim 3. 207 teaches in Figs. 2 and 3 about a semiconductor package, wherein the lower semiconductor chip (Fig. 3, item 20) and the upper semiconductor chip (Fig. 2, item 10) each have a rectangular plane (items 10 and 20 both have a rectangular plane).
207 does not teach about a semiconductor package, wherein the first and second lower semiconductor chips and the first and second upper semiconductor chips each have a rectangular plane.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to duplicate the lower and second semiconductor chips while maintaining the same rectangular shape to increase device power or processing capabilities, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04.
Regarding Claim 4. 273 teaches in Fig. 9 about a semiconductor package, wherein the first and second lower semiconductor chips are configured to face each other, and the first and second upper semiconductor chips are configured to face each other.
273 does not teach about a semiconductor package, wherein the first and second lower semiconductor chips are configured such that longer sides thereof face each other, and the first and second upper semiconductor chips are configured such that longer sides thereof face each other.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to experiment layout configurations within a same plane of the upper and lower semiconductor chips including longer sides facing each other, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding Claim 5. 273 teaches in Fig. 9 about a semiconductor package, wherein the first and second lower semiconductor chips are configured to face each other.
273 does not teach about a semiconductor package, wherein the first and second lower semiconductor chips are configured such that the longer sides thereof are configured to be offset from each other in the second direction.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to experiment layout configurations of the first and second lower chips including an offset from each other in any given direction within the same plane, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding Claim 8. 273 teaches in Fig. 9 about a semiconductor package, wherein the redistribution substrate has a not disclosed thickness.
273 does not teach about a semiconductor package, wherein the redistribution substrate has a thickness of 100 μm or less.
It would have been an obvious matter of design choice to choose a redistribution substrate with a thickness of 100 μm or less, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding Claim 9. 273 teaches in Fig. 9 about a semiconductor package, wherein the redistribution structure has a not disclosed thickness.
273 does not teach about a semiconductor package, wherein the redistribution structure has a thickness of 100 μm or less.
It would have been an obvious matter of design choice to choose a redistribution structure with a thickness of 100 μm or less, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding Claim 10. 273 teaches in Fig. 9 about a semiconductor package, wherein each of the plurality of first and second insulating layers includes a photosensitive insulating layer (“each of the polymer layers 102 includes a polymer material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB)”, [0015], Ln. 10-12; and “polymer layers 106 includes a polymer material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB)”, [0022], Ln. 12-14; wherein the previously quoted materials are well known in the art for their photosensitive material nature).
Regarding Claim 11. 273 teaches in Fig. 9 about a semiconductor package, wherein the first molding layer has side surfaces that are respectively coplanar with side surfaces of the redistribution structure (molding layer item E1 has side surfaces that are coplanar with side surfaces of item RDL2).
Regarding Claim 12. 273 teaches in Fig. 9 about a semiconductor package, wherein the second molding layer has side surfaces that are respectively coplanar with side surfaces of the redistribution substrate (molding layer item E2 has side surfaces that are coplanar with side surfaces of item RDL1).
Regarding Claim 13. 273 teaches in Fig. 9 about a semiconductor package, wherein the plurality of conductive posts include conductive posts positioned between the first and second lower semiconductor chips (at least five items TIV are between semiconductor items 101 and 201).
Claims 14 -20 are rejected under 35 U.S.C. 103 as being obvious over US 2019/0131273 A1; Chen et al.; 05/2019; (“273”).
Regarding Claim 14. 273 teaches in Fig. 9 about a semiconductor package, comprising:
a redistribution substrate (item RDL1) including a first surface (upper surface of item RDL1) and a second surface opposite to the first surface (bottom surface of item RDL1 is opposite to the first surface), the first surface having a first region (region of the first surface of item RDL1 below item CM) and a second region extending around at least a portion of the first region (other region of the first surface of item RDL1 not below item CM), the redistribution substrate including a plurality of first insulating layers (layer items 102) and a plurality of first redistribution layers (layer items 104) that are sequentially stacked and electrically connected to each other (layer items 104 are sequentially stacked and electrically connected to each other);
a plurality of lower semiconductor chips (items 101 and 201) on the first region of the first surface of the redistribution substrate (items 101 and 201 are on the first region of the first surface of item RDL1), each of the plurality of lower semiconductor chips electrically connected to the plurality of first redistribution layers (see Examiner annotated Fig. 9, semiconductor items 101 and 201 are electrically connected to items 104 through first contact pads and solder bumps), wherein spaces between the plurality of lower semiconductor chips include a space extending from one side of the redistribution substrate to an opposite side of the redistribution substrate (spaces between items 101 and 201 include a space extending from a left-side to a right-side of item RDL1);
a first molding layer (item E1) on the first region of the first surface of the redistribution substrate and on the plurality of lower semiconductor chips (item E1 is positioned on the first region of item RDL1 and on semiconductor items 101 and 201);
a redistribution structure on the first molding layer (item RDL2 is on item E1) and including a plurality of second insulating layers (items 106) and a plurality of second redistribution layers (items 108) that are sequentially stacked and electrically connected to each other (items 108 are sequentially stacked and electrically connected to each other);
a plurality of conductive posts (items TIV) on the first region of the first surface of the redistribution substrate and electrically connecting the plurality of first redistribution layers to the plurality of second redistribution layers (items TIV are on the first region of the first surface of item RDL1 and electrically connecting items 104 and 108);
a plurality of upper semiconductor chips (items 300 and 400) partially overlapping the space extending from one side of the redistribution substrate to an opposite side of the redistribution substrate (items 300 and 400 are partially overlapping the space extending from the left-side to the right-side of item RDL1), on the redistribution structure and each electrically connected to the plurality of second redistribution layers (items 300 and 400 are on item RDL2 and each electrically connected to items 108); and
a second molding layer (item E2) on the second region of the first surface of the redistribution substrate (see Examiner annotated Fig. 9, item E2 is on the second region of the first surface of item RDL1) and on the redistribution structure and the plurality of upper semiconductor chips (item E2 is on item RDL2 and semiconductor items 300 and 400).
273 does not teach about a semiconductor package, comprising:
a plurality of upper semiconductor chips overlapping the space extending from one side of the redistribution substrate to an opposite side of the redistribution substrate.
It would have been also obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to re-orientate the side-by-side layout of the upper semiconductor chips in a direction within the same plane to overlap the space extending from one side of the redistribution substrate to an opposite side of the redistribution substrate, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding Claim 15. 273 teaches in Fig. 9 about a semiconductor package, wherein the plurality of lower semiconductor chips include a first and second lower semiconductor chips having a same area.
273 does not teach about a semiconductor package, wherein the plurality of lower semiconductor chips include a first lower semiconductor chip having a first area and second and third lower semiconductor chips having an area less than the first area.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to add a third lower semiconductor chip to improve semiconductor package capabilities, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04.
It would have been also an obvious matter of design choice to provide the duplicated lower semiconductors chip with a same or different size, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding Claim 16. 273 teaches in Fig. 9 about a semiconductor package, wherein a side-by-side first and second lower semiconductor chips have a same area.
273 does not teach about a semiconductor package, wherein the second and third lower semiconductor chips are along one side of the first lower semiconductor chip, and a space is between the first lower semiconductor chip and the second and third lower semiconductor chips.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to add a third lower semiconductor chip to improve semiconductor package capabilities, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04.
It would have been also obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to experiment orientating the side-by-side layout of the lower semiconductor chips in a fitting direction within the same plane, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding Claim 17. 273 teaches in Fig. 9 about a semiconductor package, wherein a side-by-side first and second lower semiconductor chips have a same area.
273 does not teach about a semiconductor package, wherein the plurality of upper semiconductor chips include an upper semiconductor chip on at least a portion of the space between the second and third lower semiconductor chips.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to add a third lower semiconductor chip to improve semiconductor package capabilities, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04.
It would have been also obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to experiment orientating (withing the same plane) an upper semiconductor chip on a portion of the space between any of the lower semiconductor chips, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding Claim 18. 273 teaches in Fig. 9 about a semiconductor package, wherein each of the plurality of first and second insulating layers includes a photosensitive insulating resin layer (“each of the polymer layers 102 includes a polymer material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB)”, [0015], Ln. 10-12; and “polymer layers 106 includes a polymer material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB)”, [0022], Ln. 12-14; wherein the previously quoted resin materials are well known in the art for their photosensitive material nature), and
each of the redistribution substrate and the redistribution structure has a thickness not disclosed.
273 does not teach about a semiconductor package, wherein each of the redistribution substrate and the redistribution structure has a thickness of 100 μm or less.
It would have been an obvious matter of design choice to choose a redistribution substrate or a redistribution structure with a thickness of 100 μm or less, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding Claim 19. 273 teaches in Fig. 9 about a semiconductor package, comprising:
a redistribution substrate (item RDL1) having a first surface (upper surface of item RDL1) and a second surface opposite to the first surface (bottom surface of item RDL1 is opposite to the first surface), the first surface including a first region (region of the first surface of item RDL1 below item CM) and a second region on the first region (other region of the first surface of item RDL1 not below item CM and on the sides of the first region) and, and including a first redistribution layer (first surface of RDL1 includes a top most first redistribution layer item 104);
first (item 101) and second (item 201) semiconductor chips positioned in a first direction (left-to-right direction) on the first region of the first surface of the redistribution substrate (items 101 and 201 are on the first region of item RDL1), each of the first and second semiconductor chips being electrically connected to the first redistribution layer (items 101 and 201 are electrically connected to the top most redistribution layer item 104);
a first molding layer (item E1) on the first region of the first surface of the redistribution substrate and on the first and second semiconductor chips (item E1 is positioned on the first region of item RDL1 and on semiconductor items 101 and 201);
a redistribution structure on the first molding layer (item RDL2 is on item E1) and including a second redistribution layer (item 108);
a plurality of conductive posts (items TIV) on the first region of the first surface of the redistribution substrate and electrically connecting the first redistribution layer to the second redistribution layer (items TIV are on the first region of the first surface of item RDL1 and electrically connecting items 104 and 108);
third (item 300) and fourth (item 400) semiconductor chips positioned in a first direction, to partially overlap a region between the first and second semiconductor chips on the redistribution structure (items 300 and 400 are partially overlapping a region between items 101 and 201 on item RDL2), and each electrically connected to the second redistribution layer (items 300 and 400 are electrically connected to item 108); and
a second molding layer (item E2) on the second region of the first surface of the redistribution substrate (see Examiner annotated Fig. 9, item E2 is on the second region of the first surface of item RDL1) and on the redistribution structure and the third and fourth semiconductor chips (item E2 is on item RDL2 and semiconductor items 300 and 400).
273 does not teach about a semiconductor package, comprising:
third and fourth semiconductor chips positioned in a second direction, intersecting the first direction, to overlap a region between the first and second semiconductor chips on the redistribution structure.
It would have been also obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to re-orientate the side-by-side layout of the upper semiconductor chips in a direction within the same plane to overlap a region between the first and second semiconductor chips on item RDL2, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding Claim 20. 273 teaches in Fig. 9 about a semiconductor package, wherein the third to fourth semiconductor chips include a same type of memory chips (“third and fourth semiconductor chips 300 and 400 includes … active devices such as memory devices”, [0026], Ln. 1-7) having a non-disclosed shape.
273 does not teach about a semiconductor package, wherein the first to fourth semiconductor chips include a same type of memory chips having a rectangular planar shape.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to duplicate and use the same type of memory device from the third and fourth semiconductor devices for the first and second semiconductor devices, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04.
It would have been also obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to experiment different shapes for the first to fourth semiconductor chips (specially a rectangular shape), since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art does not teach or suggest the claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897
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