DETAILED ACTION
Election/Restrictions
Applicant’s election of Invention I (semiconductor device), reflected in claims 1-10 in the reply filed on 12/02/2025 is acknowledged. Claims 11-17 are withdrawn from further consideration pursuant to 37 CFR 1.142 (b), as being drawn to the nonelected group.
Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)).
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, and 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 20220320116 A1, hereinafter Lin‘116).
Regarding independent claim 1, Lin‘116 teaches, “A semiconductor device (fig. 1-4; ¶ [0014] - ¶ [0151]), comprising:
a lower active region (810, 132, fig. 1I-1, 1I-2) arranged on a substrate (110), wherein the lower active region comprises:
a fin (132, ‘fin structure’, ¶ [0017]) extending in a first direction on the substrate (110), and
lower source/drain portions (810, ‘source/drain epitaxial structures’, ¶ [0046]) at two opposite ends of the fin (132) in the first direction, respectively;
an upper active region (930, 154) arranged above the lower active region, wherein the upper active region comprises:
one or more nanosheets (154, ‘nanostructures’, ¶ [0071]), wherein a lowest nanosheet is spaced apart from the fin (132) in a vertical direction relative to the substrate (110), and
upper source/drain portions (930) at two opposite ends of the one or more nanosheets (154) in the first direction, respectively; and
a gate stack (410 in fig. 1I-1, 1I-2, and 1220, 130 in fig. 1P, 1Q) extending in a second direction intersecting with the first direction so as to intersect with the fin (132) and the one or more nanosheets (154)”.
Regarding claim 2, Lin‘116 further teaches, “The semiconductor device according to claim 1, wherein the fin (132, fig. 1I-2) is self-aligned with the one or more nanosheets (154)”.
Regarding claim 3, Lin‘116 further teaches, “The semiconductor device according to claim 1, wherein the upper active region comprises a plurality of nanosheets (154, fig. 1I-2), and each of the plurality of nanosheets is spaced apart from each other in the vertical direction and self-aligned with each other”.
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Regarding claim 4, Lin‘116 further teaches, “The semiconductor device according to claim 1, further comprising: an isolation layer (910, fig. 1I-2) between the lower source/drain portions (810) and the upper source/drain portions (930)”.
Regarding claim 5, Lin‘116 further teaches, “The semiconductor device according to claim 1, wherein the gate stack (410 in fig. 1I-1, 1I-2, and 1220, 130 in fig. 1P, 1Q) surrounds a periphery of each of the one or more nanosheets (154) and extends on a top surface and a side surface of the fin (132)”.
Regarding claim 8, Lin‘116 further teaches, “The semiconductor device according to claim 1, wherein a length of the fin (fig. Lin‘116, fig. 2I-2, mapping 810, 132 as fin) in the first direction is greater than a length of the nanosheet (154) in the first direction”.
Regarding claim 9, Lin‘116 further teaches, “The semiconductor device according to claim 4, further comprising a spacer structure on sidewalls of the gate stack on two opposite sides in the first direction, wherein the spacer structure comprises:
an outer spacer (420, fig. I1-1, 1I-2) extending in the second direction; and
an inner spacer (230) extending in the second direction, between adjacent nanosheets (154) in the one or more nanosheets and on a lower surface of the lowest nanosheet,
wherein the outer spacer (420), the inner spacer (230) are located between the gate stack (410) and the upper source/drain portion (930), and the isolation layer (910) is located between the lower source/drain portion (810) and the upper source/drain portion (930)”.
Regarding claim 10, Lin‘116 further teaches, “The semiconductor device according to claim 1, wherein the lower source/drain portion and the upper source/drain portion have a same doping type or different doping types (¶ [0047], ¶ [0053])”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lin‘116 as applied to claim 1 above, and further in view of Xie et al. (US 20190326286 A1, hereinafter Xie‘286).
Regarding claim 6, Lin‘116 teaches all the limitations described in claim 1.
But Lin‘116 is silent upon the provision of wherein a width of the fin in the second direction is smaller than a width of the nanosheet in the second direction.
However, Xie‘286 teaches a similar semiconductor device (fig. 21), wherein a width of the fin (218a) in the second direction is smaller than a width of the nanosheet (211a, 211b) in the second direction.
Lin‘116 and Xie‘286 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lin‘116 with the features of Xie‘286 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Lin‘116 and Xie‘286 to form the fin and nanosheet in the stack transistor according to the teachings of Xie‘286 with a motivation of achieving mechanical stability of the stack transistors as discussed by Xie‘286, ¶ [0002] - ¶ [0006].
Regarding claim 7, Lin‘116 modified with Xie‘286 further teaches, “The semiconductor device according to claim 6, wherein the fin has a width of 1 nm to 50 nm in the second direction (Xie‘286, ¶ [0066])”.
Examiner’s Note
The prior arts cited in PTO-892 but not used in the current rejection are related to the claimed novelty.
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817