DETAILED ACTION
Response to Arguments
Applicant's arguments filed 04/09/2026 have been fully considered but they are not persuasive.
Applicant argues:
[Page 8] of REMARKS,
According to FIG. 11-2 of Lin, the second inner gate spacer 620 is located between the nanostructure 154 and the first fin structure 132 in the vertical direction. Due to the presence of the second inner gate spacer 620, the gate stack surrounding the periphery of the nanostructure 154 clearly cannot extend on the top surface of the first fin structure 132. Furthermore, there is no evidence to suggest that the gate stack surrounding the periphery of nanostructure 154 can extend on the side surface of the first fin structure 132. This results in the gate stack surrounding the periphery of the nanostructure 154 only being able to control the nanostructure 154, and unable to control the first fin structure 132.
Examiner’s reply:
The office disagrees.
The newly included limitation in claim 1 (previous dependent claim 5, now cancelled, ‘wherein the gate stack surrounds a periphery of each of the one or more nanosheets and extends on a top surface and a side surface of the fin’) mentions the limitataion ‘gate stack’. The limitataion, ‘gate stack’ is interpretated as a stack/structure including gate electrodes, gate spacers, gate dielectric films and gate caps etc. Referring to fig. 1G-1, 2 -1I-1, 2 of Lin’116, gate stack (410, 230, 610, 620) fully/completely surrounds the nanosheet (154) and also extends on a top surface and a side surface of the fin (132). Similarly, referring to fig. 1M-1, 2 of Lin’116, gate stack (1320 etc.) completely surround the nanostructures (154). See ¶ [0070]- ¶ [0071]], “the second gate stack 1320 encircles (wraps) the semiconductor layers 154” and extends on a top surface and a side surface of the fin (132).
If we consider ‘gate electrode’ instead of ‘gate stack’ in the amended claim, referring to fig. 1M-1, 2, gate electrodes (1220c, 1320c etc.) completely surround the nanostructures (154) and extends on a top surface and a side surface of the fin (132).
The newly included limitation in claim 1 (previous dependent claim 5, now cancelled, ‘wherein the gate stack surrounds a periphery of each of the one or more nanosheets and extends on a top surface and a side surface of the fin’) can be interpreted using broadest reasonable interpretation (BRI). During examination, the claims must be interpreted as broadly as their terms reasonably allow. In re American Academy of Science Tech Center, F.3d, 2004 WL 1067528 (Fed. Cir. May 13, 2004). In the instant case, the limitation “surround” is given the broadest reasonable interpretation as “partially surround”. A partially surrounded situation describes something that is not fully enclosed but is limited in its exposure to the outside.
Referring to fig. 1I-1, 2, (dummy) gate electrode (330) at least partially surrounds nanostructures (154).
The applicant is being requested to review all the drawings of Lin’116.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, and 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 20220320116 A1, hereinafter Lin’116) of record.
Regarding independent claim 1, Lin’116 teaches, “A semiconductor device (fig. 1-4; ¶ [0014] - ¶ [0151]), comprising:
a lower active region (810, 132, fig. 1I-1, 1I-2) arranged on a substrate (110), wherein the lower active region comprises:
a fin (132, ‘fin structure’, ¶ [0017]) extending in a first direction on the substrate (110), and
lower source/drain portions (810, ‘source/drain epitaxial structures’, ¶ [0046]) at two opposite ends of the fin (132) in the first direction, respectively;
an upper active region (930, 154) arranged above the lower active region, wherein the upper active region comprises:
one or more nanosheets (154, ‘nanostructures’, ¶ [0071]), wherein a lowest nanosheet is spaced apart from the fin (132) in a vertical direction relative to the substrate (110), and
upper source/drain portions (930) at two opposite ends of the one or more nanosheets (154) in the first direction, respectively; and
a gate stack (410 in fig. 1I-1, 1I-2, and 1220, 130 in fig. 1P, 1Q) extending in a second direction intersecting with the first direction so as to intersect with the fin (132) and the one or more nanosheets (154),
wherein the gate stack (410 or 410, 230, 610, 620) surrounds (partially or fully) a periphery of each of the one or more nanosheets (154) and extends on a top surface and a side surface of the fin (132)”.
Regarding claim 2, Lin’116 further teaches, “The semiconductor device according to claim 1, wherein the fin (132, fig. 1I-2) is self-aligned with the one or more nanosheets (154)”.
Regarding claim 3, Lin’116 further teaches, “The semiconductor device according to claim 1, wherein the upper active region comprises a plurality of nanosheets (154, fig. 1I-2), and each of the plurality of nanosheets is spaced apart from each other in the vertical direction and self-aligned with each other”.
Regarding claim 4, Lin‘116 further teaches, “The semiconductor device according to claim 1, further comprising: an isolation layer (910, fig. 1I-2) between the lower source/drain portions (810) and the upper source/drain portions (930)”.
Regarding claim 8, Lin‘116 further teaches, “The semiconductor device according to claim 1, wherein a length of the fin (fig. Lin‘116, fig. 2I-2, mapping 810, 132 as fin) in the first direction is greater than a length of the nanosheet (154) in the first direction”.
Regarding claim 9, Lin‘116 further teaches, “The semiconductor device according to claim 4, further comprising a spacer structure on sidewalls of the gate stack on two opposite sides in the first direction, wherein the spacer structure comprises:
an outer spacer (420, fig. I1-1, 1I-2) extending in the second direction; and
an inner spacer (230) extending in the second direction, between adjacent nanosheets (154) in the one or more nanosheets and on a lower surface of the lowest nanosheet,
wherein the outer spacer (420), the inner spacer (230) are located between the gate stack (410) and the upper source/drain portion (930), and the isolation layer (910) is located between the lower source/drain portion (810) and the upper source/drain portion (930)”.
Regarding claim 10, Lin‘116 further teaches, “The semiconductor device according to claim 1, wherein the lower source/drain portion and the upper source/drain portion have a same doping type or different doping types (¶ [0047], ¶ [0053])”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lin‘116 as applied to claim 1 above, and further in view of Xie et al. (US 20190326286 A1, hereinafter Xie‘286) of record.
Regarding claim 6, Lin‘116 teaches all the limitations described in claim 1.
But Lin‘116 is silent upon the provision of wherein a width of the fin in the second direction is smaller than a width of the nanosheet in the second direction.
However, Xie‘286 teaches a similar semiconductor device (fig. 21), wherein a width of the fin (218a) in the second direction is smaller than a width of the nanosheet (211a, 211b) in the second direction.
Lin‘116 and Xie‘286 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lin‘116 with the features of Xie‘286 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Lin‘116 and Xie‘286 to form the fin and nanosheet in the stack transistor according to the teachings of Xie‘286 with a motivation of achieving mechanical stability of the stack transistors as discussed by Xie‘286, ¶ [0002] - ¶ [0006].
Regarding claim 7, Lin‘116 modified with Xie‘286 further teaches, “The semiconductor device according to claim 6, wherein the fin has a width of 1 nm to 50 nm in the second direction (Xie‘286, ¶ [0066])”.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266. The examiner can normally be reached 9AM-7PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
Prosecution Insights