Prosecution Insights
Last updated: April 19, 2026
Application No. 18/462,614

SEMICONDUCTOR MEMORY DEVICE

Non-Final OA §103§112
Filed
Sep 07, 2023
Examiner
QUINTO, KEVIN V
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
86%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
710 granted / 837 resolved
+16.8% vs TC avg
Minimal +1% lift
Without
With
+1.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
31 currently pending
Career history
868
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
47.7%
+7.7% vs TC avg
§102
34.0%
-6.0% vs TC avg
§112
14.4%
-25.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 837 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claim 11 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 11 depends on claim 10. Claim 10 states that the first portion and a second portion of the first word line are alternately arranged in the second direction. Claim 11 limitation requires that (emphasis added), “the pair of the second portions of the first word line are adjacent to each other in the second direction.” This limitation of claim 11 contradicts parent claim 10 which requires that the first portion and a second portion of the first word line are alternately arranged in the second direction. Thus claim 11 fails to include all the limitations of the claim upon which it depends (claim 10). Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Renn (United States Patent Application Publication No. US 2011/0227145 A1, hereinafter “Renn”) in view of Cheng et al. (United States Patent Application Publication No. US 2018/0286977 A1, hereinafter “Cheng”). In reference to claim 1, Renn discloses a similar device. Fig. 1-7 of Renn discloses a semiconductor memory device which comprises a bit line (20) extended in a first direction (X-direction) on a substrate (10). A first word line (52) extends in a second direction (Y-direction) on the bit line (20). Fig. 1 of Renn shows a single memory cell as part of an array; it is understood that there are additional identical memory cells to the left and right of the fig. 1 memory cell along the X-direction. Therefore there is a second word line (52) extended in the second direction (Y-direction) on the bit line (20) and spaced apart from the first word line (52) in the first direction (X-direction). A back gate electrode (54) is between the first word line (52) and the second word line (52) and is extended in the second direction (Y-direction). A first active pattern (10a) is between the first word line (52) and the back gate electrode (54) on the bit line (20). A second active pattern (10b) is between the first word line (52) and the back gate electrode (54) on the bit line (20). Renn does not disclose that the back gate electrode includes a first region comprising a first conductive material and a second region comprising a second conductive material different from the first conductive material, and the first region of the back gate electrode is between the second region of the back gate electrode and the bit line. However fig. 8 of Cheng discloses a back gate electrode stack (808) which has a first lower region with a stack of at least two work function metal layers since Cheng discloses (emphasis added - p. 5, paragraph 52), “Non-limiting examples of suitable work function metals include p-type work function metal materials and n-type work function metal materials. P-type work function materials include compositions such as ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, or any combination thereof. N-type metal materials include compositions such as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or any combination thereof.” Cheng further discloses that the back gate electrode stack (808) includes a second upper region comprising a second conductive material in the form of a conductive gate metal which comprises aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof (p. 5, paragraph 53). The second conductive material (conductive gate metal) is formed over the stack of at least two work function metal layers and is different from the first conductive material of either of the at least two work function metal layers. Cheng discloses that using a back gate electrode with a structure different from the front gate allows different voltages to be applied to the back gate and front gate electrodes which provides the benefit of tuning the characteristics of the device (p. 6, paragraph 57). In view of Cheng, it would therefore be obvious to implement a back gate electrode which includes a first region comprising a first conductive material and a second region comprising a second conductive material different from the first conductive material. In the device of Renn constructed in view of Cheng, the uppermost layer of the work function metal layer stack is the first region of the back gate electrode while the conductive gate metal forms the second region of the back gate electrode; the first region of the back gate electrode is between the second region of the back gate electrode and the bit line (20 – fig. 1-7 of Renn). With regard to claim 2, in the device of Renn constructed in view of Cheng, the first region of the back gate electrode is a first electrode pattern of the first conductive material (work function metal), and the second region of the back gate electrode is a second electrode pattern of the second conductive material (conductive gate metal). In reference to claim 3, in the device of Renn constructed in view of Cheng, the lowermost layer of the work function metal layer stack forms a third region between the uppermost layer of the work function metal layer (that forms the first region) and the bit line. The third region of the back gate electrode comprises a third conductive material different from the first conductive material. With regard to claim 10, fig. 1 of Renn shows that the first word line (52) comprises a first portion and a second portion that are alternately arranged in the second direction (Y-direction), and a width of the first portion of the first word line in the first direction is less than a width of the second portion of the first word line in the first direction. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Renn in view of Cheng as applied to claim 1 above and further in view of Cheng. In reference to claim 9, Renn does not disclose that the first and second word lines (52) each comprises a first word line material layer comprising a third conductive material and a second word line material layer comprising a fourth conductive material different from the third conductive material. However Cheng discloses the known use of two different gate metal material layers, which include a combination of aluminum, platinum, gold, tungsten, or titanium, as a gate electrode material (p. 3, paragraph 36). The applicant is reminded in this regard that it has been held that the selection of a known material based on its suitability for its intended use would be entirely obvious. See Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) ("Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious). See MPEP 2144.07. In view of the above, it would therefore be obvious to implement each of the first and second word lines (52) with a stack of two different metal layers with one metal layer being the third conductive material and the second metal layer being the fourth conductive material. Allowable Subject Matter Claims 12-20 are allowed. Claims 4-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement a semiconductor memory device which comprises a bit line extended in a first direction on a substrate, a first and second word lines extended in a second direction on the bit line such that the first and second word lines are spaced apart from each other in the first direction, a back gate electrode between the first word line and the second word line and extended in the second direction, first and second active patterns between the first word line and the back gate electrode on the bit line such that the back gate electrode includes a first region comprising a first conductive material and a second region comprising a second conductive material different from the first conductive material, and the first region of the back gate electrode is between the second region of the back gate electrode and the bit line in combination with the specific first and second sub-electrode patterns described by the applicant in claim 4. In the examiner’s opinion, it would also not be obvious to implement a semiconductor memory device which comprises a bit line extended in a first direction on a substrate, first and second active patterns on the bit line such that the first and second active patterns are spaced apart from each other in the first direction, first and second word lines between the first and second active patterns and extended in a second direction such that the first and second word lines are spaced apart from each other in the first direction in combination with a gate isolation pattern on the bit line such that the gate isolation pattern comprises a horizontal portion and a protrusion portion, with the horizontal portion being between the first word line and the bit line and between the second word line and the bit line and the protrusion portion being between the first and second word lines, and a width of the horizontal portion in the first direction is greater than that of the protrusion portion in the first direction; a back gate electrode on the bit line which is spaced apart from the first and second word lines in the first direction and is extended in the second direction, data storage patterns connected to the first and second active patterns and the second active pattern such that the back gate electrode comprises a first region comprising a first conductive material and a second region comprising a second conductive material different from the first conductive material, and the first region of the back gate electrode is between the second region of the back gate electrode and the bit line as described by the applicant in claim 12. In the examiner’s opinion, it would also not be obvious to implement a semiconductor memory device which comprises a peripheral gate structure on a substrate, a bit line extended in a first direction on the peripheral gate structure, a shielding conductive line adjacent to the bit line on the peripheral gate structure and extended in the first direction, first and second word lines extended in a second direction on the bit line and the shielding conductive line such that the first and second word lines are spaced apart from each other in the first direction, a back gate electrode between the first and second word lines that is extended in the second direction, first and second active patterns between the first word line and the back gate electrode on the bit line, contact patterns connected to the first and second active patterns with data storage patterns respectively connected to the contact patterns such that each of the first and second active patterns comprises a single crystalline semiconductor material, and the back gate electrode comprises a first region comprising a first conductive material and a second region comprising a second conductive material different from the first conductive material as described by the applicant in claim 16. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KEVIN QUINTO/Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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Prosecution Timeline

Sep 07, 2023
Application Filed
Jan 03, 2026
Non-Final Rejection — §103, §112
Feb 10, 2026
Applicant Interview (Telephonic)
Feb 21, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12598732
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING MEMORY
2y 5m to grant Granted Apr 07, 2026
Patent 12598730
MEMORY DEVICE AND METHOD FOR FABRICATING SAME
2y 5m to grant Granted Apr 07, 2026
Patent 12581637
METHODS AND STRUCTURES FOR THREE-DIMENSIONAL DYNAMIC RANDOM-ACCESS MEMORY
2y 5m to grant Granted Mar 17, 2026
Patent 12575087
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Mar 10, 2026
Patent 12568613
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
86%
With Interview (+1.4%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 837 resolved cases by this examiner. Grant probability derived from career allow rate.

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