DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-7 & 9 in the reply filed on 12/28/2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 & 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the staircase section includes a first structure in which the row decoders are provided to overlap with each other in the stack direction” in lines 14-17. The limitation raises ambiguity as applicant’s Fig. 5 places the row decoders in the circuit section 52 and not in array chip/stacked body 51, which is contrary to the above limitation. Claim 1 appears to place the row decoders in the stacked body/array chip. It is further unclear how the row decoders are overlapping one another. The Examiner requests the applicant map said limitation to a specific drawing to help remove the ambiguity. Correction/clarification is required.
Claim 9 recites the limitation “a seventh staircase section” and “an eighth staircase section”. Said limitations raise ambiguity as there are no “second staircase section” to “sixth staircase section” in claims 7 & 5 from which claim 9 depends. Correction is required.
Claims 2-7 are rejected for being dependent on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As best understood, claims 1-2 & 5-7 & 9 are rejected under 35 U.S.C. 103 as being unpatentable over AHN et al. (US Pub. 2019/0214404) in view of FUTATSUYMA (US Pub. 2019/0371382).
Regarding claim 1, AHN teaches a semiconductor storage device comprising:
a stacked body in which a plurality of electrically conductive layers (GE-L to GE-U) is stacked with an insulating layer 210 interposed in between (see Fig. 11B below); and
a circuit section that is provided to overlap with the stacked body in a stack direction (see Fig. 11B below), wherein
the stacked body includes a memory section 370 in which a plurality of memory cells is disposed and a staircase section S1 in which the plurality of electrically conductive layers has stepped ends (see Fig. 11B below),
the circuit section includes a row decoder 32 that is electrically connected to the plurality of electrically conductive layers (Fig. 11B and Fig. 1),
the staircase section includes a first structure (see Fig. 11B below) in which the row decoders are provided to overlap with each other in the stack direction and a second structure different from the first structure (see the difference between the first and second structures in Fig. 11 below), and
the second structure has a greater step gap than a step gap of the first structure (see Fig. 11B below).
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AHN appears to teach a single row decoder and is silent on the use multiple row decoders. However, FUTATSUYAMA teaches multiple row decoders that overlap each other in the stack direction (see Fig. 1-3 & Fig. 7-8). This has the advantage of providing a more efficient layout and faster speed, reduced delay and lower power consumption. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of AHN with the multiple decoders, as taught by FUTATSUYAMA, so as to obtain an improved semiconductor device.
Regarding claim 2, the combination of AHN and FUTATSUYAMA teaches the semiconductor storage device according to 1, wherein the memory section (370 in AHN’s Fig. 1B & note memory section/layout in FUTATSUYAMA’s Fig. 7-8) includes a first memory section (S1 in AHN’s Fig. 11B and note annotation in FUTATSUYAMA’s Fig. 7 below) and a second memory section (S1 in AHN’s Fig. 11B and note annotation in FUTATSUYAMA’s Fig. 7 below), the staircase section includes a first staircase section and a second staircase section, the first staircase section being joined to the first memory section and including the first structure (AHN’s memory section 370 that includes staircase sections would be joined to FUTATSUYAMA’s circuit section as shown in Fig. 7 upon incorporation of F in AHN), the second staircase section being joined to the second memory section and including the first structure (AHN’s memory section 370 that includes staircase sections would be joined to FUTATSUYAMA’s circuit section as shown in Fig. 7 upon incorporation of F in AHN), the row decoders RD include a first row decoder and a second row decoder, the first row decoder being joined to the first staircase section, the second row decoder being joined to the second staircase section (see FUTATSUYAMA’s Fig. 7 below), and the first row decoder is provided to overlap with a first side of the memory section and the second row decoder is provided to overlap with a second side of the memory section, the second side being different from the first side (see FUTATSUYAMA’s Fig. 7 below and AHN’s Fig. 11B above).
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Regarding claim 5, the combination of AHN and FUTATSUYAMA teaches the semiconductor storage device according to claim 1, wherein the first structure is provided with a contact plug (284g in AHN’s Fig. 11B and C0 in FUTATSUYAMA’s Fig. 8) that is electrically joined to each of the row decoders RD (note contact plugs 284g in AHN’s Fig. 11B and contact plugs C0 in FUTATSUYAMA’s Fig. 8).
Regarding claim 6, the combination of AHN and FUTATSUYAMA teaches
6. The semiconductor storage device according to claim 5, wherein the memory cells include drains (AHN’s Fig. 11B and FUTATSUYAMA’s Fig. 8).
Regarding claim 7, the combination of AHN and FUTATSUYAMA teaches the semiconductor storage device according to claim 6, wherein the first memory section and the second memory section share a bit line that is joined to the drains (note bit line in AHN and FUTATSUYAMA’s Fig. 2).
Regarding claim 9, the combination of AHN and FUTATSUYAMA teaches the semiconductor storage device according to claim 7, wherein a seventh staircase section (S1 in AHN’s Fig. 11B) is provided between the first memory section and the second memory section (, the seventh staircase section being joined to the first memory section and including the second structure, and an eighth staircase section (S1 in AHN’s Fig. 11B) is provided between the first memory section and the second memory section, the eighth staircase section being joined to the second memory section and including the second structure (see annotations in AHN’s Fig. 11B above and FUTATSUYAMA’s Fig. 7 above).
Allowable Subject Matter
Claims 3-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM.
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818