DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Non-Final office action based on application 18/462,824 filed September 7, 2023. Claims 1-20 are currently pending and have been considered below.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Japan on September 26, 2022. It is noted, however, that applicant has not filed a certified copy of the JP2022-152406 application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 10-12, & 16-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang (Chinese Publication CN 116207179).
Regarding claim 1, Wang discloses a photodiode comprising:
A chip (Fig. 6, 1) including a main surface;
A first conductivity type first semiconductor region (2; Paragraph [0050]) formed at least in a surface layer portion of the main surface;
a trench structure (3) including a trench formed in the main surface to be located within the first semiconductor region, and a second conductivity type polysilicon (4; Paragraph [0050]) mechanically and electrically connected to the chip and located within the trench; and
a second conductivity type second semiconductor region (5; Paragraph [0051]) formed within the first semiconductor region along a wall surface of the trench structure and forming a pn junction, as a photodiode, with the first semiconductor region.
Regarding claim 2, Wang further discloses:
the second semiconductor region contains a second conductivity type impurity of a same type as a second conductivity type impurity of the polysilicon such as they can both have n-type conductivity (Paragraph [0051]).
Regarding claim 3, Wang further discloses:
the second semiconductor region has an impurity concentration lower than an impurity concentration of the polysilicon (Paragraph [0062]).
Regarding claim 10, Wang further discloses:
An insulating film (9) covering the main surface and a via electrode (10) electrically connected to the polysilicon within the insulating film.
Regarding claim 11, Wang further discloses:
the via electrode (10) is mechanically and electrically connected to the polysilicon at an interval from the second semiconductor region (Fig. 6).
Regarding claim 12, Wang further discloses:
the via electrode (10) has no mechanical connection to the second semiconductor region (5).
Regarding claim 16, Wang further discloses:
a second conductivity type contact region (7) formed in a surface layer portion of the first semiconductor region at an interval from the trench structure (Paragraph [0031]).
Regarding claim 17, Wang further discloses:
a light receiving region provided in the main surface; and
a region isolation structure (14) that electrically isolates the light receiving region from other regions, wherein the trench structure (3) is formed in the light receiving region, and wherein the second semiconductor region (5) is formed along the wall surface of the trench structure in the light receiving region.
Regarding claim 18, Wang further discloses:
a plurality of light receiving regions (Fig. 5 & 14) provided in the main surface, wherein the trench structure (3) is formed in each of the light receiving regions, and wherein the second semiconductor region (5) is formed along the wall surface of the trench structure in each of the light receiving regions.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-7 & 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (Chinese Publication CN 116207179) in view of Katayama (US Patent 8,410,533).
Regarding claim 5-7 & 13-15 Wang disclose all of the limitations of claim 1 (addressed above). Wang does not disclose a second conductivity type impurity region which has a higher impurity concentration within the polysilicon. However Katayama discloses a semiconductor device comprising:
A photodiode region (Fig. 3, 20) wherein the photodiode includes a first diffusion region (42), a second diffusion region (56), a third high impurity diffusion region (70; Col. 4, Lines 29-32) within the second diffusion region.
the impurity region (70) is formed in a surface layer portion of the silicon substrate (30) at an interval from a bottom wall of the trench.
the impurity region (70) is formed at an interval from a middle portion of a depth range of the trench to an opening side of the trench.
A via electrode (85) forming an ohmic contact with the impurity region (70) and a multilayer wiring (not shown; Col. 8, Lines 31-34) connected to the via electrode (85) on an insulating film (80)
It would have been obvious to those having ordinary skill in the art at the time of invention to form the high impurity region in the second diffusion region because it will serve to form a photodiode device having reduced leakage current thereby increasing the sensitivity of the photodiode (Col. 1, Lines 20-29). Further the wiring coupled to the via electrode will establish an electrical path to and from the photodiode diffusion regions.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (Chinese Publication CN 116207179) in view of Kanematsu (Japanese Reference 2006222116).
Regarding claim 19, Wang discloses a photodiode comprising:
preparing a wafer (Fig. 8-13, 1) including a main surface and including a first conductivity type first semiconductor region (2) at least in a surface layer portion of the main surface;
forming a trench (3) in the main surface to be located within the first semiconductor region;
burying a second conductivity type polysilicon (4) in the trench to be mechanically and electrically connected to the wafer; and
forming a second conductivity type second semiconductor region (5) forming a pn junction, as a photodiode, with the first semiconductor region.
Wang does not disclose the second conductivity type second semiconductor region is formed by diffusing a second conductivity type impurity into the first semiconductor region. However Kanematsu disclose a light receiving element comprising:
A light receiving element (Fig. 2-10) including a trench (22) wherein a doped polysilicon material (25; Paragraph [0029]) fills the trench and a second conductivity type second semiconductor region is formed by diffusing impurities from the polysilicon film (Paragraph [0032]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the second semiconductor region by diffusing impurities form the polysilicon film in the trench because it will allow the conductivity of the polysilicon film serving as a conductive wiring of the photodiode to be stabilized and suppress influence of an adjacent semiconductor region (Paragraph [0032]).
Regarding claim 20, Wang further discloses:
the polysilicon remains as a polar electrode for the second semiconductor region after the act of forming the second semiconductor region (Paragraph [0060]).
Allowable Subject Matter
Claims 4, 8-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 4 is considered allowable because none of the prior art either alone or in combination discloses the second semiconductor region has a concentration gradient that gradually decreases starting from the polysilicon.
Claim 8 is considered allowable because none of the prior art either alone or in combination discloses the impurity region forms a concentration gradient that gradually decreases from an inner portion of the polysilicon toward a peripheral portion of the polysilicon within the trench.
Claim 9 is considered allowable because none of the prior art either alone or in combination discloses the impurity region contains a second conductivity type impurity of a type different from a second conductivity type impurity of the polysilicon.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM.
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/BRANDON C FOX/Examiner, Art Unit 2818
/DAVID VU/Primary Examiner, Art Unit 2818
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