Attorney’s Docket Number: 8947-001908-US
Filing Date: 09/07/2023
Claimed Foreign Priority Date: 02/10/2023 (KR10-2023-0017899)
Applicant: Yoo
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the application filed on 09/07/2023.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The application serial no. 18/462,851 filed on 09/07/2023 has been entered. Pending in this Office Action are claims 1-20.
Drawings
The drawings are objected to because of severe inconsistencies between Fig. 4 and its sectional views along A-A’ and B-B’, as illustrated respectively in Figs. 5A and 5B. Applicant is requested to correct all inconsistencies in the arrangements of M1, M2, AC, and GCs. For example:
- along A-A’, a line M1_I is depicted in Fig. 4 as being continuous, overlapped by four M2_I lines, and without any underlying gate contact GC to gates GE, while Fig. 5A differently depicts the line M1_I as segmented, overlapped by a different number of M2_I lines, and with a plurality of underlying gate contacts GC.
- along B-B’, a line M1_I is depicted in Fig. 4 as extending on the right half of the layout, overlapped by two M2_I lines, and with an underlying gate contact GC to middle gate GE, while Fig. 5B differently depicts the line M1_I as extending across the entire layout, overlapped by a different number of M2_I lines, without any underlying gate contact GC to middle gate GE, and connected to an AC contact instead.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
- Par. [0042]: amend to --The first source/drain patterns SD1 may be impurity regions of a first conductivity type (e.g., p-type)--, for consistency with AP1 being provided on a PMOSFET region, as disclosed in Par. [0038].
- Par. [0043]: amend to -- The second source/drain patterns SD2 may be impurity regions of a second conductivity type (e.g., n-type)--, for consistency with AP2 being provided on a NMOSFET region, as disclosed in Par. [0038].
Appropriate corrections are required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 6-7 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Claim 6 recites “an intermediate layer” at L. 2. However, claim 2, from which claim 6 depends, already recites “an intermediate layer” feature at L. 2, and it is unclear if two recitations of “an intermediate layer” are directed to a same or different features, thus rendering the claim indefinite. For the purpose of examination, the claim will be construed as reciting -- The semiconductor device of claim 2, further comprising:
Claim 7 depends of claim 6, thus inherits the deficiencies identified supra.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (US2021/0098583).
Regarding Claim 1, Tsai (see, e.g., Figs. 17-18) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., substrate 20)
- a channel pattern on the substrate (e.g., vertical stack of semiconductor channel layers 28), the channel pattern including a plurality of semiconductor patterns, the plurality of semiconductor patterns being vertically stacked and spaced apart from each other, and a lowermost one of the plurality of semiconductor patterns being a first semiconductor pattern
- a source/drain pattern (e.g., epitaxial source/drain region 38) connected to the plurality of semiconductor patterns
- an interlayer insulating layer (e.g., inter-layer dielectric 40) on the source/drain pattern
- an active contact (e.g., contact comprising barrier layer 54 and metal 56) penetrating the interlayer insulating layer and being electrically connected to the source/drain pattern, wherein
- a level of a bottommost surface of the active contact is lower than a top surface of the first semiconductor pattern (see, e.g., Fig. 18).
Regarding Claim 2, Tsai (see, e.g., Fig. 18) shows an intermediate layer (e.g., silicide 52) between the active contact and the source/drain pattern.
Regarding Claim 3, Tsai (see, e.g., Fig. 18) shows that:
- the active contact comprises a conductive pattern (e.g., metal 56) and a barrier pattern (e.g., barrier layer 54) enclosing the conductive pattern
- the barrier pattern is between the intermediate layer and the conductive pattern.
Regarding Claim 4, Tsai (see, e.g., Fig. 18) shows that a mean thickness of the intermediate layer (e.g., 52) is smaller than a mean thickness of the source/drain pattern (e.g., 38).
Regarding Claim 5, Tsai (see, e.g., Fig. [0076]) disclosed that silicide 52 is a silicide of Ti, Ni, Co, or the like. Therefore, Tsai shows that the intermediate layer (e.g., 52) comprises at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, or cobalt-silicide.
Claims 1-2, 4-5, and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al. (US2023/0187508).
Regarding Claim 1, Xie (see, e.g., Figs. 1 and 13) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., substrate 102)
- a channel pattern on the substrate (e.g., vertical stack of semiconductor channel layers 106b), the channel pattern including a plurality of semiconductor patterns, the plurality of semiconductor patterns being vertically stacked and spaced apart from each other, and a lowermost one of the plurality of semiconductor patterns being a first semiconductor pattern
- a source/drain pattern (e.g., source/drain region 116) connected to the plurality of semiconductor patterns
- an interlayer insulating layer (e.g., interlayer dielectric layer 126) on the source/drain pattern
- an active contact (e.g., contact comprising high conductance metal 134) penetrating the interlayer insulating layer and being electrically connected to the source/drain pattern, wherein
- a level of a bottommost surface of the active contact is lower than a top surface of the first semiconductor pattern (see, e.g., Fig. 13A).
Regarding Claim 2, Xie (see, e.g., Par [0101]) shows an intermediate layer (e.g., metal/metal-silicide layer 132) between the active contact and the source/drain pattern.
Regarding Claim 4, Xie (see, e.g., Fig. 13a) shows that a mean thickness of the intermediate layer (e.g., 132) is smaller than a mean thickness of the source/drain pattern (e.g., 116).
Regarding Claim 5, Xie (see, e.g., Fig. [0101]) disclosed that metal/metal-silicide layer 132 is a silicide of titanium (Ti). Therefore, Tsai shows that the intermediate layer (e.g., 132) comprises at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, or cobalt-silicide.
Regarding Claim 11, Xie (see, e.g., Figs. 1 and 13) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., substrate 102) including an active region (see, e.g., Fig. 13B: region delimited by shallow trench isolation regions 101)
- a source/drain pattern (e.g., source/drain region 116) on the active region, the source/drain pattern including a first inner surface, the source/drain pattern being among a plurality of source/drain patterns
- channel patterns (e.g., vertical stacks of semiconductor channel layers 106b) on the active region and connected to the plurality of source/drain patterns, each of the channel patterns including a plurality of semiconductor patterns, the plurality of semiconductor patterns being vertically stacked and spaced apart from each other, and a lowermost one of the semiconductor patterns being a first semiconductor pattern
- gate electrodes (e.g., gate structures 128) on the channel patterns, respectively
- an active contact (e.g., contact comprising high conductance metal 134) electrically connected to the source/drain pattern
- an intermediate layer (e.g., metal/metal-silicide layer 132) on the first inner surface, wherein
- the active contact is on the intermediate layer, and
- a level of a bottom surface of the first inner surface is lower than a top surface of the first semiconductor pattern (see, e.g., Fig. 13A).
Claims 1-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US2022/0359678 hereinafter Kim-678).
Regarding Claim 1, Kim-678 (see, e.g., Figs. 4-7) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., substrate 100)
- a channel pattern on the substrate (e.g., channel pattern CH1 or CH2), the channel pattern including a plurality of semiconductor patterns (e.g., SP1-SP3), the plurality of semiconductor patterns being vertically stacked and spaced apart from each other, and a lowermost one of the plurality of semiconductor patterns being a first semiconductor pattern (e.g., SP1)
- a source/drain pattern (e.g., source/drain pattern SD1 or SD2) connected to the plurality of semiconductor patterns
- an interlayer insulating layer (e.g., interlayer insulating layer 110) on the source/drain pattern
- an active contact (e.g., active contact AC comprising FM,BM) penetrating the interlayer insulating layer and being electrically connected to the source/drain pattern, wherein
- a level of a bottommost surface of the active contact is lower than a top surface of the first semiconductor pattern (see, e.g., Figs. 6-7).
Regarding Claim 2, Kim-678 (see, e.g., Figs. 5-7) shows an intermediate layer (e.g., silicide layer SC) between the active contact and the source/drain pattern.
Regarding Claim 3, Kim-678 (see, e.g., Figs. 5-7) shows that:
- the active contact comprises a conductive pattern (e.g., conductive pattern FM) and a barrier pattern (e.g., barrier pattern BM) enclosing the conductive pattern
- the barrier pattern is between the intermediate layer and the conductive pattern.
Regarding Claim 4, Kim-678 (see, e.g., Figs. 5-7) shows that a mean thickness of the intermediate layer (e.g., SC) is smaller than a mean thickness of the source/drain pattern (e.g., SD1 or SD2).
Regarding Claim 5, Kim-678 (see, e.g., Par. [0121]) shows that the intermediate layer (e.g., SC) comprises at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, or cobalt-silicide.
Regarding Claim 6, Kim-678 (see, e.g., Figs. 6A-B) shows:
- an intermediate layer (e.g., silicide layer SC), wherein
- the source/drain pattern is in a PMOSFET region of the semiconductor device (e.g., SD1 in PMOSFET region PR1), the source/drain pattern comprises a first layer (e.g., BFL1) and a second layer (e.g., MAL1) on the first layer, the second layer comprises a concave top surface (see, e.g., Fig. 6B)
- the intermediate layer is between the concave top surface of the second layer and the active contact
- the intermediate layer is between an inner surface of the first layer and the active contact.
Regarding Claim 7, Kim-678 (see, e.g., Par. [0067]-[0068]) discloses that a concentration of the germanium (Ge) in BFL1 may range from 0 at % to 10 at %, and a concentration of the germanium (Ge) in MAL1 may range from 30 at % to 70 at %. Therefore, Kim-678 shows that a germanium concentration of the second layer (e.g., MAL1) is higher than a germanium concentration of the first layer (e.g., BFL1).
Regarding Claims 8-10, Kim-678 discloses that:
- each of BFL1 and MAL1 contain impurities (e.g., boron, gallium, or indium) allowing SD1 to have a p-type, and that the impurity concentration of MAL1 is higher than BFL1 (see, e.g., Par. [0069])
- each of BFL2 and MAL2 contain impurities (e.g., phosphorus, arsenic, or antimony) allowing SD2 to have an n-type, and that the impurity concentration of MAL2 is higher than BFL2 (see, e.g., Par. [0079])
Therefore, Kim-678 shows:
- Claim 8: wherein a concentration of an impurity in the source/drain pattern (e.g., SD1 or SD2) increases as a distance to the active contact decreases (e.g., concentration of impurities in MAL1 is higher than BFL1, MAL1 being at least closer to AC than BFL1 along D4; or concentration of impurities in MAL2 is higher than BFL2, MAL2 being at least closer to AC than BFL2 along D4).
- Claim 9: wherein the source/drain pattern is in a PMOSFET region of the semiconductor device (SD1 in PMOSFET region PR1), and the impurity comprises at least one of boron (B), gallium (Ga), or indium (In).
- Claim 10: wherein the source/drain pattern is in an NMOSFET region of the semiconductor device (SD2 in NMOSFET region PR2), and the impurity comprises at least one of arsenic (As), phosphorus (P), or antimony (Sb).
Regarding Claim 11, Kim-678 (see, e.g., Figs. 4-7) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., substrate 100) including an active region (see, e.g., active pattern AP1 in PR1 or AP2 in PR2)
- a source/drain pattern (e.g., source/drain pattern SD1 or SD2) on the active region, the source/drain pattern including a first inner surface, the source/drain pattern being among a plurality of source/drain patterns
- channel patterns (e.g., channel pattern CH1 or CH2) on the active region and connected to the plurality of source/drain patterns, each of the channel patterns including a plurality of semiconductor patterns (e.g., SP1-SP3), the plurality of semiconductor patterns being vertically stacked and spaced apart from each other, and a lowermost one of the semiconductor patterns being a first semiconductor pattern (e.g., SP1)
- gate electrodes (e.g., gate electrodes GE) on the channel patterns, respectively
- an active contact (e.g., active contact AC comprising FM,BM) electrically connected to the source/drain pattern
- an intermediate layer (e.g., silicide layer SC) on the first inner surface, wherein
- the active contact is on the intermediate layer, and
- a level of a bottom surface of the first inner surface is lower than a top surface of the first semiconductor pattern (see, e.g., Figs. 6-7).
Regarding Claims 12-14, Kim-678 discloses that:
- each of BFL1 and MAL1 contain impurities (e.g., boron, gallium, or indium) allowing SD1 to have a p-type, and that the impurity concentration of MAL1 is higher than BFL1 (see, e.g., Par. [0069])
- each of BFL2 and MAL2 contain impurities (e.g., phosphorus, arsenic, or antimony) allowing SD2 to have an n-type, and that the impurity concentration of MAL2 is higher than BFL2 (see, e.g., Par. [0079])
Therefore, Kim-678 shows:
- Claim 12: wherein a concentration of an impurity in the source/drain pattern (e.g., SD1 or SD2) increases as a distance to the active contact decreases (e.g., concentration of impurities in MAL1 is higher than BFL1, MAL1 being at least closer to AC than BFL1 along D4; or concentration of impurities in MAL2 is higher than BFL2, MAL2 being at least closer to AC than BFL2 along D4).
- Claim 13: wherein the source/drain pattern is in a PMOSFET region of the semiconductor device (SD1 in PMOSFET region PR1), and the impurity comprises at least one of boron (B), gallium (Ga), or indium (In).
- Claim 14: wherein the source/drain pattern is in an NMOSFET region of the semiconductor device (SD2 in NMOSFET region PR2), and the impurity comprises at least one of arsenic (As), phosphorus (P), or antimony (Sb).
Regarding Claim 15, Kim-678 (see, e.g., Figs. 6A-B) shows:
- the source/drain pattern is in a PMOSFET region of the semiconductor device (e.g., SD1 in PMOSFET region PR1), the source/drain pattern comprises a first layer (e.g., BFL1) and a second layer (e.g., MAL1) on the first layer, the second layer has a concave top surface (see, e.g., Fig. 6B)
- the intermediate layer is between the concave top surface of the second layer and the active contact
- the intermediate layer is between an inner surface of the first layer and the active contact.
Furthermore, Kim-678 (see, e.g., Par. [0067]-[0068]) discloses that a concentration of the germanium (Ge) in BFL1 may range from 0 at % to 10 at %, and a concentration of the germanium (Ge) in MAL1 may range from 30 at % to 70 at %. Therefore, Kim-678 shows that a germanium concentration of the second layer (e.g., MAL1) is higher than a germanium concentration of the first layer (e.g., BFL1).
Claims 1-4, 6, 8, 10-12, and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US2023/0011153 hereinafter Kim-153).
Regarding Claim 1, Kim-153 (see, e.g., Figs. 1-4 or 31-32) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., substrate 100)
- a channel pattern on the substrate (e.g., vertical stack of semiconductor nanosheets NW1 or NW1x), the channel pattern including a plurality of semiconductor patterns, the plurality of semiconductor patterns being vertically stacked and spaced apart from each other, and a lowermost one of the plurality of semiconductor patterns being a first semiconductor pattern
- a source/drain pattern (e.g., source/drain region 120 or 520/620) connected to the plurality of semiconductor patterns
- an interlayer insulating layer (e.g., interlayer insulating layer 140) on the source/drain pattern
- an active contact (e.g., source/drain contact 150 or 550/650) penetrating the interlayer insulating layer and being electrically connected to the source/drain pattern, wherein
- a level of a bottommost surface of the active contact is lower than a top surface of the first semiconductor pattern (see, e.g., Figs. 2 or 32).
Regarding Claim 2, Kim-153 (see, e.g., Par [0028]) shows an intermediate layer (e.g., silicide layer 160 or 560/660) between the active contact and the source/drain pattern.
Regarding Claim 3, Kim-153 (see, e.g., Figs. 2 or 32) shows that:
- the active contact comprises a conductive pattern (e.g., contact filling layer 152 or 552/652) and a barrier pattern (e.g., contact barrier layer 151 or 551/651) enclosing the conductive pattern
- the barrier pattern is between the intermediate layer and the conductive pattern.
Regarding Claim 4, Kim-153 (see, e.g., Figs. 2 or 32) shows that a mean thickness of the intermediate layer (e.g., 160 or 560/660) is smaller than a mean thickness of the source/drain pattern (e.g., 120 or 520/620).
Regarding Claim 6, Kim-153 (see, e.g., Fig. 32) shows:
- an intermediate layer (e.g., silicide layer 660), wherein
- the source/drain pattern is in a PMOSFET region of the semiconductor device (e.g., 620 is in PMOS region II), the source/drain pattern comprises a first layer (e.g., 621) and a second layer (e.g., 622) on the first layer, the second layer comprises a concave top surface
- the intermediate layer is between the concave top surface of the second layer and the active contact
- the intermediate layer is between an inner surface of the first layer and the active contact.
Regarding Claim 8, Kim-153 (see, e.g., Figs. 2 or 32, and Par. [0063]-[0066],[0140]-[0145]) discloses that the semiconductor device disposed in each of the NMOS region I and PMOS region II has the same structure as the semiconductor device of FIG. 2., and that source/drain region 120 or 520/620 comprises a first doping layer 121 or 521/621 doped with a first impurity at a first concentration, and a second doping layer 122 or 522/622 (closer to contact 150 or 550/650) doped with the first impurity at a second concentration higher than the first concentration. Therefore, Kim-153 shows that a concentration of an impurity in the source/drain pattern increases as a distance to the active contact decreases.
Regarding Claim 10, Kim-153 (see, e.g., Fig. 32 and Par. [0063]-[0066],[0140]-[0145]) shows that the source/drain pattern is in an NMOSFET region of the semiconductor device (e.g., 520 is in NMOS region I), and the impurity comprises at least one of arsenic (As), phosphorus (P), or antimony (Sb).
Regarding Claim 11, Kim-153 (see, e.g., Figs. 1-4 or 31-32) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., substrate 100) including an active region (see, e.g., active pattern Fx delimited by field insulating layer 105)
- a source/drain pattern (e.g., source/drain region 120 or 520/620) on the active region, the source/drain pattern including a first inner surface, the source/drain pattern being among a plurality of source/drain patterns
- channel patterns (e.g., vertical stacks of semiconductor nanosheets NW1 or NW1x) on the active region and connected to the plurality of source/drain patterns, each of the channel patterns including a plurality of semiconductor patterns, the plurality of semiconductor patterns being vertically stacked and spaced apart from each other, and a lowermost one of the semiconductor patterns being a first semiconductor pattern
- gate electrodes (e.g., gate electrodes G1 or G11-G14) on the channel patterns, respectively
- an active contact (e.g., source/drain contact 150 or 550/650) electrically connected to the source/drain pattern
- an intermediate layer (e.g., silicide layer 160 or 560/660) on the first inner surface, wherein
- the active contact is on the intermediate layer, and
- a level of a bottom surface of the first inner surface is lower than a top surface of the first semiconductor pattern (see, e.g., Figs. 2 or 32).
Regarding Claim 12, Kim-153 (see, e.g., Figs. 2 or 32, and Par. [0063]-[0066],[0140]-[0145]) discloses that the semiconductor device disposed in each of the NMOS region I and PMOS region II has the same structure as the semiconductor device of FIG. 2., and that source/drain region 120 or 520/620 comprises a first doping layer 121 or 521/621 doped with a first impurity at a first concentration, and a second doping layer 122 or 522/622 (closer to contact 150 or 550/650) doped with the first impurity at a second concentration higher than the first concentration. Therefore, Kim-153 shows that a concentration of an impurity in the source/drain pattern increases as a distance to the active contact decreases.
Regarding Claim 14, Kim-153 (see, e.g., Fig. 32 and Par. [0063]-[0066],[0140]-[0145]) shows that the source/drain pattern is in an NMOSFET region of the semiconductor device (e.g., 520 is in NMOS region I), and the impurity comprises at least one of arsenic (As), phosphorus (P), or antimony (Sb).
Claims 1-5, 11, and 16-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (US2023/0115743 hereinafter Lee-743).
Regarding Claim 1, Lee-743 (see, e.g., Figs. 1-2) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., substrate 100)
- a channel pattern on the substrate (e.g., channel pattern CH2), the channel pattern including a plurality of semiconductor patterns (e.g., semiconductor pattern SP1-SP3), the plurality of semiconductor patterns being vertically stacked and spaced apart from each other, and a lowermost one of the plurality of semiconductor patterns being a first semiconductor pattern (e.g., SP1)
- a source/drain pattern (e.g., source/drain pattern SD2) connected to the plurality of semiconductor patterns
- an interlayer insulating layer (e.g., interlayer dielectric layer 110) on the source/drain pattern
- an active contact (e.g., active contact AC2) penetrating the interlayer insulating layer and being electrically connected to the source/drain pattern, wherein
- a level of a bottommost surface of the active contact is lower than a top surface of the first semiconductor pattern (see, e.g., Fig. 2B).
Regarding Claim 2, Lee-743 (see, e.g., Fig. 2B) shows an intermediate layer (e.g., silicide pattern SC2) between the active contact and the source/drain pattern.
Regarding Claim 3, Lee-743 (see, e.g., Fig. 2B) shows that:
- the active contact comprises a conductive pattern (e.g., conductive pattern FM) and a barrier pattern (e.g., barrier pattern BM) enclosing the conductive pattern
- the barrier pattern is between the intermediate layer and the conductive pattern.
Regarding Claim 4, Lee-743 (see, e.g., Fig. 2B) shows that a mean thickness of the intermediate layer (e.g., SC2) is smaller than a mean thickness of the source/drain pattern (e.g., SD2).
Regarding Claim 5, Lee-743 (see, e.g., Par. [0060]) shows that the intermediate layer (e.g., SC2) comprises at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, or cobalt-silicide.
Regarding Claim 11, Lee-743 (see, e.g., Figs. 1-2) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., substrate 100) including an active region (see, e.g., active pattern AP2 in NR)
- a source/drain pattern (e.g., source/drain pattern SD2) on the active region, the source/drain pattern including a first inner surface, the source/drain pattern being among a plurality of source/drain patterns
- channel patterns (e.g., channel patterns CH2) on the active region and connected to the plurality of source/drain patterns, each of the channel patterns including a plurality of semiconductor patterns (e.g., SP1-SP3), the plurality of semiconductor patterns being vertically stacked and spaced apart from each other, and a lowermost one of the semiconductor patterns being a first semiconductor pattern (e.g., SP1)
- gate electrodes (e.g., gate electrodes GE) on the channel patterns, respectively
- an active contact (e.g., active contact AC2 comprising FM,BM) electrically connected to the source/drain pattern
- an intermediate layer (e.g., silicide layer SC2) on the first inner surface, wherein
- the active contact is on the intermediate layer, and
- a level of a bottom surface of the first inner surface is lower than a top surface of the first semiconductor pattern (see, e.g., Fig. 2B).
Regarding Claim 16, Lee-743 (see, e.g., Figs. 1-2) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., substrate 100) including an active region (see, e.g., active region NR)
- a device isolation layer (e.g., device isolation layer ST) on the active region, the device isolation layer defining an active pattern (e.g., active pattern AP2) on the active region
- a channel pattern (e.g., channel pattern CH2) on the active pattern, the channel pattern including a plurality of semiconductor patterns (e.g., SP1-SP3), the plurality of semiconductor patterns being vertically stacked and spaced apart from each other, a lowermost one of the plurality of semiconductor patterns being a first semiconductor pattern (e.g., SP1)
- a source/drain pattern (e.g., source/drain pattern SD2) on the active pattern
- a gate electrode (e.g., gate electrode GE) on the plurality of semiconductor patterns, the gate electrode including a portion interposed between adjacent semiconductor patterns among the plurality of semiconductor patterns
- a gate insulating layer (e.g., gate dielectric layer GI) between the adjacent semiconductor patterns and the portion of the gate electrode
- an inner spacer (e.g., inner spacers IP) between the gate insulating layer and the source/drain pattern
- a gate spacer (e.g., gate spacer GS) on a side surface of the gate electrode
- a gate capping pattern (e.g., gate capping pattern GP) on a top surface of the gate electrode
- an interlayer insulating layer (e.g., interlayer dielectric layer 120) on the gate capping pattern
- an active contact (e.g., conductive pattern FM) penetrating the interlayer insulating layer and being electrically connected to the source/drain pattern
- a metal layer (e.g., metal barrier pattern BM) between the active contact and the source/drain pattern
- a gate contact (e.g., gate contacts GC) penetrating the interlayer insulating layer and the gate capping pattern, the gate contact being electrically connected to the gate electrode
- a first metal layer (e.g., metal layer M1) on the interlayer insulating layer, the first metal layer including a power line (e.g., power line M1_R) and a first interconnection line (e.g., line M1_I), the power line and the first interconnection line being electrically connected to the active contact and gate contact (e.g., AC2 and GC, respectively) (see, e.g., Figs. 2C-2D)
- a second metal layer (e.g., metal layer M2) on the first metal layer, the second metal layer includes second interconnection lines (e.g., lines M2_I) electrically connected to the first metal layer (see, e.g., Figs. 2C-2D)
- a level of a lowermost portion of the active contact (e.g., AC2) is lower than a level of a top surface of the first semiconductor pattern (e.g., SP1) (see, e.g., Fig. 2B)
Regarding Claim 17, Lee-743 (see, e.g., Fig. 2B) shows an intermediate layer (e.g., silicide layer SC2) between the active contact and the source/drain pattern.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US2023/0011153 hereinafter Kim-153) in view of Xie et al. (US2023/0187508).
Regarding Claim 9, Kim-153 (see, e.g., Fig. 32 and Par. [0063]-[0066],[0140]-[0145]) shows that the source/drain pattern is in an PMOSFET region of the semiconductor device (e.g., 620 is in PMOS region II). However, Kim-153 is silent about the impurity comprising at least one of boron (B), gallium (Ga), or indium (In).
Xie (see, e.g., Par. [0085]), on the other hand and in the same filed of endeavor, teaches that suitable dopants for source/drain regions 116 include, for example, an n-type dopant selected from a group of phosphorus (P), arsenic (As) and antimony (Sb), or a p-type dopant selected from a group of boron (B), gallium (Ga), indium (In).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the impurity comprising at least one of boron (B), gallium (Ga), or indium (In) in the structure of Kim-153, because it is know in the semiconductor art that such impurities are suitable for p-type dopants for doping the S/D region of a PMOS, as suggested by Xie, and selecting known impurities based on their suitability for their intended use would have been obvious to the skilled artisan. See, Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Regarding Claim 13, Kim-153 (see, e.g., Fig. 32 and Par. [0063]-[0066],[0140]-[0145]) shows that the source/drain pattern is in an PMOSFET region of the semiconductor device (e.g., 620 is in PMOS region II). However, Kim-153 is silent about the impurity comprising at least one of boron (B), gallium (Ga), or indium (In). Also, see comments stated above in Par. 62-63 with regards to Claim 9, which are considered repeated here.
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US2022/0319907 hereinafter Lee-907) in view of Kim et al. (US2022/0359678 hereinafter Kim-678).
Regarding Claim 16, Lee-907 (see, e.g., Figs. 1 and 18) shows most aspects of the instant invention, including a semiconductor device, comprising:
- a substrate (e.g., substrate 100) including an active region (see, e.g., active region NR)
- a device isolation layer (e.g., device isolation layer ST) on the active region, the device isolation layer defining an active pattern (e.g., active pattern AP2) on the active region
- a channel pattern (e.g., channel pattern CH2) on the active pattern, the channel pattern including a plurality of semiconductor patterns (e.g., SP1-SP3), the plurality of semiconductor patterns being vertically stacked and spaced apart from each other, a lowermost one of the plurality of semiconductor patterns being a first semiconductor pattern (e.g., SP1)
- a source/drain pattern (e.g., source/drain pattern SD2) on the active pattern
- a gate electrode (e.g., gate electrode GE) on the plurality of semiconductor patterns, the gate electrode including a portion interposed between adjacent semiconductor patterns among the plurality of semiconductor patterns
- a gate insulating layer (e.g., gate dielectric layer GI) between the adjacent semiconductor patterns and the portion of the gate electrode
- an inner spacer (e.g., inner spacers IP) between the gate insulating layer and the source/drain pattern
- a gate spacer (e.g., gate spacer GS) on a side surface of the gate electrode
- a gate capping pattern (e.g., gate capping pattern GP) on a top surface of the gate electrode
- an interlayer insulating layer (e.g., interlayer dielectric layer 120) on the gate capping pattern
- an active contact (e.g., conductive pattern FM) penetrating the interlayer insulating layer and being electrically connected to the source/drain pattern
- a metal layer (e.g., metal barrier pattern BM) between the active contact and the source/drain pattern
- a gate contact (e.g., gate contacts GC) penetrating the interlayer insulating layer and the gate capping pattern, the gate contact being electrically connected to the gate electrode
- a first metal layer (e.g., metal layer M1) on the interlayer insulating layer, the first metal layer including a power line (e.g., power line MPR2) and a first interconnection line (e.g., line MIx), the power line and the first interconnection line being electrically connected to the active contact and gate contact (e.g., AC and GC, respectively) (see, e.g., Figs. 18C-18D)
- a second metal layer (e.g., metal layer M2) on the first metal layer, the second metal layer includes second interconnection lines (e.g., lines M2_I) electrically connected to the first metal layer (see, e.g., Figs. 18C-18D)
However, Lee-907 does not show that a level of a lowermost portion of the active contact is lower than a level of a top surface of the first semiconductor pattern. Kim-678 (see, e.g., Fig. 7A and Par. [0163]), on the other hand and in the same field of endeavor, teaches a semiconductor device wherein active contact AC can be formed with a deep buried portion BCP2, such that a level of a lowermost portion of the active contact AC is lower than a level of a top surface of the first semiconductor pattern SP1, to increase a contact area between the source/drain pattern SD2 and the active contact AC, thus reducing the electric resistance therebetween and improving the electric characteristics of the semiconductor device.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a level of a lowermost portion of the active contact as claimed in the structure of Lee-907, as taught by Kim-678, to increase a contact area between the source/drain pattern and the active contact, thus reducing the electric resistance therebetween and improving the electric characteristics of the semiconductor device.
Regarding Claim 17, Lee-907 (see, e.g., Fig. 18) shows an intermediate layer (e.g., silicide layer SC) between the active contact and the source/drain pattern. Additionally, Kim-678 teaches a silicide layer SC between AC and SD2.
Regarding Claims 18-20, Kim-678 teaches that:
- each of BFL1 and MAL1 contain impurities (e.g., boron, gallium, or indium) allowing SD1 to have a p-type, and that the impurity concentration of MAL1 is higher than BFL1 (see, e.g., Par. [0069])
- each of BFL2 and MAL2 contain impurities (e.g., phosphorus, arsenic, or antimony) allowing SD2 to have an n-type, and that the impurity concentration of MAL2 is higher than BFL2 (see, e.g., Par. [0079])
Therefore, Kim-678 teaches:
- Claim 18: wherein a concentration of an impurity in the source/drain pattern (e.g., SD1 or SD2) increases as a distance to the active contact decreases (e.g., concentration of impurities in MAL1 is higher than BFL1, MAL1 being at least closer to AC than BFL1 along D4; or concentration of impurities in MAL2 is higher than BFL2, MAL2 being at least closer to AC than BFL2 along D4).
- Claim 19: wherein the source/drain pattern is in a PMOSFET region of the semiconductor device (SD1 in PMOSFET region PR1), and the impurity comprises at least one of boron (B), gallium (Ga), or indium (In).
- Claim 20: wherein the source/drain pattern is in an NMOSFET region of the semiconductor device (SD2 in NMOSFET region PR2), and the impurity comprises at least one of arsenic (As), phosphorus (P), or antimony (Sb).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose GAA transistors with S/D contact arrangements or metal wiring layers having some aspects similar to the instant inventions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814