DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is response to Application 18/462,883 filed on 09/07/2023. Claims 1-20 are pending in the office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claims 1, 10, and 16: recited the limitation “prohibition region” which is “surrounding the through-via region in a plan view” and “a power gating cell in the prohibition region” but unclear the role of “a prohibition region” and “a power gating cell” in this structure, they appear as listed elements without functioning or activity of the claim.
As per claim 2-9, 11-15, and 17-20 are also rejected because are depended directly or indirectly to claims 1, 10, and 16, respectively.
Examiner notes: if the feature or limitation recited of claims 7, 13, and 17 incorporate into the independent claims 1, 10, and 16 that would address the above issue.
Prior Arts
Lee et al., (U.S. Pat. 7,687,311)
Lee teaches an integrated circuit device (‘311, fig. 1-20 and also see col. 1, ll. 25-26, 3D IC) comprising:
a first chip (‘311, col. 1, ll. 27-31, two dies (i.e., first chip and second chip) are bonded together and stacked on top each other, hence, include first chip); and
a second chip on the first chip (‘311, col. 1, ll. 27-31, two dies (i.e., first chip and second chip) are bonded together and stacked on top each other);
wherein the first chip (‘311, col. 1, ll. 27-31) comprises:
a first substrate (‘331, fig. 1-20, first substrate 112) comprising a through-via region (‘311, fig. 1-20, through via region 103), and a device region (‘311, fig. 1-20, electrical circuitry 113 and contacts 118);
a through-via in the through-via region and in the first substrate (‘311, fig. 1-20, through via 104a in the through-via region 103 and in the first substrate 112); and
wherein the second chip (‘311, col. 1, ll. 27-31) comprises:
a second substrate (‘331, fig. 7-20, second substrate 204); and
a second logic block on the second substrate (‘331, col. 5, ll. 50-51), wherein the second logic block is configured to receive power and/or signals through the through-via (‘331, col. 5, ll. 52-60, transfer of electrical signal between the conductive bump 202 and the corresponding TSV 104, and col. 6, ll. 50-55).
Lee does not teach a prohibition region surrounding the through-via region in a plan view and a power gating cell in the prohibition region.
Nakayama et al., (U.S. Pat. 6,691,296)
Nakayama teaches a power/ground layer detecting unit detects at least one layer, among power and ground layers, to which the detected power and/or ground terminals are connected. A layer detecting unit specifies a layer, among the detected layers, that is nearest to a signal layer on which the conductor is placed. A prohibition area (region) generating unit generates a via prohibition area on the specified layer. As a result, vias are placed on the specified layer, avoiding the via prohibition area (‘296, fig. 1, prohibition area (region) generation unit 1110), a prohibition region surrounding the through-via region in a plan view (‘296, fig. 9-11, via prohibition area 1307 in ground layer 1311 is project in a plan view on signal layer 1301).
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claim invention to combine Nakayama and Lee to modify Lee’s to having Nakayama’s a prohibition area in the power/ground layers to prohibit conductors and vias to be placed in the prohibition area that provides efficiently design with a low noise level (‘296, col. 3, ll. 10-15).
However, Lee and Nakayama do not teach a power gating cell in the prohibition region.
Patel, Rakesh (U.S. Pat. 8,878,354).
Patel teaches a semiconductor package including i) a first semiconductor die and ii) a second semiconductor die vertically stacked on top of the first semiconductor die. The first semiconductor die includes a first electronic component and a second electronic component, in which the first electronic component operates in accordance with power associated with a first power domain, and the second electronic component operates in accordance with power associated with a second power domain. The second semiconductor die is configured to supply the power associated with the first power domain to the first electronic component of the first semiconductor die, and supply the power associated with the second power domain to the second electronic component of the first semiconductor die (‘354, the abstract). Patel also teaches a switching array 608 (power gating cell) (‘354, fig. 6A-9, 608).
Patel does not teach a power gating cell (i.e., switching array 608) in the prohibition region.
Conclusion
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NGHIA M. DOAN
Primary Examiner
Art Unit 2851
/NGHIA M DOAN/ Primary Examiner, Art Unit 2851
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