DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
Abstract
The abstract of the disclosure is objected to because of the language in the first sentence. The examiner suggest amending the first line of the abstract to read, “A display deviceincluding a capacitor disposed in the”
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For example, a more descriptive title could be, “DISPLAY DEVICE WITH SECOND CAPACITOR HAVING GREATER TRANSPARENCY THAN FIRST CAPACITOR”.
Claim Objections
Claims 1-20 are objected to because of the following informalities:
In claim 1, last line, “transparancy” should read “transparency”;
In claim 9, line 2, “absolue” should read “absolute”;
In claim 13, third line from the last, “least one the anode” should read, “least one of the anode”; and
Claims 2-8, 10-12 and 14-20 inherit the objection to either independent claim 1 or 13.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 13-20 and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2017/0148861 A1).
Regarding claim 1:
Kim discloses a display device comprising:
a substrate 10 (Fig. 4 and [0067]) including a first area P1 (Fig. 1 and [0067]) having a plurality of first subpixels [0028] and a second area P2 (Fig. 1 and [0067]) having a plurality of second subpixels [0028];
a light emitting diode OLED (Fig. 4 and [0048]) within each of the respective first and second subpixels, each of the light emitting diodes having an anode 150 (Fig. 4 and [0075]) and a cathode 170 (Fig. 4 and [0078]);
a drive transistor M1 (Fig. 4 and [0075]) within each of the respective first and second subpixels, each of the drive transistors having a gate electrode 124 (Fig. 4 and [0102]), a first terminal 128S (Fig. 4 and [0114]) electrically coupled to a power supply source and a second terminal 128D (Fig. 4 and [0114]) electrically coupled to at least one the anode 150 or the cathode of the light emitting diode;
a first capacitor (C1 in P1, Fig. 4 and [0072]) within each of respective first subpixels, the first capacitor having a first electrode 142 (Fig. 4 and [0098]) and a second electrode 144a (Fig. 4 and [0098]); and a second capacitor (C1 in P2, Fig. 4 and [0072]) within each of respective second subpixels, the second capacitor C1 having a first electrode 142 [0098] and a second electrode 144a [0098],
wherein, the first electrode 142 of the first capacitor (C1 in P1, Figs. 1 and 4) is directly connected to the gate electrode of the drive transistor M1 (Figs. 2, 4 and [0098]) in each respective first subpixel,
the first electrode 142 of the second capacitor (C1 in P2) is directly connected to the gate electrode of the drive transistor M1 in each respective second subpixel, and
a transparency of the [second electrode 144a of the] second capacitor (C1 in P2, which is transparent conductive oxide having transmittance greater than 95% [0091]) is greater than a transparency of the [first electrode 142 of the] first capacitor (C1 in P1, which is polysilicon [0091], i.e., polysilicon is typically opaque to visible light).
Regarding claims 13-20 and 22:
re claim 13, Kim discloses a display device comprising:
a substrate 10 (Fig. 4 and [0067]) including a first area P1 (Fig. 1 and [0067]) having a plurality of first subpixels [0028] and a second area P2 (Fig. 1 and [0067]) having a plurality of second subpixels [0028];
a light emitting diode OLED (Fig. 4 and [0048]) within each of the respective first and second subpixels, each of the light emitting diodes having an anode 150 (Fig. 4 and [0075]) and a cathode 170 (Fig. 4 and [0078]);
a capacitor C1 (Figs. 2 and 4) within each of the respective first and second subpixels, each of the capacitor having a first electrode 142 (Fig. 4 and [0098]) and a second electrode 144a (Fig. 4 and [0098]);
a drive transistor M1 (Fig. 2 and 4) within each of the respective first and second subpixels, each of the drive transistors having a gate electrode 124 (Fig. 4 and [0102]) directly connected to the first electrode 142 (Figs. 2, 4 and [0098]) of the capacitor, a first terminal ELVDD (Fig. 2 and [0077]) electrically coupled to a driving voltage line a second terminal ELVSS (Fig. 2 and [0078]) electrically coupled to at least one of the anode or the cathode of the light emitting diode OLED (Fig. 2); and
a connection pattern 128D positioned on a same layer (e.g., substrate layer 10 in Fig. 4) on which the driving voltage line is disposed and electrically coupled to the anode (i.e., all layers in the device are essentially disposed on the substrate layer 10);
re claim 14, the device of claim 13, wherein the connection pattern 128D (Fig. 4) is electrically coupled to the driving voltage line ELVDD (Figs. 2 and 4, wherein the anode OLED is connected to the drain of M1);
re claim 15, the display device of claim 14, wherein the connection pattern 128D is not directly connected to the driving voltage line ELVDD (i.e., the source 128S of M1 is directly connected to ELVDD);
re claim 16, the display device of claim 13, wherein the second electrode of the capacitor C1 (Fig. 2) is electrically coupled to power supply source ELVDD (Fig. 2, wherein C1 is electrically coupled to ELVDD);
re claim 17, the display device of claim 13, further comprising:
a data line (“Data” in Fig. 2) supplying a data voltage to each of the respective first and second subpixels, and positioned on a layer (e.g., on the substrate layer 10) on which the driving voltage line ELVDD and the connection pattern 128D are disposed;
re claim 18, the display device of claim 13, further comprising:
a switching transistor M2 (Fig. 2) within each of the respective first and second subpixels, each of the switching transistor M2 having a terminal electrically coupled to the connection pattern 128D (i.e., M2 is electrically coupled to the drain of M1 by M3);
re claim 19, the device of claim 18, wherein the switching transistor M2 has an active layer and an electrode positioned under the active layer (i.e., an active layer and a gate electrode are inherent to M2, wherein “under” is a relative term such that an orientation of M2 can be rotated accordingly);
re claim 20, the display device of claim 19, wherein the drive transistor M1 (Fig. 4) has an active layer 122 [0102] and an electrode124 positioned under the active layer 122 (when Fig. 4 is rotated 180 degrees); and
re claim 22, the display device of claim 20, wherein the active layer included in the drive transistor M1 is positioned on a same layer (e.g., on substrate layer 10 in Fig. 4) on which the active layer included in the switching transistor M2 is disposed (i.e., all layers in the device are positioned on the substrate layer 10).
Therefore, Kim anticipates 1, 13-20 and 22.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim.
Regarding claims 2-6:
Initially, the current claims are directed to incorporating capacitor electrode(s) on one capacitor having greater transparency the other electrode or greater transparency than electrodes of the other capacitor. Kim anticipates claim 1 and discloses the first and second capacitors plates of each capacitor (C1 in P1, and C1 in P2) can be either polysilicon or transparent conductive oxide (TCO) [0091]. Kim does not disclose the specific combinations of capacitor electrode transparencies currently claimed; however, the current claims are deemed obvious because the general conditions of the claimed invention are disclosed, and given Kim, one of ordinary skill in the art would have been able to incorporate capacitor electrodes with various combinations of polysilicon and ITO without extensive experimentation. In other words, the only modification of Kim needed to arrive at the current invention is to use the same materials disclosed by Kim to incorporate various combinations of polysilicon and ITO capacitor electrodes. One of ordinary skill in the art would have been able to perform such a modification relatively easily depending on how much transparency is required for a specific design; and given specific design requirements, one of ordinary skill in the art would have be able to easily incorporate a specific combination of polysilicon and TCO capacitor electrodes.
Regarding claims 7-12:
Initially, the current claims are directed to various comparisons between “an area”, areas, or “absolute area”, wherein the current claims do not limit or clarify what may or may not be considered to be “an area” or “the absolute area” of a capacitor. In other words, “an area” can be any chosen size in Kim’s capacitor electrodes and “the absolute area” could be chosen to be “the absolute area of one electrode” in comparison to “the absolute area of both electrodes”.
Given Kim, one of ordinary skill in the art could have easily chosen area sizes necessary to arrive and the current claimed invention; therefore, the current claims are deemed obvious because no modification of Kim is required, but rather, one of ordinary skill in the art would only need to compare a chosen area with another chosen area, wherein there are no limits to a size of area that can be chosen.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Kim et al. (US 2021/0104558 A1; hereinafter, “Kim-II”).
Regarding claim 21:
Kim anticipates claim 20 but does not specify exactly where the switching transistor is located relative to the driving transistor.
Kim-II teaches (in Fig. 7 and [0007-0008]) ultra-high-definition (UHD) display devices with different gate capacitances can be obtained by positioning a drive transistor DT on a different layer from switching transistors ST1 and ST2.
It would have been obvious to one of ordinary skill in the art to modify Kim by positioning the driving transistor and the switching transistor on different layers, because Kim-II teaches such a modification could provide an UHD display device with different gate capacitances.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The references listed on the attached PTO-892 disclose display devices capacitors in transmissive regions wherein the devices have some similarities to the current invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892