DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yoshikawa et al. (20240322020).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding Claim 1, in Figs. 1-4 and paragraphs 0025-0051, 0057 and 0058, Yoshika et al .discloses a semiconductor device, comprising: a first electrode 31; a second electrode 32 separated from the first electrode; a first region 1 located on a portion of the first electrode and positioned between the first electrode and the second electrode, the first region including a first semiconductor region of a first conductivity type, a second semiconductor region 2 of a second conductivity type, a portion of the second semiconductor region being located on the first semiconductor region, a third semiconductor region 3 located on the portion of the second semiconductor region, the third semiconductor region being of the first conductivity type, a gate electrode 20 facing the third semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction, the first direction being from the first electrode toward the second electrode, a fourth semiconductor region located on the third semiconductor region and arranged with a portion of the second electrode in the second direction, the fourth semiconductor region being of the second conductivity type, a fifth semiconductor region 5 located between the fourth semiconductor region and a portion of the third semiconductor region in a third direction, the fifth semiconductor region being of the first conductivity type, the third direction being perpendicular to the first and second directions, the fifth semiconductor region being arranged with the portion of the second electrode in the second direction, a first-conductivity-type impurity concentration of the fifth semiconductor region being greater than a first-conductivity-type impurity concentration of the third semiconductor region, and a sixth semiconductor region 6 located between the third semiconductor region and the portion of the second electrode, the sixth semiconductor region being of the first conductivity type, a first-conductivity-type impurity concentration of the sixth semiconductor region being greater than the first-conductivity-type impurity concentration of the third semiconductor region; and a second region located on another portion of the first electrode and positioned between the first electrode and the second electrode, the second region including a seventh semiconductor region 7 of the second conductivity type, the seventh semiconductor region having a higher second-conductivity-type impurity concentration than the second semiconductor region, another portion of the second semiconductor region located on the seventh semiconductor region, and an eighth semiconductor region 8 located on the other portion of the second semiconductor region, the eighth semiconductor region being of the first conductivity type.
Regarding Claim 2, in Yoshikawa et al. the fourth semiconductor region 4 is located between a pair of the fifth semiconductor regions 5 in the third direction.
Regarding Claim 3, in Yoshikawa et al the portion of the third semiconductor region 3 is alternately arranged in the third direction with a group including the fourth semiconductor region 4 and the pair of fifth semiconductor regions 5.
Regarding Claim 4, in Yoshikawa,the first region 1includes a first part, and a second part positioned between the first part and the second region, the third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, and the sixth semiconductor region each are located in the first part and in the second part, and a length in the third direction of the fifth semiconductor region located in the first part is greater than a length in the third direction of the fifth semiconductor region located in the second part.
Regarding Claim 5, in Yoshikawa, a plurality of the fifth semiconductor regions 5 is arranged in the second direction in the second part, and lengths in the third direction of the plurality of fifth semiconductor regions decrease toward the second region.
Regarding Claim 6, in Yoshikawa, a length in the second direction of the second part is greater than a distance in the first direction between the first electrode and the second electrode.
Regarding Claim 7, in Yoshikawa, a first-conductivity-type impurity concentration of the eighth semiconductor region 8 is less than a first-conductivity-type impurity concentration of the third semiconductor region 3.
Regarding Claim 8, in Figs. 1-4 and paragraphs 0025-0051, 0057 and 0058, Yoshikawa et al. discloses a semiconductor device, comprising: a first electrode 31; a second electrode 32 separated from the first electrode; a first region 1 located on a portion of the first electrode and positioned between the first electrode and the second electrode, the first region including a first semiconductor region located in a first part of the first region and in a second part of the first region, the first semiconductor region being of a first conductivity type, a second semiconductor region 2 of a second conductivity type, a portion of the second semiconductor region being located on the first semiconductor region, a third semiconductor region 3 located in the first and second parts and positioned on the portion of the second semiconductor region, the third semiconductor region being of the first conductivity type, a gate electrode 20 located in the first part, the gate electrode facing the third semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction, the first direction being from the first electrode toward the second electrode, a fourth semiconductor region 4 located in the first part and in the second part, the fourth semiconductor region being of the second conductivity type, the fourth semiconductor region being positioned on the third semiconductor region and arranged with a portion of the second electrode in the second direction, a fifth semiconductor region 5 located in the first part, the fifth semiconductor region being of the first conductivity type, the fifth semiconductor region being arranged with the portion of the second electrode in the second direction, a first-conductivity-type impurity concentration of the fifth semiconductor region being greater than a first-conductivity-type impurity concentration of the third semiconductor region, and a sixth semiconductor region 6 located in the first part and in the second part, the sixth semiconductor region being of the first conductivity type, the sixth semiconductor region being positioned between the third semiconductor region and the portion of the second electrode, a first-conductivity-type impurity concentration of the sixth semiconductor region being greater than the first-conductivity-type impurity concentration of the third semiconductor region, the fourth semiconductor region and the fifth semiconductor region being alternately arranged in a third direction in the first part, the fourth semiconductor region and a portion of the third semiconductor region being alternately arranged in the third direction in the second part, the third direction being perpendicular to the first and second directions; and a second region located on another portion of the first electrode and positioned between the first electrode and the second electrode, the second region including a seventh semiconductor region 7 of the second conductivity type, the seventh semiconductor region having a higher second-conductivity-type impurity concentration than the second semiconductor region, another portion of the second semiconductor region located on the seventh semiconductor region, an eighth semiconductor region located on the other portion of the second semiconductor region, the eighth semiconductor region 8 being of the first conductivity type, the second part being positioned between the first part and the second region.
Regarding Claim 9, in Yoshikawa et al, a length in the second direction of the second part is greater than a distance between the first electrode 31 and the second electrode 32.
Regarding Claim 10, in Yoshikawa, a plurality of the sixth semiconductor regions 6 is arranged in the third direction in the second part, and the plurality of sixth semiconductor regions is separated from each other.
Regarding Claim 11, in Yoshikawa, a first-conductivity-type impurity concentration of the eighth semiconductor region 8 is less than a first-conductivity-type impurity concentration of the third semiconductor region.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 8 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 7 of copending Application No. 18486528 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because
Regarding Claim 1, both the instant claim 1 and claim 1 of ‘528 recite, semiconductor device, comprising: a first electrode; a second electrode separated from the first electrode; a first region located on a portion of the first electrode and positioned between the first electrode and the second electrode, the first region including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a portion of the second semiconductor region being located on the first semiconductor region, a third semiconductor region located on the portion of the second semiconductor region, the third semiconductor region being of the first conductivity type, a gate electrode facing the third semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction, the first direction being from the first electrode toward the second electrode, a fourth semiconductor region located on the third semiconductor region and arranged with a portion of the second electrode in the second direction, the fourth semiconductor region being of the second conductivity type, a fifth semiconductor region located between the fourth semiconductor region and a portion of the third semiconductor region in a third direction, the fifth semiconductor region being of the first conductivity type, the third direction being perpendicular to the first and second directions, the fifth semiconductor region being arranged with the portion of the second electrode in the second direction, a first-conductivity-type impurity concentration of the fifth semiconductor region being greater than a first-conductivity-type impurity concentration of the third semiconductor region, and a sixth semiconductor region located between the third semiconductor region and the portion of the second electrode, the sixth semiconductor region being of the first conductivity type, a first-conductivity-type impurity concentration of the sixth semiconductor region being greater than the first-conductivity-type impurity concentration of the third semiconductor region; and a second region located on an other portion of the first electrode and positioned between the first electrode and the second electrode, the second region including a seventh semiconductor region of the second conductivity type, the seventh semiconductor region having a higher second-conductivity-type impurity concentration than the second semiconductor region, an other portion of the second semiconductor region located on the seventh semiconductor region, and an eighth semiconductor region located on the other portion of the second semiconductor region, the eighth semiconductor region being of the first conductivity type.
Regarding Claim 8, both the instant claim 8 and claim 7 of ‘528 recite a semiconductor device, comprising: a first electrode; a second electrode separated from the first electrode; a first region located on a portion of the first electrode and positioned between the first electrode and the second electrode, the first region including a first semiconductor region located in a first part of the first region and in a second part of the first region, the first semiconductor region being of a first conductivity type, a second semiconductor region of a second conductivity type, a portion of the second semiconductor region being located on the first semiconductor region, a third semiconductor region located in the first and second parts and positioned on the portion of the second semiconductor region, the third semiconductor region being of the first conductivity type, a gate electrode located in the first part, the gate electrode facing the third semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction, the first direction being from the first electrode toward the second electrode, a fourth semiconductor region located in the first part and in the second part, the fourth semiconductor region being of the second conductivity type, the fourth semiconductor region being positioned on the third semiconductor region and arranged with a portion of the second electrode in the second direction, a fifth semiconductor region located in the first part, the fifth semiconductor region being of the first conductivity type, the fifth semiconductor region being arranged with the portion of the second electrode in the second direction, a first-conductivity-type impurity concentration of the fifth semiconductor region being greater than a first-conductivity-type impurity concentration of the third semiconductor region, and a sixth semiconductor region located in the first part and in the second part, the sixth semiconductor region being of the first conductivity type, the sixth semiconductor region being positioned between the third semiconductor region and the portion of the second electrode, a first-conductivity-type impurity concentration of the sixth semiconductor region being greater than the first-conductivity-type impurity concentration of the third semiconductor region, the fourth semiconductor region and the fifth semiconductor region being alternately arranged in a third direction in the first part, the fourth semiconductor region and a portion of the third semiconductor region being alternately arranged in the third direction in the second part, the third direction being perpendicular to the first and second directions; and a second region located on an other portion of the first electrode and positioned between the first electrode and the second electrode, the second region including a seventh semiconductor region of the second conductivity type, the seventh semiconductor region having a higher second-conductivity-type impurity concentration than the second semiconductor region, an other portion of the second semiconductor region located on the seventh semiconductor region, an eighth semiconductor region located on the other portion of the second semiconductor region, the eighth semiconductor region being of the first conductivity type, the second part being positioned between the first part and the second region.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Examiner is including Kato (20240290781) as a pertinent prior art that is not relied upon on this rejection but that discloses (see paragraphs 0059, 0062, 0070, 00121) suppression of parasitic thyristor in RC-IGBT devices.
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 11/29/2025