DETAILED ACTION
This correspondence is in response to the communications received 03/10/2026. Claims 9 and 10 have been added. Claims 1, 3, 4, 7, and 8 have been amended. Claim 2 has been canceled. Claims 1 and 3-10 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/10/2026 has been considered by the examiner and made of record in the application file.
Response to Amendment
Applicant’s amendment to claim 4 overcomes the objection outlined in the previous Office Action. The objection is withdrawn.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the surface of the semiconductor substrate" in lines 2 and 3. There is insufficient antecedent basis for this limitation in the claim.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a capacitor (1) comprising:
a semiconductor substrate (10) that includes a trench having side walls and a bottom surface (see Fig. 1);
an electrode layer (30) extending from a surface of the semiconductor substrate into the trench of the semiconductor substrate (see Fig. 1), the electrode layer extending along the side walls and the bottom surface of the trench such that a cavity (AG) is formed inside the trench (see Fig. 1), the electrode layer containing a metal silicide ([0027]);
an insulating film (40) covering the electrode layer along the surface of the semiconductor substrate and closing an opening of the cavity (see Fig. 1);
a dielectric film (20) provided between the electrode layer and the semiconductor substrate and electrically insulating the electrode layer from the semiconductor substrate (see Fig. 1);
a first terminal (53) connected to the electrode layer (see Fig. 1); and
a second terminal (55) connected to the semiconductor substrate (see Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 10,276,651 B2, published 04/30/2019) in view of Park (US 7,183,603 B2, published 02/27/2007).
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Regarding claim 1, Figs. 9A and 9B of Lin disclose a capacitor (“With reference to FIGS. 9A and 9B, various views 800A, 800B of some embodiments of a trench capacitor 802”, col. 9, lines 64-65) comprising:
a semiconductor substrate (“semiconductor substrate 806 may be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a group III-V substrate, or some other semiconductor substrate”, col. 10, lines 9-12) that includes a trench (“trenches 808t”, col. 10, line 7) having side walls and a bottom surface (as seen in Fig. 9B, 808t have side walls and a bottom surface);
an electrode layer (“capacitor electrodes 810”, col. 10, line 31) extending from a surface of the semiconductor substrate into the trench of the semiconductor substrate (as seen in Fig. 9B, 810 extend from the upper surface of 806 into 808t), the electrode layer extending along the side walls and the bottom surface of the trench such that a cavity is formed inside the trench (as seen in Fig. 9B, 810 extends along the sidewalls and the bottom surface of 808t such that “air gaps 804”, col. 9, lines 66, are formed);
an insulating film (“capping layer 816”, col. 11, line 12, where “capping layer 816 may be, for example, silicon nitride, silicon carbide, silicon oxide, or some other dielectric”, col. 11, lines 22-23, these materials are known in the art as insulating) covering the electrode layer along the surface of the semiconductor substrate (as seen in Fig. 9B, 816 covers 810 along the upper surface of 806) and closing an opening of the cavity (as seen in Fig. 9B, 816 closes the openings in 804);
a dielectric film (“capacitor dielectric layer 814”, col. 11, lines 5-6) provided between the electrode layer and the semiconductor substrate (as seen in Fig. 9B, 814 is provided between 810 and 806) and electrically insulating the electrode layer from the semiconductor substrate (as a dielectric layer, 814 will electrically insulate 810 from 806, further one having ordinary skill in the art would recognize that 810 will necessarily electrically insulate 810 from 806 in order for 800B to function as a capacitor structure);
a first terminal connected to the electrode layer (“contacts vias 812 electrically couple the capacitor electrode(s) 810 … to an overlying (e.g., overlying in the z dimension) back end of line (BEOL) metallization stack”, col. 10, lines 61-64, for ease of reference 812 that are connected to 810 will hereinafter be referred to as “812E”); and
a second terminal connected to the semiconductor substrate (“contacts vias 812 electrically couple … the doped well 806[w] to an overlying (e.g., overlying in the z dimension) back end of line (BEOL) metallization stack”, col. 10, lines 61-64, for ease of reference 812 that are connected to 806w will hereinafter be referred to as “812S”, as 806w is formed in 806, 812S are therefore connected to 806).
Lin fails to disclose “the electrode layer containing a metal silicide”.
However, in a similar field of endeavor, Figs. 2-9C of Park teach the electrode layer containing a metal silicide (“a doped polysilicon layer as the gate layer 210 having conductivity is deposited, and a metal silicide layer as the gate layer 230 is formed thereon to improve the conductivity of the gate”, col. 6, lines 62-65, therefore 810 of Lin can be formed of a doped polysilicon layer with an additional metal silicide layer to increase conductivity).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the electrode layer containing a metal silicide” as taught by Park in the system of Lin for the purpose of increasing the conductivity of the electrode layer.
Regarding claim 5, Figs. 9A and 9B of Lin in combination with Figs. 2-9C of Park disclose the capacitor according to claim 1, Figs. 2-9C of Park further disclose wherein the electrode layer further includes a polysilicon layer provided between the dielectric film and the metal silicide (as discussed above Park teaches “a doped polysilicon layer as the gate layer 210 having conductivity is deposited, and a metal silicide layer as the gate layer 230 is formed thereon to improve the conductivity of the gate”, col. 6, lines 62-65, therefore after substituting 210 and 230 of Park for 810 of Lin, 210 of Park will be provided between 814 of Lin and 230 of Park).
Regarding claim 6, Figs. 9A and 9B of Lin in combination with Figs. 2-9C of Park disclose the capacitor according to claim 1, Figs. 9A and 9B of Lin further disclose wherein the dielectric film includes at least one of a silicon oxide film, a silicon nitride film, and a high dielectric constant film (“The capacitor dielectric layer(s) 814 may be, for example, silicon nitride, silicon oxide, some other dielectric, or any combination of the foregoing”, col. 11, 8-11).
Regarding claim 7, Figs. 9A and 9B of Lin in combination with Figs. 2-9C of Park disclose the capacitor according to claim 1, Figs. 9A and 9B of Lin further disclose wherein
the dielectric film covers the bottom surface and the sidewalls of the trench (as seen in Fig. 9B, 814 covers the bottom surface and the sidewalls of 808t), and
the electrode layer covers the dielectric film in the trench (as seen in Fig. 9B, 810 covers 814 in 808t).
Regarding claim 8, Figs. 9A and 9B of Lin in combination with Figs. 2-9C of Park disclose the capacitor according to claim 1, Figs. 2-9C of Park further disclose wherein
the electrode layer further contains conductive polysilicon (as discussed above, 210 is conductive polysilicon).
Figs. 9A and 9B of Lin further disclose
the polysilicon is provided on the dielectric film on the bottom surface and at a bottom surface side of the side wall of the trench (as seen in Fig. 9B, 810, or 210 of Park after the substitution, is provided on 814 on the bottom surface and at a bottom surface side of the side wall of 808t), and
the metal silicide is provided on the dielectric film at an opening side of the trench (as discussed above, after the substitution of 210 and 230 of Park for 810 of Lin, 230 of Park will be provided on 814 of Lin at an opening side of 808t).
Regarding claim 9, Figs. 9A and 9B of Lin disclose a capacitor (“With reference to FIGS. 9A and 9B, various views 800A, 800B of some embodiments of a trench capacitor 802”, col. 9, lines 64-65) comprising:
a semiconductor substrate (“semiconductor substrate 806 may be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a group III-V substrate, or some other semiconductor substrate”, col. 10, lines 9-12) that includes a trench (“trenches 808t”, col. 10, line 7) inside which a space is left (“air gaps 804”, col. 9, lines 66, as seen in Fig. 9B 804 are in 808t which are in 806);
an electrode layer (“capacitor electrodes 810”, col. 10, line 31) containing a metal silicide (Lin does not disclose the electrode layer containing a metal silicide, however a secondary reference will be used to teach this limitation below) and extending along inner surfaces of the trench such that the electrode layer is exposed to the space (as seen in Fig. 9B, 810 extends along inner surfaces of 808t such that 810 is exposed to 804);
a dielectric film (“capacitor dielectric layer 814”, col. 11, lines 5-6) extending between the electrode layer and the semiconductor substrate (as seen in Fig. 9B, 814 extends between 810 and 806) and electrically insulating the electrode layer from the semiconductor substrate (as a dielectric layer, 814 will electrically insulate 810 from 806, further one having ordinary skill in the art would recognize that 810 will necessarily electrically insulate 810 from 806 in order for 800B to function as a capacitor structure);
a first terminal connected to the electrode layer (“contacts vias 812 electrically couple the capacitor electrode(s) 810 … to an overlying (e.g., overlying in the z dimension) back end of line (BEOL) metallization stack”, col. 10, lines 61-64, for ease of reference 812 that are connected to 810 will hereinafter be referred to as “812E”); and
a second terminal connected to the semiconductor substrate (“contacts vias 812 electrically couple … the doped well 806[w] to an overlying (e.g., overlying in the z dimension) back end of line (BEOL) metallization stack”, col. 10, lines 61-64, for ease of reference 812 that are connected to 806w will hereinafter be referred to as “812S”, as 806w is formed in 806, 812S are therefore connected to 806).
Lin fails to disclose “an electrode layer containing a metal silicide”.
However, in a similar field of endeavor, Figs. 2-9C of Park teach an electrode layer containing a metal silicide (“a doped polysilicon layer as the gate layer 210 having conductivity is deposited, and a metal silicide layer as the gate layer 230 is formed thereon to improve the conductivity of the gate”, col. 6, lines 62-65, therefore 810 of Lin can be formed of a doped polysilicon layer with an additional metal silicide layer to increase conductivity).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “an electrode layer containing a metal silicide” as taught by Park in the system of Lin for the purpose of increasing the conductivity of the electrode layer.
Regarding claim 10, Figs. 9A and 9B of Lin in combination with Figs. 2-9C of Park disclose the capacitor according to claim 9, Figs. 9A and 9B of Lin further disclose further comprising:
an insulating film (“capping layer 816”, col. 11, line 12, where “capping layer 816 may be, for example, silicon nitride, silicon carbide, silicon oxide, or some other dielectric”, col. 11, lines 22-23, these materials are known in the art as insulating) covering the electrode layer along the surface of the semiconductor substrate (as seen in Fig. 9B, 816 covers 810 along the surface of 806), wherein
the space is surrounded by the insulating film and the electrode layer (as seen in fig 9B, 804 is surrounded by 810 and 816).
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 10,276,651 B2, published 04/30/2019) in view of Park (US 7,183,603 B2, published 02/27/2007) in view of Chou et al. (US 9,105,759 B2, published 08/11/2015).
Regarding claim 3, Figs. 9A and 9B of Lin in combination with Figs. 2-9C of Park disclose the capacitor according to claim 1.
Lin in combination with Park does not specify “the first terminal is provided on the insulating film and extends in a first contact hole provided in the insulating film so as to be connected to the electrode layer, and
the second terminal is provided on the insulating film and extends in a second contact hole provided in the insulating film so as to be connected to the semiconductor substrate.”
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However, in a similar field of endeavor, Figs. 1A, 1B, 3 and 4A-4I of Chou teach the first terminal is provided on the insulating film (as seen in Fig. 1A, “Electrode 142b”, col. 4, line 15, is provided on “cap dielectric layer 130”, col. 1, line 67, where 142b and 130 of Chou are equivalent to 812E and 816 of Lin) and extends in a first contact hole provided in the insulating film so as to be connected to the electrode layer (as seen in Fig. 1A, 142b extends in a first contact hole provided in 130 so as to be connected to “conductive layer 124a”, col. 3, line 19, where 124a of Chou is equivalent to 810 of Lin), and
the second terminal is provided on the insulating film (as seen in Fig. 1A, “electrode 142a”, col. 4, line 11, is provided on 130, where 142a of Chou is equivalent to 812S of Lin) and extends in a second contact hole provided in the insulating film so as to be connected to the semiconductor substrate (as seen in Fig. 1A, 142a extends in a second contact hole provided in 130 so as to be connected to “Well 110”, col. 2, line 29”, where 110 of Chou is equivalent to 806w of Lin).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the first terminal is provided on the insulating film and extends in a first contact hole provided in the insulating film so as to be connected to the electrode layer, and
the second terminal is provided on the insulating film and extends in a second contact hole provided in the insulating film so as to be connected to the semiconductor substrate” as taught by Chou in the system of Lin in combination with Park for increasing the surface area of the terminals so as to reduce contact resistance when connecting to the device terminals.
Regarding claim 4, Figs. 9A and 9B of Lin in combination with Figs. 2-9C of Park and Figs. 1A, 1B, 3 and 4A-4I of Chou disclose the capacitor according to claim 3, Figs. 9A and 9B of Lin further disclose wherein
the insulating film covers a part of the surface of the semiconductor substrate (as seen in Fig. 9B, 816 covers a part of the upper surface of 806),
the dielectric film extends between the part of the surface of the semiconductor substrate and the insulating film (as seen in Fig. 9B, 814 extends between the part of the upper surface of 806 and 816).
Figs. 1A, 1B, 3 and 4A-4I of Chou further disclose
the second contact hole penetrates the insulating film and the dielectric film (as seen in Fig. 1A, the second contact hole containing 142a penetrates 130 and “dielectric layer 122a”, col. 3, lines 18-19, where 122a of Chou is equivalent to 814 of Lin), and
the second terminal extends in the second contact hole so as to be connected to the semiconductor substrate (as seen in Fig. 1A, 142a extends in the second contact hole so as to be connected to 110).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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