DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kumagai (20170271324) in view of Kubo (20170077272)
Regarding Claim 1, in Fig. 32 Kumagai discloses a semiconductor device, comprising: a first electrode 10; a first semiconductor layer 1,2 connected to the first electrode, the first semiconductor layer including silicon and carbon (Silicon Carbide, see paragraphs 0012 and 0013), the first semiconductor layer being of a first conductivity type (N); a plurality of second semiconductor layers 4/6b1/6b2 located on a (upper) portion of the first semiconductor layer, the plurality of second semiconductor layers including silicon and carbon (Silicon Carbide see paragraphs 0012 and 0013) , the plurality of second semiconductor layers being of a second conductivity type (P); a third semiconductor layer 5/5b/17a located on a (upper) portion of the second semiconductor layer, the third semiconductor layer including silicon and carbon (Silicon Carbide, see paragraphs 0012 and 0013), the third semiconductor layer being of the first conductivity type (N); a second electrode (gate electrode) 8a facing the second semiconductor layer via an insulating film 7a; and a third electrode 9 connected to the second and third semiconductor layers. Kumagai fails to disclose the limitation where a fourth semiconductor layer located in a portion of the first semiconductor layer between the second semiconductor layers, the fourth semiconductor layer including silicon and carbon, the fourth semiconductor layer being of the second conductivity type. However, Saito et al. discloses a semiconductor device where in Figs. 9 and 10 and in paragraph 0052 (along with paragraph 0037), the required fourth (second conductivity type (P)) semiconductor layer 4 is disclosed (please note that in Figs 9 and 10, the base layer is 5. Essentially the “the fourth semiconductor layer 4” covers bottom left and bottom left sidewalls of base layer 5. This is different from the instant application as in the instant application Fig. 4, the fourth semiconductor layer 27 covers the middle sidewall of base layer 23. However, this difference is not reflected in the claim language)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the fourth semiconductor layer in Kumagai as taught by Saito et al. in order to reduce gate to drain capacitance (please see paragraph 0052 of Saito et al. )(Please note that even though paragraph 0052 mentions Fig. 7 and not Figs 9 and 10, the essential concept of reducing “facing area” between the gate and drain (drift), is also present in Figs 9 and 10.)
Regarding Claim 6, in Figs 9 and 10 of Saito et al. fourth semiconductor layer 5 is separated from an upper surface of the first semiconductor layer 2/3.
Regarding Claim 7, in Figs. 9 and 10 of Saito et al, the fourth semiconductor layer contacts the second semiconductor layer 5/7.
Regarding Claim 8, in Figs. 9 and 10 of Saito et al, upper surface of the fourth semiconductor layer 4 is positioned lower than an upper surface of the second semiconductor layer 5/7, and a lower surface of the fourth semiconductor layer 4 is positioned higher than a lower surface of the second semiconductor layer 5/7.
Regarding Claim 9, in paragraph 0075 of Kumagai, the metal layer includes titanium (Please note that it is examiner’s opinion that this claim should depend from claim 2. Otherwise, the claim has an antecedent issue. Proper corrected is requested.)
Regarding Claim 10, in paragraph 0075 of Kumagai, the conductive layer includes nickel and silicon. Please note that it is examiner’s opinion that this claim should depend from claim 2. Otherwise, the claim has an antecedent issue. Proper corrected is requested.)
Regarding Claim 11, in Fig. 32, Kumagai discloses a semiconductor device, comprising: a first electrode 10; a first semiconductor layer 1,2 connected to the first electrode, the first semiconductor layer being of a first conductivity type (N); a second semiconductor layer 4/6b1/6b2 located on a (upper) portion of the first semiconductor layer, the second semiconductor layer being of a second conductivity type (P); a third semiconductor layer 5/5b/17a located on a (upper) portion of the second semiconductor layer, the third semiconductor layer being of the first conductivity type (N); a second electrode 8a (gate electrode) located in a region, the second electrode 8a facing the second semiconductor layer; and a third electrode 9 connected to the second and third semiconductor layers. Kumagai fails to disclose a fourth semiconductor layer located on a side surface of the second semiconductor layer in the first semiconductor layer, the fourth semiconductor layer being of the second conductivity type and the second electrode directly above the fourth semiconductor layer. However, Saito et al. discloses a semiconductor device where in Figs. 9 and 10 and in paragraph 0052 (along with paragraph 0037), the required fourth (second conductivity type (P)) semiconductor layer 4 is disclosed (please note that in Figs 9 and 10, the base layer is 5. Essentially the “the fourth semiconductor layer 4” covers bottom left and bottom left sidewalls of base layer 5. This is different from the instant application as in the instant application Fig. 4, the fourth semiconductor layer 27 covers the middle sidewall of base layer 23. However, this difference is not reflected in the claim language). Saito further discloses that the second electrode i.e. the gate electrode 19 directly above the fourth semiconductor layer 4.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the fourth semiconductor layer and the second/gate electrode being directly above the fourth semiconductor layer in Kumagai as taught by Saito et al. in order to reduce gate to drain capacitance (please see paragraph 0052 of Saito et al. )(Please note that even though paragraph 0052 mentions Fig. 7 and not Figs 9 and 10, the essential concept of reducing “facing area” between the gate and drain (drift), is also present in Figs 9 and 10.)
Regarding Claim 12, in paragraph 0012 and 0013 Kumagai it is disclosed that the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer include silicon and carbon (SiC/Silicon Carbide).
Allowable Subject Matter
Claims 2-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 2, prior art failed to disclose or fairly suggest a semiconductor device comprising, along with other recited claim limitations, a metal layer located on the first semiconductor layer, the metal layer having a Schottky junction with the first semiconductor layer, the second semiconductor layer extending in a first direction, a plurality of first openings being arranged along the first direction in the second semiconductor layer, the third semiconductor layer extending in the first direction, a second opening and a third opening being alternately arranged along the first direction in the third semiconductor layer, the conductive layer being located in the second opening, the metal layer being located in the third opening and contacting a portion of the first semiconductor layer located in the first opening. Claims 3-5 depend from claim 2 and hence are indicated as allowable subject matter for the same reason therein.
Relevant Cited Prior Art
Examiner is including Baliga (20040099905), Hebert (20100155836) and Kubo (2017/0077272) as pertinent prior art references that are not relied upon but that do disclose planar integrated/embedded SiC MOSFET/SBD devices
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 12/17/2025