DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-9 in the reply filed on 01/27/2026 is acknowledged.
Claims 10-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/27/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent No. 9,871,107 to Green et al. (hereinafter Green).
With respect to claim 1, Green discloses a high electron mobility transistor (e.g., HEMT transistor 120 in the active area mesa 114, see the annotated Figs. 1-2 below) (Green, Figs. 1-4, Col. 2, lines 26-68; Cols. 3-12), comprising:
a body (e.g., substrate 212 including sapphire) (Green, Figs. 1-4, Col. 5, lines 12-24) having a first surface (e.g., a top surface 213) and a second surface (e.g., a bottom surface 210) opposite to said first surface;
a transistor unit (e.g., active area mesa 114 including a HEMT transistor 120) (Green, Figs. 1-4, Col. 3, lines 11-43; Col. 7, lines 45-53) including a
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composite semiconductor layer (e.g., buffer layer 214, channel layer 216, and barrier layer 218) (Green, Figs. 1-4, Col. 5, lines 12-15) disposed on said first surface (213) and an electrode component (e.g., 124/126/122) (Green, Figs. 1-4, Col. 8, lines 13-18) disposed on said composite semiconductor layer (214/216/218) opposite to said first surface (213), said electrode component including a gate electrode (126), a source electrode (124), and a drain electrode (122) which are spaced apart from one another, said source electrode (124) and said drain electrode (122) disposed at two opposite sides of said gate electrode (126); and
an electrically conducting structure (e.g., 134/128/142, an interconnect metal 128, an interconnect structure 134, and a metal layer 142 inside through wafer vias 168 and on the bottom surface 210) (Green, Figs. 1-4, Col. 9, lines 5-21; Col. 11, lines 8-29; Col. 21, lines 46-54) including a back electrode (e.g., the metal layer 142 on the bottom surface 210) disposed on said second surface (210) and at least one connecting electrode (e.g., the interconnect metal 128 under the interconnect structure 134 coupled to the gate electrode 126 and the metal layer 142 inside through via 168) connecting said gate electrode (126) and said back electrode (e.g., the metal layer 142 on the bottom surface 210).
Regarding claim 2, Green discloses the high electron mobility transistor as claimed in claim 1. Further, Green discloses the high electron mobility transistor, wherein said body (212) (Green, Figs. 1-4, Col. 5, lines 12-24) further includes two opposite side surfaces (e.g., a left surface including a side surface of the through via 168 and a right surface of the substrate 212) each of which connects said first surface (213) and said second surface (210), said at least one connecting electrode (e.g., the interconnect metal 128 under the interconnect structure 134, and the metal layer 142 inside through wafer vias 168) (Green, Figs. 1-4, Col. 9, lines 5-21; Col. 11, lines 8-29) being disposed on one of said side surfaces and said composite semiconductor layer (214/216/218).
Regarding claim 3, Green discloses the high electron mobility transistor as claimed in claim 1. Further, Green discloses the high electron mobility transistor, wherein said composite semiconductor layer (214/216/218) includes a buffer layer (e.g., 214/216) (Green, Figs. 1-4, Col. 5, lines 12-68; Col. 6, lines 1-67; Col. 8, lines 13-46) disposed on said first surface (213) and a barrier layer (e.g., 218) disposed on said buffer layer (214/216) opposite to said first surface (213), said electrode component (124/126/122) being disposed on said barrier layer (218).
Regarding claim 4, Green discloses the high electron mobility transistor as claimed in claim 3. Further, Green discloses the high electron mobility transistor, wherein said body (212) is made of aluminum oxide (e.g., the substrate 212 made of sapphire that includes aluminum oxide) (Green, Figs. 1-4, Col. 5, lines 15-21).
Regarding claim 5, Green discloses the high electron mobility transistor as claimed in claim 3. Further, Green discloses the high electron mobility transistor, wherein said buffer layer (e.g., GaN layer 214/216) (Green, Figs. 1-4, Col. 5, lines 37-44; Col. 6, lines 11-21) is made of gallium nitride.
Regarding claim 6, Green discloses the high electron mobility transistor as claimed in claim 3. Further, Green discloses the high electron mobility transistor, wherein said barrier layer (e.g., AlGaN layer 218) (Green, Figs. 1-4, Col. 6, lines 28-47) is made of aluminum gallium nitride.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-8 are rejected under 35 U.S.C. 103 as being unpatentable over KR 20100096942 A to Choi et al. (hereinafter Choi) in view of Brech et al. (US 2021/0057528, hereinafter Brech).
With respect to claim 1, Choi discloses a high electron mobility transistor (e.g., HEMT transistor having a heat dissipation structure, see the annotated Fig. 1 below) (Choi, Fig. 1, Abstract, pp. 3-6), comprising:
a body (e.g., 10/12/14) (Choi, Fig. 1, pp. 3-4) having a first surface (e.g., a top surface of the buffer layer 14) and a second surface (e.g., a bottom surface of the substrate 10) opposite to said first surface;
a transistor unit (e.g., a mesa structure including an active region 20 of the HEMT transistor) (Choi, Fig. 1, pp. 3-4) including a composite semiconductor layer (e.g., GaN 16 and AlGaN 19) disposed on said first surface and an electrode component (e.g., 31/33/35) disposed on said composite semiconductor layer (16/19) opposite to said first surface, said electrode component including a gate electrode (33), a source electrode (31), and a drain electrode (35) which are spaced apart from one another, said source electrode (31) and said drain
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electrode (35) disposed at two opposite sides of said gate electrode (33); and
an electrically conducting structure (e.g., 53/43, a wiring layer 53 and a heat dissipation layer 43 comprised of a metal material and used as a ground electrode) (Choi, Fig. 1, pp. 4-5) including a back electrode (43) disposed on said second surface and at least one connecting electrode (53) connecting said source electrode (31) and said back electrode (43).
Further, Choi does not specifically disclose at least one connecting electrode connecting said gate electrode and said back electrode.
However, Brech teaches forming a semiconductor device comprising a mesa (14) (Brech, Fig. 4, ¶0050-¶0055) including a high electron mobility transistor (HEMT, see the annotated Fig. 4 below), wherein at least one connecting electrode (e.g., a plurality of conducting vias 24/30 extending along a side of the mesa 14) (Brech, Fig. 4, ¶0057, ¶0059) is provided to connect a gate electrode (31) (Brech, Fig. 4, ¶0039, ¶0048) and a back electrode (e.g., an outer contact pad 39) (Brech, Fig. 4, ¶0056, ¶0058), and a source electrode (20) and a back electrode (e.g., an outer contact pad 22), to improve electrical and thermal performance of the semiconductor device by minimizing thermal resistance and parasitic electrical interconnects
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(Brech, ¶0004, ¶0012, ¶0050, ¶0082).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the high electron mobility transistor of Choi by forming least one connecting electrode including a plurality of conducting vias extending along a sidewall of the HEMT mesa structure and connected to the gate electrode as taught by Brech to have at least one connecting electrode connecting said gate electrode and said back electrode, in order to improve electrical and thermal performance of the semiconductor device by minimizing thermal resistance and parasitic electrical interconnects (Brech, ¶0004, ¶0012, ¶0050, ¶0082).
Regarding claim 3, Choi in view of Brech discloses the high electron mobility transistor as claimed in claim 1. Further, Choi discloses the high electron mobility transistor, wherein said composite semiconductor layer (16/19) includes a buffer layer (e.g., GaN layer 16 of the mesa structure is the etched portion of the GaN buffer layer 14) (Choi, Fig. 1, pp. 4-5) disposed on said first surface and a barrier layer (e.g., AlGaN layer 19) disposed on said buffer layer (16) opposite to said first surface, said electrode component (31/33/35) being disposed on said barrier layer (19).
Regarding claim 4, Choi in view of Brech discloses the high electron mobility transistor as claimed in claim 3. Further, Choi discloses the high electron mobility transistor, wherein said body (10/12/14) is made of aluminum oxide (e.g., the substrate 10 made of sapphire Al2O3) (Choi, Fig. 1, p. 4).
Regarding claim 5, Choi in view of Brech discloses the high electron mobility transistor as claimed in claim 3. Further, Choi discloses the high electron mobility transistor, wherein said buffer layer (e.g., GaN layer 16) (Choi, Fig. 1, p. 4) is made of gallium nitride.
Regarding claim 6, Choi in view of Brech discloses the high electron mobility transistor as claimed in claim 3. Further, Choi discloses the high electron mobility transistor, wherein said barrier layer (e.g., AlGaN layer 19) (Choi, Fig. 1, p. 4) is made of aluminum gallium nitride.
Regarding claim 7, Choi in view of Brech discloses the high electron mobility transistor as claimed in claim 1. Further, Choi discloses the high electron mobility transistor, wherein said body (10/12/14) is formed with a recess (e.g., a heat dissipation groove 41 has a size that includes the active region 20 of the HEMT transistor) (Choi, Fig. 1, pp. 4, 6) which corresponds in position with said transistor unit (e.g., mesa structure including an active region 20 of the HEMT transistor) (Choi, Fig. 1, pp. 3-4), said second surface having an inner recess portion (e.g., a U-shaped surface corresponding to a heat dissipation groove 41) that defines said recess (41) and an outer surface portion (e.g., an outer flat surface) connected to a periphery of said inner recess portion, said back electrode (e.g., heat dissipation metal layer 43) including a thermally conducting portion disposed on said inner recess portion (e.g., the U-shaped surface corresponding to a heat dissipation groove 41), and a grounding portion (e.g., the flat portion of the metal layer 43 used as a ground layer) connected to said thermally conducting portion, disposed on said outer surface portion and electrically connected to said at least one connecting electrode (53).
Regarding claim 8, Choi in view of Brech discloses the high electron mobility transistor as claimed in claim 7. Further, Choi discloses the high electron mobility transistor, wherein said body (10/12/14) is made of aluminum oxide (e.g., the substrate 10 made of sapphire Al2O3) (Choi, Fig. 1, p. 4).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over KR 20100096942 A to Choi in view of Brech (US 2021/0057528) as applied to claim 1, and further in view of Green (US Patent No. 9,871,107).
Regarding claim 2, Choi in view of Brech discloses the high electron mobility transistor as claimed in claim 1. Further, Choi discloses the high electron mobility transistor, wherein said body (e.g., 10/12/14) (Choi, Fig. 1, pp. 3-4) further includes two opposite side surfaces each of which connects said first surface (e.g., a top surface of the buffer layer 14) and said second surface (e.g., a bottom surface of the substrate 10), but does not specifically disclose that said at least one connecting electrode being disposed on one of said side surfaces and said composite semiconductor layer.
However, Green teaches forming a semiconductor device (Green, Figs. 1-4, Col. 2, lines 26-68; Cols. 3-12) comprising a HEMT transistor (120) (Green, Figs. 1-4, Col. 3, lines 11-43; Col. 7, lines 35-53) including an active area mesa (114) on a top surface (213) of the body (e.g., substrate 112 including sapphire) (Green, Figs. 1-4, Col. 5, lines 12-24), wherein the body (e.g., 212) further includes two opposite side surfaces (e.g., a left surface including a side surface of the through via 168 and a right surface of the substrate 212) each of which connects said first surface (e.g., a top surface 213 of the substrate 212) and said second surface (e.g., a bottom surface 210 of the substrate 212), and at least one connecting electrode (e.g., metal layer 142 inside through wafer via 168 coating a sidewall of the body 112) (Green, Figs. 1-4, Col. 11, lines 8-29) being disposed on one of the side surfaces of the body (112) and the composite semiconductor layer (e.g., the active mesa 114 including a buffer/channel GaN layer 214/216 and AlGaN barrier layer 218) (Green, Figs. 1-4, Col. 5, lines 37-67; Col. 6, lines 1-67), to provide a connection between the interconnect (128, to electrically couple the gate electrode 126 , the source electrode 124) (Green, Figs. 1-4, Col. 9, lines 5-21) and the backside metal layer (142/140) coupled to a ground plane (e.g., PCB 410) (Green, Figs. 1-4, Col. 12, lines 34-40), and that is further connected to the thermal dissipation structure (Green, Figs. 1-4, Col. 12, lines 7-13), to provide a thermal heat path that allows heat to flow from transistor (120) through the body (212) to an appropriate heat sink.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the high electron mobility transistor of Choi/Brech by forming at least one connecting electrode that connects the interconnect (formed on a top surface of the body and electrically coupled to the gate electrode of the HEMT transistor) and backside electrode (coupled to a ground plane and heat sink) as taught by Green to have the high electron mobility transistor, wherein said at least one connecting electrode being disposed on one of said side surfaces and said composite semiconductor layer, in order to improve electrical and thermal performance of the semiconductor device by providing a thermal heat path that allows heat to flow from transistor through the body to an appropriate heat sink, and to provide a ground plane for the electronic package with improved performance characteristics for radio-frequency application (Green, Col. 1, lines 7-8, 38-41; Col. 9, lines 5-21; Col. 12, lines 7-13; lines 34-40).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 9,871,107 to Green in view of Choi (KR 20100096942 A).
Regarding claim 7, Green discloses the high electron mobility transistor as claimed in claim 1. Further, Green discloses the high electron mobility transistor, wherein said body (212) is formed with a recess (e.g., a cavity 160 under the transistor 120, not shown in Fig. 2) (Green, Figs. 2-4, Col. 10, lines 38-43) which corresponds in position with said transistor unit (e.g., 120), said second surface (210) having an inner recess portion (e.g., the inner cavity surface 262 and cavity sidewall surface 264, wherein the cavity 160 only partially extend through the body 212) (Green, Figs. 2-4, Col. 9, lines 65-67; Col. 10, lines 1-7, lines 32-34) that defines said recess (160) and an outer surface portion (e.g., an outer flat surface 210) connected to a periphery of said inner recess portion, said back electrode (e.g., metal layer 140 below transistor 120 connected to heat sink through the portion 420) (Green, Fig. 4, Col. 12, lines 7-13) including a thermally conducting portion (420), and a grounding portion (e.g., bottom conductor 414 provides ground layer) (Green, Fig. 4, Col. 12, lines 34-40) connected (through the bottom layer 416) to said thermally conducting portion (420), disposed on said outer surface portion and electrically connected to said at least one connecting electrode (142).
Further, Green does not specifically disclose a thermally conducting portion disposed on said inner recess portion.
However, Choi teaches forming a recess portion (e.g., a heat dissipation groove 41 has a size that includes the active region 20 of the HEMT transistor) (Choi, Fig. 1, pp. 4, 6) which corresponds in position with said transistor unit (e.g., mesa structure including an active region 20 of the HEMT transistor) (Choi, Fig. 1, pp. 3-4), said second surface having an inner recess portion (e.g., a U-shaped surface corresponding to a heat dissipation groove 41) that defines said recess (41) and an outer surface portion (e.g., an outer flat surface) connected to a periphery of said inner recess portion, said back electrode (e.g., heat dissipation metal layer 43) including a thermally conducting portion disposed on said inner recess portion (e.g., the U-shaped surface corresponding to a heat dissipation groove 41), to provide a heat dissipation structure capable of effectively dissipating heat (Choi, Abstract, pp. 2-4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the high electron mobility transistor of Green by forming a thermally conducting portion on the inner surface of the heat dissipation groove as taught by Choi to have the high electron mobility transistor comprising: a thermally conducting portion disposed on said inner recess portion, in order to provide a heat dissipation structure capable of effectively dissipating heat (Choi, Abstract, pp. 2-4).
Regarding claim 8, Green in view of Choi discloses the high electron mobility transistor as claimed in claim 7. Further, Green discloses the high electron mobility transistor, wherein said body (212) is made of aluminum oxide (e.g., the substrate 212 made of sapphire that includes aluminum oxide) (Green, Figs. 1-4, Col. 5, lines 15-21).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 9,871,107 to Green in view of Choi (KR 20100096942 A) as applied to claim 7, and further in view of Tsunami (US 2020/0098634).
Regarding claim 9, Green in view of Choi discloses the high electron mobility transistor as claimed in claim 7. Further, Green does not specifically disclose that said inner recess portion of said second surface is separated from said first surface by a minimum distance ranging from 1 μm to 30 μm.
However, Tsunami teaches forming a semiconductor device (Tsunami, Fig. 5, ¶0005-¶0006, ¶0019-¶0021, ¶0063, ¶0078) comprising a tapered groove (17) in a body of the semiconductor substrate made difficult-to-tch material such as sapphire, and forming a backside metal on the tapered groove (17).
Further, Tsunami teaches that for a high-frequency operation (Tsunami, Fig. 5, ¶0004, ¶0012, ¶0061-¶0078), it is desirable that the thickness of the body (e.g., compound substrate 11) is in the range from 10 μm to 200 μm (Tsunami, Fig. 5, ¶0063). When the thickness of the body (11) is less than 10 μm, there is a risk that cracks occur in the body (11), and the insulating property of the body (11) also degrades. Also, Tsunami teaches that for a multi-finger type GaN transistor structure, the body (11) is thinned in the first region (R1) (Tsunami, Fig. 5, ¶0078) including tapered via holes (17) to reduce the distance from heat generating sites to the backside metal, so that the heat dissipation of the transistor can be enhanced, and the thickness of the body (11) is made sufficiently thick in the second regions (R2), to enhance the heat dissipation property while keeping the mechanical strength high.
Thus, a person of ordinary skill in the art would recognize that forming inner recess portion of the backside surface separated from the top surface by a specific minimum distance (as taught by Tsunami), the heat from the top surface of the body would be easily transferred to the backside metal film.
Thus, Tsunami recognizes that thinning the substrate to a specific minimum distance in the groove region impacts heat dissipation property and the mechanical strength of the device. Thus, thinning the substrate to a specific minimum distance in the groove region is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, thinning the substrate to a specific minimum distance in the groove region as Tsunami has identified the thinning the substrate to a specific minimum distance in the groove region as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at a specific minimum distance ranging from 1 μm to 30 μm, in order to enhance the heat dissipation property while keeping the mechanical strength high as taught by Tsunami (¶0078) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the high electron mobility transistor of Green/Choi by optimizing a specific minimum distance in the groove region as taught by Tsunami to have the high electron mobility transistor, wherein a said inner recess portion of said second surface is separated from said first surface by a minimum distance ranging from 1 μm to 30 μm, in order to enhance the heat dissipation property while keeping the mechanical strength high (Tsunami, ¶0063, ¶0068, ¶0078).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over KR 20100096942 A to Choi in view of Brech (US 2021/0057528) as applied to claim 7, and further in view of Tsunami (US 2020/0098634).
Regarding claim 9, Choi in view of Brech discloses the high electron mobility transistor as claimed in claim 7. Further, Choi does not specifically disclose that said inner recess portion of said second surface is separated from said first surface by a minimum distance ranging from 1 μm to 30 μm.
However, Tsunami teaches forming a semiconductor device (Tsunami, Fig. 5, ¶0005-¶0006, ¶0019-¶0021, ¶0063, ¶0078) comprising a tapered groove (17) in a body of the semiconductor substrate made difficult-to-tch material such as sapphire, and forming a backside metal on the tapered groove (17).
Further, Tsunami teaches that for a high-frequency operation (Tsunami, Fig. 5, ¶0004, ¶0012, ¶0061-¶0078), it is desirable that the thickness of the body (e.g., compound substrate 11) is in the range from 10 μm to 200 μm (Tsunami, Fig. 5, ¶0063). When the thickness of the body (11) is less than 10 μm, there is a risk that cracks occur in the body (11), and the insulating property of the body (11) also degrades. Also, Tsunami teaches that for a multi-finger type GaN transistor structure, the body (11) is thinned in the first region (R1) (Tsunami, Fig. 5, ¶0078) including tapered via holes (17) to reduce the distance from heat generating sites to the backside metal, so that the heat dissipation of the transistor can be enhanced, and the thickness of the body (11) is made sufficiently thick in the second regions (R2), to enhance the heat dissipation property while keeping the mechanical strength high.
Thus, a person of ordinary skill in the art would recognize that forming inner recess portion of the backside surface separated from the top surface by a specific minimum distance (as taught by Tsunami), the heat from the top surface of the body would be easily transferred to the backside metal film.
Thus, Tsunami recognizes that thinning the substrate to a specific minimum distance in the groove region impacts heat dissipation property and the mechanical strength of the device. Thus, thinning the substrate to a specific minimum distance in the groove region is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, thinning the substrate to a specific minimum distance in the groove region as Tsunami has identified the thinning the substrate to a specific minimum distance in the groove region as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at a specific minimum distance ranging from 1 μm to 30 μm, in order to enhance the heat dissipation property while keeping the mechanical strength high as taught by Tsunami (¶0078) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the high electron mobility transistor of Choi/Brech by optimizing a specific minimum distance in the groove region as taught by Tsunami to have the high electron mobility transistor, wherein a said inner recess portion of said second surface is separated from said first surface by a minimum distance ranging from 1 μm to 30 μm, in order to enhance the heat dissipation property while keeping the mechanical strength high (Tsunami, ¶0063, ¶0068, ¶0078).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891