DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-7 in the reply filed on 2/24/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 6-7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The applicant relies on functional blocks and triangles to represent the power supply module, an excitation power supply circuit, a reference voltage source circuit, an adjustable gain amplifier circuit, a voltage regulation circuit, an AD conversion circuit, a microprocessor, a shift register without disclosing the necessary structural components. The specification fails to satisfy the enablement requirement because a skilled artisan would be unable to construct the invention without undue experimentation.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regards to claim 6, The applicant relies on functional blocks and triangles to represent the a power supply module, an excitation power supply circuit, a reference voltage source circuit, an adjustable gain amplifier circuit, a voltage regulation circuit, an AD conversion circuit, a microprocessor, a shift
register without disclosing the necessary structural components. The claim is indefinite as they rely on functional labels rather than structural definition. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Hirler (US Pub no. 2013/0075724 A1) in view of Vervaeke (US Pub no 2007/0046287 A1) .
Regarding claim 1, Hirler et al discloses A high sensitivity magnetic sensing matrix chip with a two-dimensional electronic gas channel structure(2DEG transistor) [0020-0021]comprising a magnetic sensing matrix(60/60’)[0022]; the magnetic sensing matrix comprises several matrix units, and the several matrix units comprises a substrate(41), a buffer layer(42), a channel layer(20), and a barrier layer(30); a two-dimensional electron gas channel material heterojunction structure(2DEG transistor) composed of the buffer layer(42), the channel layer(20), and the barrier layer(30) is sequentially on the substrate(41) [0021], and a horizontal Hall element(60) and a switching device(10)[0028] are arranged above the channel layer(20); a main body of the horizontal Hall element(60) is composed of a cross-shaped barrier layer(30), and four ends of the cross- shaped barrier layer (30) fig. 1c)are respectively provided with electrode C1(611), electrode C2(612), electrode S1(621), and electrode S2(622)[0023]; the switching device comprises a gate electrode G(53), a source electrode S(51), and a drain electrode D(52); the source electrode S (51)and the drain electrode D(52) are arranged on the channel layer(20)[0020]. The limitation “grown” asserts the process by which the heterojunction is formed and is being treated as a product by process limitation. As set forth in MPEP 2113, product by process claims are NOT limited to the manipulations of the recited steps, only to the structure implied by the steps.
Hirler et al fails to teach a shift register, and a back- end interface circuit, wherein the shift register is sequentially connected to the magnetic sensor matrix and the back-end interface circuit; and the channel layer is provided with a dielectric layer extending to the barrier layer, and the gate electrode G is arranged above the dielectric layer; the electrode C2 is connected to the source electrode S through a metal interconnection line.
However, Vervaeke et al discloses a Hall sensor and switching hybrid device comprising shift register(4-phase measurement cycle infers a shift register is present)[0132-0133], and a back- end interface circuit[0138-0140], wherein the shift register is sequentially connected to the magnetic sensor matrix and the back-end interface circuit[0138-0140]; a channel layer provided with a dielectric layer [0103]extending to the barrier layer, and the gate electrode G is arranged above the dielectric layer[0160-0161]; the electrode C2 (TiJ and Bij) of the hall sensor is connected to the source electrode S(source contact) through a metal interconnection line(Lij and Rij)[0093][0102]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Hirler et al with the teachings of Vervaeke et al since providing back end interface and shift register results in circuitry to control the readout of the hall sensor array and provide offset reduction; providing a gate dielectric prevents leakage currents from flowing to the gate and enhances the gate breakdown voltage; Furthermore, since applying a metal interconnection line is one of finite solutions to send current through the hall sensor to generate a voltage to detect magnetic fields the claim would have been obvious that a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Regarding claim 2, Hirler et al discloses wherein the substrate(40) is one of
Si, SiC, and sapphire[0021]; the buffer(42) layer is one of AIN[0021].
Regarding claim 3, Hirler et al discloses, wherein the channel layer (20) is one of GaN,; the barrier layer(30) is the heterojunction material forming a two-dimensional electron gas channel with the channel layer(20) [0019].
Regarding claim 4, Vervaeke et al discloses wherein the dielectric layer is
one of Al2O₃, SiO₂[0103][0161]; the metal interconnection line adopts one of copper, tungsten, aluminum [0150].
Regarding claim 5, Hirler et al discloses wherein the thickness of the buffer layer(42) is; the thickness of the channel layer(20); the thickness of the barrier layer(30) but fails to teach the thickness 10-100nm; 0.1-10micron, 10-100 nm and the thickness of the dielectric layer is 20~50nm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to optimize the thickness to achieve 10-100nm; 0.1-10micron, 10-100 nm through routine experimentation "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation."In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, Vervaeke et al teaches the thickness of the dielectric layer [0161]but fails to teach is 20~50nm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to achieve a thickness of 20-50 nm through routine experimentation to optimize leakage. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. “In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
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/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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