Prosecution Insights
Last updated: October 02, 2026
Application No. 18/463,296

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Sep 08, 2023
Priority
Jun 12, 2023 — RE 10-2023-0074660
Examiner
SPRENGER, JAIME LYNN
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
3 (Non-Final)
100%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allowance Rate
2 granted / 2 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
27 currently pending
Career history
24
Total Applications
across all art units

Statute-Specific Performance

§103
54.7%
+14.7% vs TC avg
§102
26.3%
-13.7% vs TC avg
§112
15.3%
-24.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 2 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, 5, 8, 10-13, 16-18, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hang Kyu Kang et al. (US 20220189988 A1), and further in view of Joo Won Park et al. (US 20200185400 A1) hereinafter referred to as "Park". Regarding Claim 1 Kang teaches A semiconductor device (100 Fig 1-4b) comprising: a gate structure (GS1 and GS2 Para [0033]) including insulating layers (120 and 220) and conductive layers (130 and 230) alternately stacked; first supports (DM1) located in the gate structure, each first support including a second channel layer(140a Fig 4a); second supports (SP) located in the gate structure, and a contact structure (280) extending between the second supports (Fig 1-2) through the gate structure(Para[0034],[0035],[0104]), wherein the contact structure is connected to a corresponding conductive layer(Para[0104]), wherein the contact structure extends through at least one of the insulating layers and at least one of the conductive layers (Para[0104]), wherein a height of the second supports is greater than a height of the first supports (Fig 3 Para[0069]). Kang is not relied upon to teach each second support including a barrier layer PNG media_image1.png 569 599 media_image1.png Greyscale Park teaches similar second support that support the contact structures in an alternative lay out and park does teach each second support (59D Fig 1) including a barrier layer (53D) (see diagrams) PNG media_image2.png 639 820 media_image2.png Greyscale It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Kang such that the layout of the contact structures and supports to have second supports that include a barrier layer, as described in Park because the modification of the alternative advantageous layout allows for high integration while preventing/inhibiting a leakage current (Park Para[0004],[0015],[0016]) Regarding Claim 2 Kang in view of Park teaches The semiconductor device of claim 1, Kang teaches that the shape of the contact structure can be changed (Para[0104]) Park teaches wherein the contact structure comprises a first portion having a first width and a second portion having a second width, (Fig. 1 element 75 first portion is the lower portion and second portion is the upper portion) wherein the first portion is spaced apart from the second support (lower portion of 75 is spaced from 59D)whereas the second portion is in contact with the second support. (Fig. 1 elements 75 and 59D upper portion of 75 contacts 59D) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Kang such that the device has the layout of the contact structures and second supports thusly the device has contact structures with varying widths, as described in Park because the modification of the alternative layout allows for high integration while preventing/inhibiting a leakage current (Park Para[0004],[0015],[0016]) Regarding Claim 3 Kang in view of Park teaches The semiconductor device of claim 2, the advantageous layout of Park further teaches wherein the second width is greater than the first width. (Fig 1. element 75 upper portion of 75 has greater width than lower portion of 75) Regarding Claim 5 Kang in view of Park teaches The semiconductor device of claim 1, wherein the contact structure comprises: the advantageous layout of Park further teaches a contact plug (Para. [0018], Fig 1. element 75 includes 74); and an insulating spacer (Para. [0018], [0074], Fig 1. element 75 includes 73) surrounding sidewalls of the contact plug. (Para. [0018], Fig. 1 element 75 and 73). Regarding Claim 8 Kang in view of Park teaches The semiconductor device of claim 1, wherein the barrier layer includes a material having an etching selectivity with respect to the insulating layers and the conductive layers. (Park Para. [0059], [0069], [0064]. Since elements 41 and 45 may be made of a different material than elements 56D, 57D, and 58D therefore they have a relationship pertaining their etching selectivity). Regarding Claim 10 Kang in view of Park teaches The semiconductor device of claim 1, Kang further teaches wherein each first support has an elliptical shape (Para [0068]) in a plane defined by a first direction and a second direction intersecting the first direction. Regarding Claim 11, Kang in view of Park teaches The semiconductor device of claim 10, Kang further teaches wherein long axes (z direction that describes the supports height) of the first supports extend along a third direction intersecting the first direction and the second direction in the plane defined by the first direction and the second direction. (Para [0068] Fig1-3) Regarding Claim 12, Kang in view of Park teaches The semiconductor device of claim 10, Kang further teaches wherein the first supports (dm1) adjacent in the first direction or the second direction are arranged so that long axes (z direction that describes the supports height) of the first supports extend in directions intersecting each other. (Para [0068] Fig1-3) Regarding Claim 13, Kang in view of Park teaches The semiconductor device of claim 10, Kang further teaches wherein the first supports are arranged to have a radial shape extending from a center thereof. (Para [0068])(a radial shape such as a circle extending from the center of Dm1) Regarding Claim 16, Kang in view of Park teaches The semiconductor device of claim 1, Kang further teaches further comprising: channel structures (CH) extending through the gate structure (Fig. 4a), each channel structure including a first channel layer. (140) Regarding claim 17 Kang teaches A semiconductor device (100 Fig 1-4b) comprising: a gate structure (GS1 and GS2 Para [0033]) including insulating layers (120 and 220) and conductive layers (130 and 230) alternately stacked; first supports (DM1) located in the gate structure, each first support including a second channel layer (140a Fig 4a); second supports (SP) located in the gate structure; and a contact structure (280) disposed between the second supports (Fig 1-2) and extending into the gate structure (Para[0034],[0035],[0104]), wherein the contact structure is connected to a corresponding conductive layer (Para[0104]), and wherein a height of the second supports is greater than a height of the first supports (Fig 3 Para[0069]). Kang is not relied upon to teach each second support including a barrier layer different from the second channel layer and a spacer surrounding the barrier layer wherein the spacer surrounds a remaining portion of the sidewall of the barrier layer, Park does teach each second support (Fig 1 59D) including a barrier layer (53D) different from the second channel layer (different from the second channel layer taught in Kang that is a part of the first supports) and a spacer (54D) surrounding the barrier layer wherein the spacer surrounds a remaining portion of the sidewall of the barrier layer, (53D) (Fig. 4 54D surrounds 59D). wherein at least a part of a sidewall of the barrier layer is in contact with the contact structure (Fig. 4-8 elements 75 and 59D) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Kang such that the layout of the contact structures and second supports have second supports that include a barrier layer, as described in Park because the modification of the alternative advantageous layout allows for high integration while preventing/inhibiting a leakage current (Park Para[0004],[0015],[0016]) Regarding Claim 18 Kang in view of Park teaches The semiconductor device of claim 17, Kang teaches that the shape of the contact structure can be changed (Para[0104]) The advantageous layout of Park further teaches wherein the contact structure comprises a first portion having a first width and a second portion having a second width (Fig. 1 element 75 first portion is the lower portion and second portion is the upper portion), wherein the first portion is spaced apart from the second support (lower portion of 75 is spaced from 59D), and wherein the second portion is in contact with the second support. (Fig. 1 elements 75 and 59D upper portion of 75 contacts 59D) Regarding Claim 20 Kang in view of Park teaches The semiconductor device of claim 17, further comprising: Kang further teaches channel structures (CH) extending through the gate structure (Fig. 4a), each channel structure including a first channel layer. (140) Claim(s) 4, 7, 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Park as applied above, and further in view of Kim Dong Young et al. (KR 20210104607 A), hereinafter referred to as “Young”. Regarding Claim 4 Kang in view of Park teaches The semiconductor device of claim 1, Park further teaches in the alternative layout PNG media_image3.png 260 265 media_image3.png Greyscale wherein the contact structures are in contact with at least one of the second supports (Para. [0018], Fig. 1 and 3 elements 75 and 59D). Kang in view of Park does not disclose second support protrudes into the contact structures. Young, also a semiconductor device similar to Kang that does disclose one second support protrudes into the contact structures (See Young translation, Fig. 8B elements 170 and 160). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device described in Kang in view of Park such that the contact structures are in contact with at least one of the second supports, and the at least one second support protrudes into the contact structures, as described by Young, because applying a known applicable element to a known base device would result in a predictable result. Doing so allows for the support structure to support the stacked gate structure without bursting while the barrier layer provides protection and prevents the contact structure from penetrating the support structure (See Young; “The support structure 170 may include a vertical pillar 171 and a barrier layer 172 covering at least an outer surface of the vertical pillar 171 , and the barrier layer 172 is a contact structure during the process of forming the contact structures 160 . Even if the structures 160 come into contact with the support structure 170 , it is possible to prevent the structures 160 from extending into the support structure 170 . Accordingly, the contact structures 160 may be self-aligned, and the support structure 170 may support the stacked structure GS without bursting. Also, the barrier layer 172 may prevent the contact structures 160 from penetrating into one side surface of the support structure 170 and extending below the gate electrodes 130 .”). Regarding Claim 7 Kang in view of Park teaches The semiconductor device of claim 1, Kang in view of Park does not disclose wherein the barrier layer protrudes into the contact structure. Young discloses a semiconductor device wherein the barrier layer protrudes into the contact structure (Fig. 8B elements 172 and 160). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device described in Kang in view of Park such that the barrier layer protrudes into the contact structure, as described in Young, because doing so allows for the support structure to support the stacked gate structure without bursting while the barrier layer provides protection and prevents the contact structure from penetrating the support structure (See Young). Regarding Claim 9 Kang in view of Park teaches The semiconductor device of claim 1, Park further teaches wherein the barrier layer as set forth above uses Silicon nitride barrier layer (Para. [0065]) Thus, Park does not disclose wherein the barrier layer includes at least one of titanium nitride or tungsten. Young discloses wherein the barrier layer includes at least one of titanium nitride or tungsten. (See Young; ). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device described in Kang in view of Park such that the barrier layer includes at least one of titanium nitride and tungsten, as described by Young, since titanium nitride is a well-known metal nitride barrier layer and the selection of a specific well-known similar barrier layer would have been within the purview of one of ordinary skill in the art. Claim(s) 14, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Park as applied above, and further in view of Hang-Ting Lue et al. (US 20150340369 A1), hereinafter referred to as “Lue”. Regarding Claim 14, Kang in view of Park discloses the semiconductor device of claim 1, the advantageous layout of Park further teaches PNG media_image4.png 409 429 media_image4.png Greyscale wherein, in a plane defined by a first direction and a second direction intersecting the first direction, each of the second supports (See diagram). Kang in view of Park is not relied upon to teach extension portions each having an elliptical shape and connection portions connecting the extension portions. Lue discloses a memory device and teaches PNG media_image5.png 335 462 media_image5.png Greyscale a memory structure with extension portions (Fig. 4 elements 41 and 42) having an elliptical shape (Fig. 4 elements 41 and 42) and connection portions connecting the extension portions (Fig. 4 elements 28 and 29). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device described in Kang in view of Park such that extension portions having elliptical shape connected to the connection portions, as described by Lue, because doing so allows for the connection portions (isolation pillars 28, and 29) to divide the even and odd word line which allows for independent double gate operation. And the elliptical shape’s increased length allows for the connection between the support structure and connection portion and decreases the number of missed connections. (See Lue [0042], [0048], [0057]). Regarding Claim 15, Kang in view of Park further in view of Lue disclose the semiconductor device of claim 14, Kang in view of Park is not relied upon to teach wherein the extension portions have a radial shape expanded from the connection portions. Lue discloses wherein the extension portions have a radial shape expanded from the connection portions (see Liu Fig. 5a). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device described in Kang in view of Park such that the extension portions have a radial shape expanded from the connection portions, as described by Lue, because doing so allows for the divide of even and odd word lines allowing for independent double gate operation (Lue Para. [0042], [0048], [0057]). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. JANG; Jung Shik (US-20220254716-A1). Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAIME LYNN SPRENGER whose telephone number is (571)272-8444. The examiner can normally be reached Monday - Friday, 9:00a.m. - 5:00p.m. ET.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, SUE PURVIS can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAIME LYNN SPRENGER/ Examiner, Art Unit 2893 /SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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Prosecution Timeline

Sep 08, 2023
Application Filed
Dec 29, 2025
Non-Final Rejection mailed — §103
Mar 10, 2026
Response Filed
Apr 07, 2026
Final Rejection mailed — §103
Jun 05, 2026
Response after Non-Final Action
Jun 26, 2026
Request for Continued Examination
Jun 30, 2026
Response after Non-Final Action
Aug 19, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12677542
DISPLAY PANEL AND ELECTRONIC APPARATUS INCLUDING THE SAME
2y 7m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 1 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
2y 8m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 2 resolved cases by this examiner. Grant probability derived from career allowance rate.

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