DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. The application has an effective filing date of June 12th, 2023.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 17-20 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Joo Won Park et al. (US 20200185400 A1) hereinafter referred to as "Park".
Regarding Claim 17 Park teaches
A semiconductor device comprising:
a gate structure including insulating layers and conductive layers alternately stacked (Para. [0005], Fig. 1-2 element 40);
first supports located in the gate structure, (Fig. 1 element 59D, see annotated figure 1 below) each first support (Para. [0017], Fig. 1 element 59D) including a second channel layer(any layer of 59D can be a channel layer other than 53D);
second supports located in the gate structure, (Fig. 1 element 59D an adjacent set of supports see annotated figure 1 below) each second support (59D) including a barrier layer (53D) different from the second channel layer (any other layer than 53D); and
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a contact structure disposed between the second supports and extending into the gate structure (Para. [0016], Fig. 1 contact structures 75 through gate structure 40), wherein the contact structure is connected to a corresponding conductive layer. (Para. [0037])
Regarding Claim 18 Park teaches
The semiconductor device of claim 17, wherein the contact structure comprises a first portion having a first width and a second portion having a second width, (Fig. 1 element 75 first portion is the lower portion and second portion is the upper portion)
wherein the first portion is spaced apart from the second support (lower portion of 75 is spaced from 59D), and wherein the second portion is in contact with the second support. (Fig. 1 elements 75 and 59D upper portion of 75 contacts 59D)
Regarding Claim 19 Park teaches
The semiconductor device of claim 17, wherein the first supports are spaced apart from the contact structure (at least a portion of the first supports in Fig 1 are spaced apart from contact structure 75), wherein each of the second supports includes the barrier layer (Fig. 1 element 59D and 53D), and wherein a sidewall of the barrier layer is in contact with the contact structure. (Fig. 4-8 elements 75 and 59D)
Regarding Claim 20 Park teaches
The semiconductor device of claim 17, further comprising:
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channel structures extending through the gate structure(Fig. 1 element 59), each channel structure including a first channel layer. (Para. [0017], Fig. 10)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 6, 8, 10-13, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park, further in view of Keisuke Izumi et al. (US 9236392 B1) hereinafter referred to as “Izumi”.
Regarding claim 1 Park teaches
A semiconductor device comprising:
a gate structure including insulating layers and conductive layers alternately stacked; (Para. [0005], Fig. 1-2 element 40)
first supports located in the gate structure (Fig. 1 element 59D, see annotated figure 1 below), each first support including a second channel layer; (Para. [0017], Fig. 1 element 59D)
second supports located in the gate structure (Fig. 1 element 59D an adjacent set of supports see annotated figure 1 below), each second support including a barrier layer (Fig. 1 element 59D and 53D); and
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a contact structure extending between the second supports through the gate structure (Para. [0016], Fig. 1 contact structures 75 through gate structure 40), wherein the contact structure is connected to a corresponding conductive layer, (Para. [0037])
Park does not teach
wherein the contact structure extends through at least one of the insulating layers and at least one of the conductive layers.
Izumi teaches interconnect structures
wherein the contact structure (Fig 26 element 66) extends through at least one of the insulating layers(32) and at least one of the conductive layers(46).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Park such that the contact structure extends through at least one of the insulating layers and at least one of the conductive layers, as described in Izumi because the modification eliminates the need for the patterned staircase structure (Fig 17, 26) ]
Regarding Claim 2, Park in view of Izumi teaches
The semiconductor device of claim 1,
Park further teaches
wherein the contact structure comprises a first portion having a first width and a second portion having a second width, (Fig. 1 element 75 first portion is the lower portion and second portion is the upper portion) wherein the first portion is spaced apart from the second support (lower portion of 75 is spaced from 59D) whereas the second portion is in contact with the second support. (Fig. 1 elements 75 and 59D upper portion of 75 contacts 59D)
Regarding Claim 3, Park in view of Izumi teaches
The semiconductor device of claim 2,
Park further teaches
, wherein the second width is greater than the first width. (Fig 1. element 75 upper portion of 75 has greater width than lower portion of 75)
Regarding Claim 5, Park in view of Izumi teaches
The semiconductor device of claim 1,
Park further teaches
, wherein the contact structure comprises:
a contact plug (Para. [0018], Fig 1. element 75 includes 74); and
an insulating spacer (Para. [0018], [0074], Fig 1. element 75 includes 73) surrounding sidewalls of the contact plug. (Para. [0018], Fig. 1 element 75 and 73)
Regarding Claim 6, Park in view of Izumi teaches
The semiconductor device of claim 1,
Park further teaches
wherein each of the second supports comprises:
a barrier layer extending through the gate structure (Fig. 1 element 59D and 53D), wherein at least a part of a sidewall of the barrier layer is in contact with the contact structure (Fig. 4-8 elements 75 and 59D); and
a spacer (54D) surrounding a remaining sidewall of the barrier layer (53D) (Fig. 4 54D surrounds 59D).
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Regarding Claim 8, Park in view of Izumi teaches
The semiconductor device of claim 6,
Park further teaches
wherein the barrier layer includes a material having an etching selectivity with respect to the insulating layers and the conductive layers (Para. [0059], [0069], [0064]. Since elements 41 and 45 may be made of a different material than elements 56D, 57D, and 58D therefore they have a relationship pertaining their etching selectivity).
Regarding Claim 10, Park in view of Izumi teaches
The semiconductor device of claim 1,
Park further teaches
wherein each first support has an elliptical shape in a plane defined by a first direction and a second direction intersecting the first direction. (Fig. 3-8 element 59D)
Regarding Claim 11, Park in view of Izumi teaches
The semiconductor device of claim 10,
Park further teaches
wherein long axes of the first supports extend along a third direction intersecting the first direction and the second direction in the plane defined by the first direction and the second direction. (Fig. 3-8 element 59D)
Regarding Claim 12, Park in view of Izumi teaches
The semiconductor device of claim 10,
Park further teaches
wherein the first supports adjacent in the first direction or the second direction are arranged so that long axes of the first supports extend in directions intersecting each other. (Fig. 3-8 element 59D)
Regarding Claim 13, Park in view of Izumi teaches
The semiconductor device of claim 10,
Park further teaches
wherein the first supports are arranged to have a radial shape extending from a center thereof. (Fig. 3-8 element 59D)
Regarding Claim 16, Park in view of Izumi teaches
The semiconductor device of claim 1,
Park further teaches
further comprising:
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channel structures extending through the gate structure (Fig. 1 element 59), each channel structure including a first channel layer. (Para. [0017], Fig. 10)
Claims 4, 7, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view Izumi as applied to claims 1 and 6 further in view of Kim Dong Young et al. (KR 20210104607 A), hereinafter referred to as “Young”.
Regarding Claim 4 Park in view of Izumi teaches
The semiconductor device of claim 1,
Park further teaches
wherein the contact structures are in contact with at least one of the second supports (Para. [0018], Fig. 1 and 3 elements 75 and 59D).
Park does not disclose second support protrudes into the contact structures.
Young, also a semiconductor device similar to Park, discloses
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one second support protrudes into the contact structures (See Young translation, Fig. 8B elements 170 and 160).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device described in Park such that the contact structures are in contact with at least one of the second supports, and the at least one second support protrudes into the contact structures, as described by Young, because applying a known applicable element to a known base device would result in a predictable result. Doing so allows for the support structure to support the stacked gate structure without bursting while the barrier layer provides protection and prevents the contact structure from penetrating the support structure (See Young; “The support structure 170 may include a vertical pillar 171 and a barrier layer 172 covering at least an outer surface of the vertical pillar 171 , and the barrier layer 172 is a contact structure during the process of forming the contact structures 160 . Even if the structures 160 come into contact with the support structure 170 , it is possible to prevent the structures 160 from extending into the support structure 170 . Accordingly, the contact structures 160 may be self-aligned, and the support structure 170 may support the stacked structure GS without bursting. Also, the barrier layer 172 may prevent the contact structures 160 from penetrating into one side surface of the support structure 170 and extending below the gate electrodes 130 .”).
Regarding Claim 7 Park in view of Izumi teaches
The semiconductor device of claim 6,
Park does not disclose
wherein the barrier layer protrudes into the at least one contact structure.
Young discloses a semiconductor device where
a barrier layer which protrudes into the at least one contact structure (Fig. 8B elements 172 and 160).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device described in Park such that the barrier layer protrudes into the at least one contact structure, as described in Young, because doing so allows for the support structure to support the stacked gate structure without bursting while the barrier layer provides protection and prevents the contact structure from penetrating the support structure (See Young).
Regarding Claim 9 Park in view of Izumi teaches
The semiconductor device of claim 6
Park further teaches
wherein the barrier layer as set forth above uses Silicon nitride barrier layer (Para. [0065])
Thus, Park does not disclose the barrier layer includes at least one of titanium nitride and tungsten.
Young discloses the barrier layer includes at least one of titanium nitride and tungsten (See Young; ).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device described in Park such that the barrier layer includes at least one of titanium nitride and tungsten, as described by Young, since titanium nitride is a well-known metal nitride barrier layer and the selection of a specific well-known similar barrier layer would have been within the purview of one of ordinary skill in the art.
Claims 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view Izumi as applied to claims 1 further in view of Hang-Ting Lue et al. (US 20150340369 A1), hereinafter referred to as “Lue”.
Regarding Claim 14, Park in view of Izumi discloses
the semiconductor device of claim 1,
Park further teaches
wherein, in a plane defined by a first direction and a second direction intersecting the first direction, each of the second supports (See Figure 4 in 103 rejections above).
Park does not disclose
extension portions each having an elliptical shape and connection portions connecting the extension portions.
Lue discloses a memory device and teaches
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a memory structure with extension portions (Fig. 4 elements 41 and 42) having an elliptical shape (Fig. 4 elements 41 and 42) and connection portions connecting the extension portions (Fig. 4 elements 28 and 29).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device described in Park such that extension portions having elliptical shape connected to the connection portions, as described by Lue, because doing so allows for the connection portions (isolation pillars 28, and 29) to divide the even and odd word line which allows for independent double gate operation. And the elliptical shape’s increased length allows for the connection between the support structure and connection portion and decreases the number of missed connections. (See Lue [0042], [0048], [0057]).
Regarding Claim 15, Park in view of Izumi further in view of Lue disclose
the semiconductor device of claim 14,
Park does not disclose
wherein the extension portions have a radial shape expanded from the connection portions.
Lue discloses
wherein the extension portions have a radial shape expanded from the connection portions (see Liu Fig. 5a).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device described in Park such that the extension portions have a radial shape expanded from the connection portions, as described by Lue, because doing so allows for the divide of even and odd word lines allowing for independent double gate operation (Lue Para. [0042], [0048], [0057]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-7, 9, 17-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAIME LYNN SPRENGER whose telephone number is (571)272-8444. The examiner can normally be reached Monday - Thursday, 7:30a.m. - 5:00p.m. ET..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAIME LYNN SPRENGER/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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