DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 6-7, 10, 11, 13-14, 19, 20-21, 23, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto et al. (US 2010/0025569) (“Matsumoto”) in view of Miyazawa et al. (US 2019/0043910) (“Miyazawa”).
With regard to claim 1, figs. 1-2 and 19-20 of Matsumoto discloses an imaging device comprising: a pixel region 12 including a pixel substrate portion 12 and an amplifying transistor Amp that is located in the pixel substrate portion 11 and that outputs a signal voltage corresponding to an amount of signal charge (“signal output from the amplifying transistor Amp”, par [0241]); and a first peripheral region 13 including a first peripheral substrate portion 13 and a first peripheral transistor 50 located in the first peripheral substrate portion 13, and when at least one type of impurity (“Germanium”, par [0154]) that contributes to inhibition of transient enhanced diffusion of a conductive impurity (“pocket ion implantations”, par [0154]) defined as a specific species (“germanium”, par [0154]), the first peripheral transistor 50 includes a first specific layer 65 that is located in the first peripheral substrate portion 13 and that contains the conductive impurity (“pocket ion implantations”, par [0154]) and the specific species (“germanium”, par [0154]).
Matsumoto does not disclose that the pixel substrate portion and the first peripheral substrate portion are stacked on each other.
However, fig. 6 of Miyazawa discloses that the pixel substrate portion 1 and the first peripheral substrate portion 12 are stacked on each other.
Therefore, it would have been obvious to one of ordinary skill in the art to form the pixel portion and peripheral circuit portion of Matsumoto stacked on top of each other as taught in Miyazawa in order to enable further downsizing of device size. See abstract of Miyazawa.
With regard to claim 3, figs. 1-2 and 19-20 of Matsumoto discloses that the specific species (“ion implantation of germanium (Ge)“, par [0154]) contains at least one selected from the group consisting of germanium (“Ge”, par [0154]), silicon, and argon.
With regard to claim 6, figs. 1-2 and 19-20 of Matsumoto discloses that the first peripheral transistor (Nch LOW-BREAKDOWN VOLTAGE TRANSISTOR, fig. 20) includes a first source 54, a first drain 55, and a first extension diffusion layer 61, the first extension diffusion layer 61 is adjacent to the first source 54 or the first drain 55 and shallower than the first source 54 and the first drain 55, and the first extension diffusion layer 61 includes the first specific layer (“ion implantation of germanium”, par [0154]).
With regard to claim 7, figs. 1-2 and 19-20 of Matsumoto discloses that the first peripheral transistor (Nch LOW-BREAKDOWN VOLTAGE TRANSISTOR, fig. 20) includes a first source 54, a first drain 55, and a first pocket diffusion layer 65, the first pocket diffusion layer 65 is adjacent to the first source 61 or the first drain, and the first pocket diffusion layer 65 includes the first specific layer (“ion implantation of germanium”, par [0154]).
With regard to claim 10, figs. 1-2 of Matsumoto discloses the pixel region 12 further includes a photoelectric conversion layer 21.
Matsumoto does not disclose that the photoelectric conversion layer, the pixel substrate portion, and the first peripheral substrate portion are stacked on each other.
However, fig. 6 of Miyazawa disclose that the photoelectric conversion layer 16, the pixel substrate portion 11, and the first peripheral substrate portion 12 are stacked on each other.
Therefore, it would have been obvious to one of ordinary skill in the art to form the pixel portion and peripheral circuit portion of Matsumoto stacked on top of each other as taught in Miyazawa in order to enable further downsizing of device size. See abstract of Miyazawa.
With regard to claim 11, figs. 1-2 of Matsumoto discloses the first peripheral transistor 50 includes an end-of-range defect (“implantation defects”, par [0154]), at least part of the first specific layer (“ion implantation of germanium (Ge)”, par [0154]) is located above the end-of-range defect (“implantation defects”, par [0154]) and overlaps the end-of-range defect (“implantation defects”, par [0154]) in a plan view.
With regard to claim 13, Masumoto do not disclose an insulating part, wherein the pixel substrate portion and the first peripheral substrate portion are stacked with the insulating part disposed between the pixel substrate portion and the first peripheral substrate portion.
However, fig. 6 of Miyazawa discloses an insulating part 102, wherein the pixel substrate portion 102 and the first peripheral substrate portion 12 are stacked with the insulating part 102 disposed between the pixel substrate portion 11 and the first peripheral substrate portion 12.
Therefore, it would have been obvious to one of ordinary skill in the art to form the pixel portion and peripheral circuit portion of Matsumoto stacked on top of each other as taught in Miyazawa in order to enable further downsizing of device size. See abstract of Miyazawa.
With regard to claim 14, figs. 1-2 of Matsumoto discloses further comprising a second peripheral region (Nch High-Breakdown Voltage Transistor, fig. 2) including a second peripheral substrate portion (11 under Nch High-Breakdown Voltage Transistor, fig. 2) and a second peripheral transistor (Nch High-Breakdown Voltage Transistor, fig. 2) located in the second peripheral substrate portion (11 under Nch High-Breakdown Voltage Transistor, fig. 2), wherein the first peripheral substrate portion (11 under Nch Low-Breakdown Voltage Transistor, fig. 2) and the second peripheral substrate portion (11 under Nch High-Breakdown Voltage Transistor, fig. 2) are included in one semiconductor substrate 11.
With regard to claim 19, figs. 1-2 of Matsumoto discloses an operating voltage of the first peripheral transistor (Nch Low-Breakdown Voltage Transistor, fig. 2) is lower than an operating voltage of the second peripheral transistor (Nch High-Breakdown Voltage Transistor, fig. 2).
With regard to claim 20, figs. 1-2 of Matsumoto discloses a threshold voltage of the first peripheral transistor (Nch Low-Breakdown Voltage Transistor, fig. 2) is lower than a threshold voltage of the second peripheral transistor (Nch High-Breakdown Voltage Transistor, fig. 2).
With regard to claim 21, figs. 1-2 of Matsumoto discloses the amplifying transistor Amp includes a gate 32, a source 34, and a drain 34, the first peripheral transistor (Nch Low-Breakdown Voltage Transistor, fig. 2) includes a gate 52, a source 54, and a drain 55, the imaging device 1 is configured such that the gate 32 of the amplifying transistor Amp is located closer to a position of incidence of incident light (“incident light”, par [0169]) on the imaging device 1 than the source 34 of the amplifying transistor Amp and the drain 34 of the amplifying transistor Amp in a direction parallel with a thickness of the imaging device 1, and the imaging device 1 is configured such that the gate of the first peripheral transistor (Nch Low-Breakdown Voltage Transistor, fig. 2) is located closer to the position of incidence of the incident light (“incident light”, par [0169]) on the imaging device 1 than the source 54 of the first peripheral transistor (Nch Low-Breakdown Voltage Transistor, fig. 2) and the drain 55 of the first peripheral transistor (Nch Low-Breakdown Voltage Transistor, fig. 2) in the direction parallel with the thickness of the imaging device.
With regard to claim 23, Matsumoto does not disclose the imaging device is configured such that the pixel substrate portion is located closer to a position of incidence of incident light on the imaging device than the first peripheral substrate portion in a direction parallel with a thickness of the imaging device.
However, fig. 6 of Miyazawa disclose the imaging device is configured such that the pixel substrate portion 11 is located closer to a position of incidence of incident light on the imaging device than the first peripheral substrate portion 12 in a direction parallel with a thickness of the imaging device.
Therefore, it would have been obvious to one of ordinary skill in the art to form the pixel portion and peripheral circuit portion of Matsumoto stacked on top of each other as taught in Miyazawa in order to enable further downsizing of device size. See abstract of Miyazawa.
With regard to claim 26, Matsumoto does not disclose a stacked structure including the pixel substrate portion and the first peripheral substrate portion; and heating the stacked structure.
However, fig. 6 of Miyazawa discloses a stacked structure including the pixel substrate portion 12 and the first peripheral substrate portion 11; and heating the stacked structure (“annealing treatment”, par [0368]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the pixel portion and peripheral circuit portion of Matsumoto stacked on top of each other as taught in Miyazawa in order to enable further downsizing of device size. See abstract of Miyazawa. It would also have been obvious for the pixel portion and peripheral circuit portion of Matsumoto to be annealed as taught in Miyazawa in order to bond the structural bodies together. See par [0368] of Miyazawa.
Applicant's claim 26 do not distinguish over the Matsumoto and Miyazawa reference regardless of the process used to form the pixel and peripheral substrate stack because only the final product is relevant, not the process of making such as by heating.
Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps. See In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Once a product appearing to be substantially identical is found and a 35 U.S.C. 102/103 rejection made, the burden shifts to the applicant to show an unobvious difference. See In re Fessmann, 489 F.2d 742, 744, 180 USPQ 324, 326 (CCPA 1974), In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983), and Ex parte Gray, 10 USPQ2d 1922 (Bd. Pat. App. & Inter. 1989). The use of 35 U.S.C. 102/103 rejections for product-by-process claims has been approved by the courts. See In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972). See also MPEP § 2113.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto et al. (US 2010/0025569) (“Matsumoto”), Miyazawa et al. (US 2019/0043910) (“Miyazawa”), and Noda (US 2009/0278209).
With regard to claim 2, Matsumoto and Miyazawa do not disclose that the specific species contains at least one selected from the group consisting of carbon, nitrogen, and fluorine.
However, fig. 1 of Noda discloses that the specific species contains at least one selected from the group consisting of carbon (“P-type extension high-concentration diffusion layer 106 contains carbon (C)”, par [0065]), nitrogen, and fluorine.
Therefore, it would have been obvious to one of ordinary skill in the art to form replace the ion implantation of germanium of Matsumoto with carbon as taught in Noda in order to removes excess point defects in the semiconductor region during annealing of the extension diffusion layers. As a result, excess point defects generated by ion implantation are reduced, so that the TED of an impurity atom, such as boron, phosphorus or the like, is suppressed, and therefore, the junction depth of each extension diffusion layer can be kept shallow. See par [0023] of Noda.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto et al. (US 2010/0025569) (“Matsumoto”), Miyazawa et al. (US 2019/0043910) (“Miyazawa”), and Miyagawa (US 2006/0192234).
With regard to claim 4, Matsumoto and Miyazawa do not disclose a gate length of the first peripheral transistor is shorter than a gate length of the amplifying transistor.
However, Miyagawa discloses a gate length of the first peripheral transistor is shorter than a gate length of the amplifying transistor (“a gate length of the amplification transistor in pixels is likely to be longer than that of the transistor in the peripheral circuitry region.”, par [0045]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the gate length of the peripheral transistor of Matsumoto shorter than the gate length of the amplifying transistor as taught in Miyagawa in order to provide different capability and driving voltage between the pixel region and peripheral circuitry region. See par [0044] of Miyagawa.
With regard to claim 5, figs. 13-14 of Matsumoto disclose the amplifying transistor (AMPLIFYING TRANSISTOR, FIG. 13) includes an amplifying gate insulator film 31, the first peripheral transistor includes a first peripheral gate insulator film 51L.
Matsumoto and Miyazawa do not disclose that the first peripheral gate insulator film is thinner than the amplifying gate insulator film.
However, Miyagawa discloses that the first peripheral gate insulator film (“gate oxide thickness of a transistor in a peripheral circuitry region “, par [0045]) is thinner (“gate oxide thickness of a transistor in a peripheral circuitry region is set to be thinner than that in a pixel region” par [0045]) than the amplifying gate insulator film.
Therefore, it would have been obvious to one of ordinary skill in the art to form the gate insulating film in the peripheral transistor of Matsumoto thinner than the gate oxide of the amplifying transistor as taught in Miyagawa in order to provide different capability and driving voltage between the pixel region and peripheral circuitry region. See par [0044] of Miyagawa.
Allowable Subject Matter
Claims 8-9, 12, 15-18, and 22 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 24-25 are allowed.
The primary reason for the allowance of claim 24 is that Matsumoto et al. (US 2010/0025569) (“Matsumoto”), Miyazawa et al. (US 2019/0043910) (“Miyazawa”), and Noda (US 2009/0278209) do not disclose that the the first pixel substrate, the second pixel substrate, and the first peripheral substrate are stacked in this order from a position of incidence of incident light on the imaging device.
Conclusion
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/BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893