DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-2, 10, and 13 are amended. Claims 3-6 are cancelled. Claims 1-2 and 7-20 are present for examination.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on October 20, 2023.
Specification
The objection to the specification of January 30, 2026 has been withdrawn.
Response to Arguments
Applicant’s arguments, see pages 8-12, filed March 24, 2026, with respect to the rejection(s) of claim(s) 1, 10, and 13 under 35 U.S.C. 102(a)(2) and 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Rajashekhar (US 2021/0265385 A1).
In the interest of compact prosecution, the Examiner suggests the Applicant more clearly define the geometric proximity of each layer with respect to each other (e.g. a layer provided in direct contact of an adjacent layer rather than on a side face of the adjacent layer). The Examiner is available at the number below for an interview to discuss ideas at the Applicant’s convenience.
Claim Rejections - 35 USC § 102
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 7, and 9-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Rajashekhar (US 2021/0265385 A1).
Claim 1, Rajashekhar discloses a semiconductor device () comprising:
a stacked film (alternating stack of insulating layers 136, dielectric barrier liners 34, and electrically conductive layer 146 is a stacked film, hereinafter, stacked film 136/146, [0236], Fig. 24C) including a plurality of electrode layers (stacked film 136/146 includes electrically conductive layer 146 which is a plurality of electrode layers, hereinafter, plurality of electrode layers 146, [0236], Fig. 24C) and a plurality of insulators (stacked film 136/146 includes insulating layers 136 which are a plurality of insulators, hereinafter, plurality of insulators 136, [0236], Fig. 24C) that are alternately provided in a first direction (plurality of electrode layers 146 and plurality of insulators 136 are alternately provided in a first direction (i.e. vertical direction), [0236], Fig. 24C); and
a second insulator (dielectric barrier liners 34 is a second insulator, hereinafter, second insulator 34, [0230], Fig. 24C) provided on a side face of the stacked film 136/146 in the stacked film 136/146 (second insulator 34 is provided on a side face of the stacked film 136/146 within the stacked film 136/146, [0230], Fig. 24C);
a charge storing layer (charge storage material portion 124 is a charge storing layer, hereinafter, charge storing layer 124, [0234], Fig. 24C) provided on a side face of the second insulator 34 in the stacked film 136/146 (charge storing layer 124 is provided on a side face of the second insulator 34 in the stacked film 136/146, [0234], Fig. 24C);
a third insulator (tunneling dielectric layer 26 is a third insulator, hereinafter, third insulator 26, [0213], Fig. 24C) provided on a side face of the storing layer 124 in the stacked film 136/146 (third insulator 26 is provided on a side face of the storing layer 124 in the stacked film 136/146, [0213], Fig. 24C); and
a semiconductor layer (first semiconductor channel layer 601 is a semiconductor layer, hereinafter, semiconductor layer 601, [0088], Fig. 24C) provided on a side face of the third insulator 26 in the stacked film 136/146 (semiconductor layer 601 is provided on a side face of the third insulator 26 in the stacked film 136/146, [0088], Fig. 24C),
wherein at least one of the plurality of electrode layers 146 includes:
a first layer (metallic barrier liner 146A is a first layer, hereinafter, first layer 146A, [0194], Fig. 24C) provided on a side face of the second insulator 34 (first layer 146A is provided on a side face of the second insulator 34, [0194], Fig. 24C) and including a metal element (first layer 146A includes a metal element, [0194], Fig. 24C);
a first insulator (silicon oxide blocking dielectric portions 122 is a first insulator, hereinafter, first insulator 122, [0229], Fig. 24C) that is in contact with the first layer 146A (first insulator 122 is in contact with the first layer 146A, [0242], Fig. 24C) and includes silicon and oxygen (first insulator 122 includes silicon and oxygen (i.e. silicon oxide), [0229], Fig. 24C); and
a second layer (metallic fill material layer 146B is a second layer, hereinafter, second layer 146B, [0195], Fig. 24C) that is in contact with the first insulator 122 (second layer 146B is in contact with the first insulator 122, [0195], Fig. 24C) and includes molybdenum or tungsten.
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Fig. 24C (Rajashekhar) – Illustrates a three-dimensional memory device including a first layer 146A including a metal element, a first insulator 122 that is in contact with the first layer 146A and includes silicon and oxygen (i.e. silicon oxide), and a second layer 146B that is in contact with the first insulator 122 and includes molybdenum or tungsten.
Claim 2, Rajashekhar discloses the device (device, Fig. 24C) of Claim 1.
Rajashekhar discloses wherein the first layer is a conductor layer including titanium as the metal element (first layer 146A is a conductor layer including titanium as the metal element, [0194], Fig. 24C).
Claim 7, Rajashekhar discloses the device (device, Fig. 24C) of Claim 1.
Rajashekhar discloses wherein the first insulator is an SiOx film where Si denotes silicon, O denotes oxygen, and "x" is a real number satisfying 0 <"x"< 2 (first insulator 122 is a SiOx film where Si denotes silicon, O denotes oxygen, and "x" is a real number satisfying 0 <"x"< 2 (i.e. silicon oxide), [0229], Fig. 24C).
Claim 9, Rajashekhar discloses the device (device, Fig. 24C) of Claim 1.
Rajashekhar discloses wherein a thickness of the first insulator is 7 nm or less (thickness of first insulator 122 is 7nm or less (i.e. 1 nm to 10 nm), [0081], Fig. 24C).
Claim 10, Rajashekhar discloses a semiconductor device (semiconductor device, Fig. 24C) comprising:
a stacked film (alternating stack of insulating layers 136, dielectric barrier liners 34, and electrically conductive layer 146 is a stacked film, hereinafter, stacked film 136/146, [0236], Fig. 24C) including a plurality of electrode layers (stacked film 136/146 includes electrically conductive layer 146 which is a plurality of electrode layers, hereinafter, plurality of electrode layers 146, [0236], Fig. 24C) and a plurality of insulators (stacked film 136/146 includes insulating layers 136 which are a plurality of insulators, hereinafter, plurality of insulators 136, [0236], Fig. 24C) that are alternately provided in a first direction (plurality of electrode layers 146 and plurality of insulators 136 are alternately provided in a first direction (i.e. vertical direction), [0236], Fig. 24C); and
a second insulator (dielectric barrier liners 34 is a second insulator, hereinafter, second insulator 34, [0230], Fig. 24C) provided on a side face of the stacked film 136/146 in the stacked film 136/146 (second insulator 34 is provided on a side face of the stacked film 136/146 within the stacked film 136/146, [0230], Fig. 24C);
a charge storing layer (charge storage material portion 124 is a charge storing layer, hereinafter, charge storing layer 124, [0234], Fig. 24C) provided on a side face of the second insulator 34 in the stacked film 136/146 (charge storing layer 124 is provided on a side face of the second insulator 34 in the stacked film 136/146, [0234], Fig. 24C);
a third insulator (tunneling dielectric layer 26 is a third insulator, hereinafter, third insulator 26, [0213], Fig. 24C) provided on a side face of the storing layer 124 in the stacked film 136/146 (third insulator 26 is provided on a side face of the storing layer 124 in the stacked film 136/146, [0213], Fig. 24C); and
a semiconductor layer (first semiconductor channel layer 601 is a semiconductor layer, hereinafter, semiconductor layer 601, [0088], Fig. 24C) provided on a side face of the third insulator 26 in the stacked film 136/146 (semiconductor layer 601 is provided on a side face of the third insulator 26 in the stacked film 136/146, [0088], Fig. 24C),
wherein at least one of the plurality of electrode layers 146 includes:
a first layer (metallic barrier liner 146A is a first layer, hereinafter, first layer 146A, [0194], Fig. 24C) provided on a side face of the second insulator 34 (first layer 146A is provided on a side face of the second insulator 34, [0194], Fig. 24C) and including a metal element (first layer 146A includes a metal element, [0194], Fig. 24C);
a first insulator (silicon oxide blocking dielectric portions 122 is a first insulator, hereinafter, first insulator 122, [0229], Fig. 24C) that is in contact with the first layer 146A (first insulator 122 is in contact with the first layer 146A, [0242], Fig. 24C) and includes silicon and oxygen (first insulator 122 includes silicon and oxygen (i.e. silicon oxide), [0229], Fig. 24C); and
a second layer (metallic fill material layer 146B is a second layer, hereinafter, second layer 146B, [0195], Fig. 24C) that is in contact with the first insulator 122 (second layer 146B is in contact with the first insulator 122, [0195], Fig. 24C) and includes a second metal element (second layer 146B includes a second metal element, [0195], Fig. 24C).
Claim 11, Rajashekhar discloses a semiconductor device (semiconductor device, Fig. 24C) of Claim 10.
Rajashekhar discloses wherein the second metal element is different from the first metal element (second metal element (i.e. molybdenum) is different from the first metal element (i.e. tungsten), [0195], Fig. 24C).
Claim 12, Rajashekhar discloses a semiconductor device (semiconductor device, Fig. 24C) of Claim 10.
Rajashekhar discloses wherein the second metal element is molybdenum or tungsten (second metal element (i.e. molybdenum), [0195], Fig. 24C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar in view of Wakatsuki (US 2020/0091080 A1).
Claim 8, Rajashekhar discloses the device (semiconductor device, Fig. 24C) of Claim 1.
Rajashekhar does not explicitly disclose wherein a concentration of oxygen atoms in the first insulator is 5.0 x 1021 to 5.0 x 1023 atoms/cm3.
However, Wakatsuki discloses wherein a concentration of oxygen atoms in the first insulator (i.e. second metal layer 8 is an Al2O3 film which is an insulator) is 5.0 x 1021 to 5.0 x 1023 atoms/cm3 (second metal layer 8 is an insulator and may be in direct contact with the electrode material layer 6 wherein the diffusion of oxygen atoms into the adjacent memory stack within the memory hole H is prevented, [0046], Fig. 4B). The combination to utilize an insulator layer adjacent to the oxygen doped electrode layer ensures sufficient diffusion blocking from the adjacent memory stack within the memory hole (Wakatsuki, [0046]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an insulator layer adjacent to the oxygen doped electrode layer ensures sufficient diffusion blocking from the adjacent memory stack within the memory hole (Wakatsuki, [0046]).
Claims 13-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar in view of Kanakamedala (US 2021/0265372 A1) in view of Chen (US 2020/0027738 A1).
Claim 13, Rajashekhar (US 2021/0265385 A1) discloses a method of manufacturing a semiconductor device (method of manufacturing a semiconductor device, [0043], Figs. 24A-24C) comprising:
forming a stacked film (alternating stack of insulating layers 136, dielectric barrier liners 34, and electrically conductive layer 146 is a stacked film, hereinafter, stacked film 136/146, [0236], Fig. 24C) including a plurality of fourth layers (stacked film 136/146 includes second sacrificial material layers 141 which is a plurality of fourth layers, hereinafter, plurality of fourth layers 141, [0236], Fig. 24C) and a plurality of insulators (stacked film 136/141 includes insulating layers 136 which are a plurality of insulators, hereinafter, plurality of insulators 136, [0236], Fig. 24C) that are alternately provided in a first direction (plurality of fourth layers 141 and plurality of insulators 136 are alternately provided in a first direction (i.e. vertical direction), [0236], Fig. 24C); and
forming a second insulator (dielectric barrier liners 34 is a second insulator, hereinafter, second insulator 34, [0230], Fig. 24C) provided on a side face of the stacked film 136/141 in the stacked film 136/141 (second insulator 34 is provided on a side face of the stacked film 136/141 within the stacked film 136/141, [0230], Fig. 24C);
forming a charge storing layer (charge storage material portion 124 is a charge storing layer, hereinafter, charge storing layer 124, [0234], Fig. 24C) provided on a side face of the second insulator 34 in the stacked film 136/141 (charge storing layer 124 is provided on a side face of the second insulator 34 in the stacked film 136/141, [0234], Fig. 24C);
forming a third insulator (tunneling dielectric layer 26 is a third insulator, hereinafter, third insulator 26, [0213], Fig. 24C) provided on a side face of the storing layer 124 in the stacked film 136/141 (third insulator 26 is provided on a side face of the storing layer 124 in the stacked film 136/141, [0213], Fig. 24C); and
forming a semiconductor layer (first semiconductor channel layer 601 is a semiconductor layer, hereinafter, semiconductor layer 601, [0088], Fig. 24C) provided on a side face of the third insulator 26 in the stacked film 136/141 (semiconductor layer 601 is provided on a side face of the third insulator 26 in the stacked film 136/141, [0088], Fig. 24C),
removing the plurality of fourth layers 141 from the stacked film 136/141 after the semiconductor layer 601 is formed (plurality of fourth layers 141 is removed from the stacked film 136/141 after the semiconductor layer 601 is formed, [0147], Figs. 24A-24C); and
forming a plurality of electrode layers (stacked film 136/146 includes electrically conductive layer 146 which is a plurality of electrode layers, hereinafter, plurality of electrode layers 146, [0236], Fig. 24C) in a plurality of recesses formed in the stacked film by the removal of the plurality of fourth layers (plurality of electrode layers 146 are formed in a plurality of recesses formed in the stacked film 136/141 by the removal of the plurality of fourth layers 141, [0236], Fig. 24C),
wherein at least one of the plurality of electrode layers 146 is formed by:
forming a first layer (metallic barrier liner 146A is a first layer, hereinafter, first layer 146A, [0194], Fig. 24C) provided on a side face of the second insulator 34 (first layer 146A is provided on a side face of the second insulator 34, [0194], Fig. 24C) and including a metal element (first layer 146A includes a metal element, [0194], Fig. 24C);
Rajashekhar does not explicitly disclose forming a first film that is in contact with the first layer and includes silicon; changing the first film into a first insulator that is in contact with the first layer and includes silicon and oxygen, and a second film that is in contact with the first insulator and includes molybdenum or tungsten; and forming a third film that is in contact with the second film and includes molybdenum or tungsten, thereby forming a second layer including the second film and the third film.
However, Chen/Kanakamedala discloses forming a first film (Chen, nucleation layer 830 is a first film, hereinafter, first film 830, [0099], Fig. 9B; Kanakamedala, forming a continuous silicon oxide blocking dielectric layer 52, hereinafter, first insulator 52, [0058], Fig. 6I) that is in contact with the first layer (Chen, substrate 820 is a first layer, hereinafter, first layer 820 and in contact with the first film 830, [0093], Fig. 9B; Kanakamedala, first insulator 52 is in contact with first layer 51, [0058], Fig. 6I) and includes silicon (Chen, first film 830 includes silicon, [0098], Fig. 9B; Kanakamedala, first insulator 52 includes silicon (i.e. silicon oxide), [0058], Fig. 6I);
changing the first film into a first insulator that is in contact with the first layer and includes silicon and oxygen (Chen, first film 830 is changed into an underlying first film which is a first insulator that is in contact with the first layer 820 and includes silicon and oxygen, [0092], Fig. 9B; Kanakamedala, first insulator 52 is in contact with first layer 51 and includes silicon and oxygen (i.e. silicon oxide), [0058], Fig. 6I), and a second film (Chen, first film 830 is also changed into a top lying second film which is in contact with the first layer 820, hereinafter, second film 840, [0105], Fig. 9B; Kanakamedala, vertical stack of charge storage material portions 54, hereinafter, second layer 54 is a second film, [0060], Figs. 5G, 6C and 6I) that is in contact with the first insulator (Chen, second film 840 is in contact with the first insulator 830; Kanakamedala, second layer 54 is in contact with first insulator 52, [0084], Figs. 6C and 6I) and includes molybdenum or tungsten (Chen, second film 840 includes molybdenum or tungsten, [0103], Fig. 9B; Kanakamedala, second film 54 (i.e. charge storage material layer) includes molybdenum or tungsten and is in contact with first insulator 52, [0060], Figs. 5G, 6C, and 6I); and
forming a third film (Chen, forming a second metal layer 850 is a third film, hereinafter, third film 850, [0105], Fig. 9B; Kanakamedala, tunneling dielectric layer 56 is a third film, [0063], Figs. 6I and 10A ) that is in contact with the second film (Chen, third film 850 is in contact with the second film 840, [0105], Fig. 9B; Kanakamedala, third film 56 is in contact with the second film 54, [0060], Figs. 5G, 6C and 6I) and includes molybdenum or tungsten (Chen, third film 850 includes molybdenum or tungsten, [0103], Fig. 9B; Kanakamedala, second film 54 (i.e. charge storage material layer) includes molybdenum or tungsten, [0060], Figs. 5G, 6C, and 6I), thereby forming a second layer including the second film and the third film (Chen, second layer includes second film 840 and third film 850, hereinafter, second layer 840/850, [0105], Fig. 9B; Kanakamedala, second layer 54/56 includes second film 54 and third film 56, [0067], Figs. 6I and 10A). The combination to utilize an amorphous silicon first film, change the first film into a first insulating film, and then deposit consecutive molybdenum or tungsten films as the second and third films, respectively, would allow for reduced film peeling as well as reduced decrease in film resistivity of the molybdenum or tungsten layers (Chen, [0116]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an amorphous silicon first film, change the first film into a first insulating film, and then deposit consecutive molybdenum or tungsten films as the second and third films, respectively, would allow for reduced film peeling as well as reduced decrease in film resistivity of the molybdenum or tungsten layers (Chen, [0116]).
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Fig. 6I (Kanakamedala) – Illustrates a three-dimensional memory device including a first layer 51 including a metal element (i.e. aluminum), a first insulator 52 that is in contact with the first layer 51 and includes silicon and oxygen (i.e. silicon oxide), and a second layer 54 that is in contact with the first insulator 52 and includes molybdenum or tungsten.
Claim 14, Rajashekhar/Kanakamedala/Chen discloses the method (Chen, processing method 700 for filming film stacks 800, [0091], Figs. 9A and 9B; Kanakamedala, semiconductor device, Fig. 9D) of Claim 13.
Rajashekhar/Kanakamedala/Chen discloses wherein the first film is an amorphous film (Chen, first film 830 is an amorphous film (i.e. amorphous silicon), [0097] – [0098], Fig. 9B; Kanakamedala, first insulator 52, [0058], Fig. 6I).
Claim 15, Rajashekhar/Kanakamedala/Chen discloses the method (Chen, processing method 700 for filming film stacks 800, [0091], Figs. 9A and 9B; Kanakamedala, semiconductor device, Fig. 9D) of Claim 13.
Rajashekhar/Kanakamedala/Chen discloses wherein a thickness of the first film is 7 nm or less (Chen, thickness of first film 830 is 7 nm or less (i.e. 1 Å to 200 Å, equivalent to 0.1 nm to 20 nm), [0099], Fig. 9B; Kanakamedala, thickness of the first insulator 52 is 7 nm or less (i.e. 1 nm to 10 nm), [0058], Fig. 6I)
Claim 16, Rajashekhar/Kanakamedala/Chen discloses the method (Chen, processing method 700 for filming film stacks 800, [0091], Figs. 9A and 9B; Kanakamedala, semiconductor device, Fig. 9D) of Claim 13.
Rajashekhar/Kanakamedala/Chen discloses wherein a first gas including molybdenum or tungsten is used to change the first film into the first insulator and the second film (Chen, first metal precursor is a first gas including molybdenum (i.e. Mo(CO)6) or tungsten (i.e. W(CO)5) used to change the first film 830 into the first insulator 822 and the second film 840, [0103], Fig. 9B; Kanakamedala, oxygen and molybdenum containing precursor used to deposit molybdenum-containing material, [0037], Figs. 6I and 10A).
Claim 17, Rajashekhar/Kanakamedala/Chen discloses the method (Chen, processing method 700 for filming film stacks 800, [0091], Figs. 9A and 9B; Kanakamedala, semiconductor device, Fig. 9D) of Claim 16.
Rajashekhar/Kanakamedala/Chen discloses wherein the first gas includes molybdenum or tungsten, and oxygen (Chen, first gas includes either oxygen and molybdenum (i.e. Mo(CO)6) or oxygen and tungsten (i.e. W(CO)5), [0103], Fig. 9B; Kanakamedala, oxygen and molybdenum containing precursor used to deposit molybdenum-containing material, [0037], Figs. 6I and 10A).
Claim 19, Rajashekhar/Kanakamedala/Chen discloses the method (Chen, processing method 700 for filming film stacks 800, [0091], Figs. 9A and 9B; Kanakamedala, semiconductor device, Fig. 9D) of Claim 13.
Rajashekhar/Kanakamedala/Chen discloses wherein the first film is changed into the first insulator and the second film that includes molybdenum at 600oC or less (Chen, first film 830 is changed into a first insulator 822 and second film 840 that includes molybdenum at 600oC or less (i.e. 25oC to 700oC) , [0112], Fig. 9B; Kanakamedala, second film 54 (i.e. charge storage material layer) includes molybdenum formed via chemical vapor deposition or atomic layer deposition (i.e. CVD or ALD), [0060], Figs. 5G, 6C, and 6I).
Claim 20, Rajashekhar/Kanakamedala/Chen discloses the method (Chen, processing method 700 for filming film stacks 800, [0091], Figs. 9A and 9B; Kanakamedala, semiconductor device, Fig. 9D) of Claim 13.
Rajashekhar/Kanakamedala/Chen discloses wherein the first film is changed into the first insulator and the second film that includes tungsten at 400 to 500oC (Chen, first film 830 is changed into a first insulator 822 and second film 840 that includes tungsten at 400 to 500oC (i.e. 25oC to 700oC) , [0112], Fig. 9B; Kanakamedala, second film 54 (i.e. charge storage material layer) includes tungsten formed via chemical vapor deposition or atomic layer deposition (i.e. CVD or ALD), [0060], Figs. 5G, 6C, and 6I).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar in view of Kanakamedala in view of Chen, further in view of Kitamura (US 2021/0083057 A1).
Claim 18, Rajashekhar/Kanakamedala/Chen discloses the method (Chen, processing method 700 for filming film stacks 800, [0091], Figs. 9A and 9B; Kanakamedala, semiconductor device, Fig. 9D) of Claim 17.
Rajashekhar/Kanakamedala/Chen does not explicitly disclose wherein the first gas includes an MoO2Cl2 gas, an MoOCl4 gas, a WO2Cl2 gas or a WOCl4 gas where Mo denotes molybdenum, W denotes tungsten, O denotes oxygen, and Cl denotes chlorine.
However, Kitamura discloses wherein the first gas includes an MoO2Cl2 gas, an MoOCl4 gas, a WO2Cl2 gas or a WOCl4 gas where Mo denotes molybdenum, W denotes tungsten, O denotes oxygen, and Cl denotes chlorine (Kitamura, material gas 201 is a first gas, hereinafter, first gas 201 and includes a WO2Cl2 gas where Mo denotes molybdenum, W denotes tungsten, O denotes oxygen, and Cl denotes chlorine, [0019], Fig. 2; Chen, first gas includes either oxygen and molybdenum (i.e. Mo(CO)6) or oxygen and tungsten (i.e. W(CO)5), [0103], Fig. 9B; Kanakamedala, oxygen and molybdenum containing precursor used to deposit molybdenum-containing material, [0037], Figs. 6I and 10A). The combination to utilize a first gas including a halogen, oxide, and metal allows for enhanced adhesion between underlying layers due to the binding energy of the deposition surface (Kitamura, [0021] – [0023]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a first gas including a halogen, oxide, and metal allows for enhanced adhesion between underlying layers due to the binding energy of the deposition surface (Kitamura, [0021] – [0023])
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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