Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Applicant Election filled on 01/13/2026. Currently, claims 1-16 are pending in the application. Claims 9-10 have been withdrawn from consideration. Claims 12-16 have been added new.
Election/Restrictions
Applicant's election without traverse of Group, claims 1-8 and 11-16, in the reply filed on 01/13/2026 is acknowledged, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 11-13 and 15-16 are rejected under 35 U.S.C. 103 as being obvious over Kalnitsky et al (US 20150325678 A1).
Regarding claim 1, Figures 1-2 of Kalnitsky disclose a field effect transistor, comprising:
a channel layer (116+114, [0014]);
a source (120, left one, [0018]), a drain (120, right one), and a gate structure (122, [0019]) that are disposed in a manner of stacking with the channel layer, wherein the source, the drain, and the gate structure are disposed at a common layer (116);
the gate structure (122) comprising an N-type gallium nitride layer (132, Figure 2a, [0024]) disposed on a P-type gallium nitride layer (130, [0024]), wherein the P-type gallium nitride layer (130) is located between the N-type gallium nitride layer (132) and the channel layer; and
a gate metal layer (124, [0039]) in ohmic contact ([0050]) with the N-type gallium nitride layer (132).
Kalnitsky does not explicitly teach that a doping density of the P-type gallium nitride layer is between 1×10.sup.18 cm.sup.−3 and 1×10.sup.19 cm.sup.−3.
However, Kalnitsky teaches that the threshold voltage of the corresponding E-mode transistors can be adjustable by varying the doping and/or the thickness of the n-p diodes ([0036]) in order to have a structure for a GaN enhancement mode transistor with reduced gate leakage ([0002] and [0021]).
Thus, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges in order to have a GaN enhancement mode transistor with reduced gate leakage and improve switching speed ([0002] and [0021]) with lower cost, and further, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 2, Kalnitsky does not explicitly teach that the field effect transistor according to claim 1, wherein a thickness of the P-type gallium nitride layer is greater than or equal to 50 nm and less than or equal to 70 nm.
However, Kalnitsky teaches that the P-type gallium nitride layer (130) is 1 nm to 100 nm ([0024]). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 3, Kalnitsky does not explicitly teach that the field effect transistor according to claim 1, wherein a doping density of the N-type gallium nitride layer is between 1×10.sup.16 cm.sup.−3 and 5×10.sup.19 cm.sup.−3.
However, Kalnitsky teaches that the threshold voltage of the corresponding E-mode transistors can be adjustable by varying the doping and/or the thickness of the n-p diodes ([0036]) in order to have a structure for a GaN enhancement mode transistor with reduced gate leakage and improve switching speed ([0002] and [0021]).
Thus, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges in order to have a GaN enhancement mode transistor with reduced gate leakage and improve switching speed ([0002] and [0021]) with lower cost, and further, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 4, Kalnitsky does not explicitly teach that the field effect transistor according to claim 3, wherein a thickness of the N-type gallium nitride layer is less than or equal to 40 nm.
However, Kalnitsky teaches that the N-type gallium nitride layer (132) is 1 nm to 100 nm ([0030]). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 5, Figures 1-2 of Kalnitsky disclose that the field effect transistor according to claim 1, wherein the channel layer (116+114, [0014]) comprises a gallium nitride layer (114) and an aluminum gallium nitride barrier layer (116, [0014]) that are stacked; and the source (120, left one), the drain (120, right one), and the gate structure (122) are disposed at the aluminum gallium nitride barrier layer (116).
Regarding claim 6, Figures 1-2 of Kalnitsky disclose that the field effect transistor according to claim 5, further comprising a substrate (110, [0014]) and a buffer layer (transition layer, not shown, [0014]) disposed on the substrate, wherein the P-type gallium nitride layer (130, [0024]) is formed on the buffer layer.
Regarding claim 7, Figures 1-2 of Kalnitsky disclose that the field effect transistor according to claim 6, wherein a material of the substrate (110) is silicon, sapphire, silicon carbide, or a gallium nitride body material ([0013]).
Regarding claim 8, Kalnitsky does not explicitly teach that the field effect transistor according to claim 5, further comprising a passivation layer disposed on the aluminum gallium nitride barrier layer; and wherein the source, the drain, and the gate structure pass through the passivation layer and are exposed from the passivation layer.
However, the Examiner takes an official notice that such passivation layer is very well known in pertinent prior arts in formed over the device for environmental protection.
Regarding claim 11, Kalnitsky does not explicitly teach a switch circuit, comprising a mainboard and the field effect transistor according to claim 1, wherein the field effect transistor is disposed on the mainboard.
However, the Examiner takes an official notice that such field effect transistor according to claim 1 is very well known in pertinent prior arts used in main board for switch circuit. Further, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ 2d 1647 (1987).
Regarding claim 12, Figures 1-2 of Kalnitsky disclose that the field effect transistor of claim 1 wherein the channel layer is configured to form two-dimensional electron gas (118) of the field effect transistor ([0017]).
Regarding claim 13, Figures 1-2 of Kalnitsky disclose that the field effect transistor of claim 12 wherein the channel layer includes a gallium nitride (GaN) layer (114), a channel (118, [0017]) is formed on a contact surface between the GaN layer and an AlGaN barrier layer, and the two-dimensional electron gas (118) is located on the contact surface between the GaN layer and the AlGaN barrier layer (116).
Regarding claim 15, Figures 1-2 of Kalnitsky disclose that the field effect transistor of claim 1 wherein the source (120, left one), the gate structure (122), and the drain (120, right one) are disposed on the channel layer (116+114) and are electrically connected to the channel layer.
Regarding claim 16, Figures 1-2 of Kalnitsky disclose that the field effect transistor of claim 1 wherein the N-type gallium nitride layer disposed on the P-type gallium nitride layer forms a reverse biased diode (please see Figure 2b, [0025]).
Claim 14 is rejected under 35 U.S.C. 103 as being obvious over Kalnitsky et al (US 20150325678 A1) in view of CHEN et al (US 20180166565 A1).
Regarding claim 14, Figures 1-2 of Kalnitsky do not explicitly teach that the field effect transistor of claim 1 wherein the channel layer includes a three-layer structure comprising a gallium nitride layer, an aluminum gallium nitride barrier layer, and an aluminum nitride layer located between the gallium nitride layer and the aluminum gallium nitride barrier layer.
However, CHEN is a pertinent art which teaches a HEMT device, wherein CHEN teaches the channel layer an active layer 130 (Figure 1) includes one or more Group III-V compound layers which are different from the Group III-V compound layers of the channel layer 120 in composition. In some embodiments, the active layer 130 comprises aluminum nitride (AlN), graded aluminum gallium nitride (Al.sub.yGa.sub.(1-y)N) (where y is the aluminum content ratio, and y is in a range from 0 to 1), or a combination thereof ([0031]) for improving current performance of the structure ([0024] and [0069]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the field effect transistor of Kalnitsky by having the channel layer with a three-layer structure comprising a gallium nitride layer, an aluminum gallium nitride barrier layer, and an aluminum nitride layer located between the gallium nitride layer and the aluminum gallium nitride barrier layer according to the teaching of CHEN in order to form a field effect transistor with improved current performance ([0024] and [0069] of CHEN).
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/Primary Examiner, Art Unit 2813