DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 18-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Thomas et al (US 2023/0037957 A1).
Regarding claim 18, Thomas et al discloses a device (Figure 1a) comprising: upper nanostructures (Figure 1a, upper devices) over lower nanostructures (Figure 1a, lower devices), the upper nanostructures (Figure 1a, upper devices) having a different crystalline orientation (paragraphs 0020-0021; SiGe and silicon) than the lower nanostructures (Figure 1a, lower devices); an isolation material (Figure 1a, reference 121) between the upper nanostructures (Figure 1a, upper devices) and the lower nanostructures (Figure 1a, lower devices); a lower gate structure (Figure 1a, references 116-118) around the lower nanostructures (Figure 1a, lower devices); an upper gate structure (Figure 1a, references 122-124) around the upper nanostructures (Figure 1a, upper devices); lower source/drain regions (Figure 1a, references 109 and 110), the lower nanostructures (Figure 1a, center lower device) extending between the lower source/drain regions (Figure 1a, references 109 and 110); an first insulating layer (Figure 1a, reference 111) over the lower source/drain regions (Figure 1a, references 109 and 110); and upper source/drain regions (Figure 1a, references 113 and 114)over the first insulating layer (Figure 1a, reference 111), the upper nanostructures (Figure 1a, center upper device) extending between the upper source/drain regions (Figure 1a, references 113 and 114).
Regarding claim 19, Thomas et al discloses wherein the lower nanostructures (Figure 1a, lower devices), the lower source/drain regions (Figure 1a, references 109 and 110), and the lower gate structure (Figure 1a, references 116-118) provide a p-type transistor (paragraphs 0019-0020), wherein the upper nanostructures (Figure 1a, upper devices), the upper source/drain regions (Figure 1a, references 113 and 114), and the upper gate structure (Figure 1a, references 122-124) provide an n-type transistor (paragraphs 0019-0020), wherein the lower nanostructures (Figure 1a, lower devices) have an (110) plane crystalline orientation (paragraph 0021), and wherein the upper nanostructures (Figure 1a, upper devices) have a (100) plane crystalline orientation (paragraph 0021; cmos device, material is interchangeable ie. Si and SiGe).
Regarding claim 20, Thomas et al discloses wherein the lower nanostructures (Figure 1a, lower devices), the lower source/drain regions (Figure 1a, references 109 and 110), and the lower gate structure (Figure 1a, references 116-118) provide an n-type transistor (paragraphs 0019-0020), wherein the upper nanostructures (Figure 1a, upper devices), the upper source/drain regions (Figure 1a, references 113 and 114), and the upper gate structure (Figure 1a, references 122-124) provide a p-type transistor (paragraphs 0019-0020), wherein the lower nanostructures (Figure 1a, lower devices) have an (100) plane crystalline orientation (paragraph 0021), and wherein the upper nanostructures (Figure 1a, upper devices) have a (110) plane crystalline orientation (paragraph 0021; cmos device, material is interchangeable ie. Si and SiGe).
Allowable Subject Matter
Claims 1-17 are allowed over the prior art of record.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance: The prior art does not disclose nor fairly suggest methods comprising: the fin comprising a plurality of lower nanostructures alternatingly stacked with first dummy nanostructures and a plurality of upper nanostructures over the plurality of lower nanostructures, the plurality of upper nanostructures being alternatingly stacked with second dummy nanostructures; replacing the first dummy nanostructures with a first gate stack, the first gate stack surrounding each of the plurality of lower nanostructures; and replacing the second dummy nanostructures with a second gate stack, the second gate stack surrounding each of the plurality of upper nanostructures (claim 1) and depositing a first bonding layer over the second semiconductor layer; depositing a second bonding layer over the fourth semiconductor layer; directly bonding the first bonding layer to the second bonding layer to form a bonded layer; patterning the second semiconductor substrate, the third semiconductor layer, the fourth semiconductor layer, the bonded layer, the second semiconductor layer, and the first semiconductor layer to define a fin extending upwards from the first semiconductor substrate; patterning source/drain recesses in the fin; forming first source/drains in the source/drain recesses; depositing a first isolation layer over the first source/drain; and forming second source/drains in the source/drain recesses over the first isolation layer (claim 10) as described in the independent claims and in the context of their recited processes, along with their depending claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm.
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/MONICA D HARRISON/ Primary Examiner, Art Unit 2815
mdh
January 15, 2026