DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 07/06/2026 has been entered. Claim 13 is canceled by the Applicant.
Claims 1-12 and 14-20 are pending.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 07/06/2026, have been fully considered, the arguments are not persuasive and some of them are moot because do not apply to new ground of rejections with a new reference, US 20190341448 A1 to Bourjot, being used in the current rejection, see detail below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections
set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-5,9-12, 14,16-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Fan et al. (20230018266, hereinafter Fan), in view of Bourjot et al. (US 20190341448 A1, hereinafter Bourjot).
Re: Independent Claim 1, Fan discloses a semiconductor device (Fig.12), comprising:
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Fan’s Figure 12-Annotated.
a substrate (202, [0016], Fig.12);
a lower pattern (upper-202, [0016], Fig.12-Annotated) on the substrate (202);
a channel pattern (208, channel layers 208a, b, c, [0016], Fig.12) on the lower pattern (upper-
202);
a source/drain pattern (228, source/drain feature, [0026], Fig.12) on both sides (Fig.12-
Annotated) of the channel pattern (208);
a gate structure (242, gate structures, [0018], Fig.12) surrounding (Fig.12) the channel pattern
(208);
a contact electrode (246, source/drain contact, [0037], Fig.12) electrically connected to the
source/drain pattern (228);
an etch stop layer (234, etch stop layer, [0030], Fig.12) between the gate structure (242) and the contact electrode (246); and
a contact interface layer (244, silicide layer, [0037], Fig.12) on the source/drain pattern (228),
wherein the contact interface layer (244) includes a first region (first region, a lower region of 244, Fig.12-Annotated) and a second region (second region, an upper and lateral regions of 244, Fig.12-Annotated), the first region (first region) is between the source/drain pattern (228) and the contact electrode (246), and the second region (second region) is between the source/drain pattern (228) and the etch stop layer (234).
Fan does not expressly disclose an interlayer insulation layer on side surfaces of the source/drain pattern and the second region is further between the interlayer insulation layer and the side surfaces of the source/drain pattern.
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Bourjot’s Figure 31B-Annotated.
However, in the same semiconductor device field of endeavor, Bourjot discloses an interlayer insulation layer (3100 dielectric fill in [0052], Fig. 31B) on side surfaces of the source/drain pattern (370 S/D epitaxy structure in [0050], Fig. 31B) and the second region (3200-lateral-top, lateral and top portions of the conformal contact layer 3200 made of silicide material in [0054], Fig. 31B-Annotated) is further between the interlayer insulation layer (3100) and the side surfaces of the source/drain pattern (370).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Bourjot’s silicide layer wherein an interlayer insulation layer on side surfaces of the source/drain pattern and the second region is further between the interlayer insulation layer and the side surfaces of the source/drain pattern to Fan’s device for increasing contact area and ultimately allowing for improved S/D contact resistance (abstract, Bourjot).
Re: Claim 2, Fan modified by Bourjot discloses the semiconductor device of claim 1, wherein the second region (Bourjot’s top- lateral sides of 3200 Fig.31B-Annotated) of the contact interface layer (3200) extends along (Fig.31B-Annotated, Bourjot) an upper surface of the source/drain pattern (Bourjot’s 370 Fig.31B-Annotated).
Re: Claim 3, Fan modified by Bourjot discloses the semiconductor device of claim 1,
Fan modified by Bourjot does not expressly disclose wherein the second region overlaps the etch stop layer in a thickness direction of the substrate.
However, in the same semiconductor device field of endeavor, Bourjot discloses wherein the second region (Bourjot’s top- lateral sides of 3200 Fig.31B-Annotated) overlaps the etch stop layer (3000 a conformal liner layer in [0052], Fig. 31B) in a thickness direction of the substrate (300 in [0043], Fig. 31B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Bourjot’s silicide layer wherein the second region overlaps the etch stop layer in a thickness direction of the substrate to Fan’s device for increasing contact area and ultimately allowing for improved S/D contact resistance (abstract, Bourjot).
Re: Claim 4, Fan modified by Bourjot discloses the semiconductor device of claim 3,
Fan modified by Bourjot does not expressly disclose wherein the interlayer insulation layer is further between the contact electrode and the etch stop layer, and wherein the second region of the contact interface layer overlaps the interlayer insulation layer in the thickness direction of the substrate.
However, in the same semiconductor device field of endeavor, Bourjot discloses wherein the interlayer insulation layer (3100 dielectric fill in [0052], Fig. 31B) is further between the contact electrode (3300 conductive contact in [0055], Fig. 31B) and the etch stop layer (3000 a conformal liner layer in [0052], Fig. 30B), and wherein the second region (Bourjot’s second region- lateral and top sides of 3200 Fig.31B-Annotated) of the contact interface layer (3200) overlaps the interlayer insulation layer (3100) in the thickness direction of the substrate (300).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Bourjot’s silicide layer wherein the interlayer insulation layer is further between the contact electrode and the etch stop layer, and wherein the second region of the contact interface layer overlaps the interlayer insulation layer in the thickness direction of the substrate to Fan’s device for increasing contact area and ultimately allowing for improved S/D contact resistance (abstract, Bourjot).
Re: Claim 5, Fan modified by Bourjot discloses the semiconductor device of claim 1,
but not disclose wherein a thickness of the second region of the contact interface layer is greater than a thickness of the first region of the contact interface layer.
Fan modified by Bourjot does not expressly disclose wherein a thickness of the second region of the contact interface layer is greater than a thickness of the first region of the contact interface layer.
However, in the same semiconductor device field of endeavor, Bourjot discloses wherein a thickness (T2, Fig.31B-Annotated) of the second region (Bourjot’s second region- lateral and top sides of 3200 Fig.31B-Annotated) of the contact interface layer (3200) is greater than a thickness (T1, Fig.31B-Annotated) of the first region (Bourjot’s first region- a top portion at the middle of 3200 Fig.31B-Annotated) of the contact interface layer (3200).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Bourjot’s silicide layer wherein a thickness of the second region of the contact interface layer is greater than a thickness of the first region of the contact interface layer to Fan’s device for increasing contact area and ultimately allowing for improved S/D contact resistance (abstract, Bourjot).
Re: Claim 9, Fan modified by Bourjot discloses the semiconductor device of claim 1, wherein an upper surface (upper-surface 228 Fig.12-Annotated, Fan) of the source/drain pattern (228, Fan) is farther from an upper surface of the substrate (202, Fan) than an upper surface (upper-surface 208 Fig.12-Annotated, Fan) of the channel pattern (208, Fan).
Re: Independent Claim 10, Fan discloses a semiconductor device, comprising:
a substrate (202, [0016], Fig.12);
a lower pattern (upper-202, [0016], Fig.12-Annotated) on the substrate (202);
a channel pattern (208, channel layers 208a, b, c, [0016], Fig.12) on the lower pattern (upper-
202);
a source/drain pattern (228, source/drain feature, [0026], Fig.12) on both sides (Fig.12-
Annotated) of the channel pattern (208);
a gate structure (242, gate structures, [0018], Fig.12) surrounding (Fig.12) the channel pattern
(208);
a contact electrode (246, source/drain contact, [0037], Fig.12) electrically connected to the
source/drain pattern (228);
a contact interface layer (244, silicide layer, [0037], Fig.12) between the source/drain pattern (228) and the contact electrode (246); and
wherein the contact interface layer (244) includes a first region (first region, a lower region of 244, Fig.12-Annotated) and a second region (second region, an upper and lateral regions of 244, Fig.12-Annotated), the first region (first region) surrounds at least a portion of the contact electrode (246), and the second region (second region) extends from the first region (first region) along (Fig.12-Annotated) an upper surface of the source/drain pattern (228).
Fan does not expressly disclose an interlayer insulation layer on side surfaces of the source/drain pattern, and the second region is between the interlayer insulation layer and the side surfaces of the source/drain pattern.
However, in the same semiconductor device field of endeavor, Bourjot discloses an interlayer insulation layer (3100 dielectric fill in [0052], Fig. 31B) on side surfaces of the source/drain pattern (370 S/D epitaxy structure in [0050], Fig. 31B) and the second region (3200-lateral-top, lateral and top portions of the conformal contact layer 3200 made of silicide material in [0054], Fig. 31B-Annotated) is between the interlayer insulation layer (3100) and the side surfaces of the source/drain pattern (370).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Bourjot’s silicide layer wherein an interlayer insulation layer on side surfaces of the source/drain pattern and the second region is between the interlayer insulation layer and the side surfaces of the source/drain pattern to Fan’s device for increasing contact area and ultimately allowing for improved S/D contact resistance (abstract, Bourjot).
Re: Claim 11, Fan modified by Bourjot discloses the semiconductor device of claim 10,
Fan modified by Bourjot does not expressly disclose further comprising: an etch stop layer on the side surfaces of the source/drain pattern, wherein the second region of the contact interface layer is between the etch stop layer and the source/drain pattern.
However, in the same semiconductor device field of endeavor, Bourjot discloses further comprising: an etch stop layer (3000 a conformal liner layer in [0052], Fig. 31B) on the side surfaces of the source/drain pattern (370 S/D epitaxy structure in [0050], Fig. 31B), wherein the second region (Bourjot’s top- lateral sides of 3200 Fig.31B-Annotated) of the contact interface layer (3200) is between the etch stop layer (3000) and the source/drain pattern (370).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Bourjot’s silicide layer further comprising: an etch stop layer on the side surfaces of the source/drain pattern, wherein the second region of the contact interface layer is between the etch stop layer and the source/drain pattern to Fan’s device for increasing contact area and ultimately allowing for improved S/D contact resistance (abstract, Bourjot).
Re: Claim 12, Fan modified by Bourjot discloses the semiconductor device of claim 11, wherein the second region (Bourjot’s top- lateral sides of 3200 Fig.31B-Annotated) of the contact interface layer (3200, Bourjot) overlaps the etch stop layer (3000, Bourjot) in a thickness direction of the substrate (300, Bourjot).
Re: Claim 14, Fan modified by Bourjot discloses the semiconductor device of claim 11, wherein the second region (Bourjot’s top- lateral sides of 3200 Fig.31B-Annotated) of the contact interface layer (3200, Bourjot) overlaps the interlayer insulation layer (3100, Bourjot) in a thickness direction of the substrate (300, Bourjot).
Re: Claim 16, Fan modified by Bourjot discloses the semiconductor device of claim 10,
Fan modified by Bourjot does not expressly disclose wherein the second region of the contact interface layer has a convex shape toward a direction away from the substrate.
However, the Applicant does not show persuasive evidence that the particular configuration of a shape of the second region of the contact interface layer having a convex shape toward a direction away from the substrate is critical for the invention.
It would have been obvious to one of ordinary skill in the art, at the time of the invention to choose the shape of the second region of the contact interface layer has a convex shape toward a direction away from the substrate as it best fits its particular device (MPEP 2144.04(IV)(B)).
Re: Independent Claim 17, Fan discloses a semiconductor device, comprising:
a substrate (202, [0016], Fig.12);
a lower pattern (upper-202, [0016], Fig.12-Annotated) on the substrate (202);
a channel pattern (208, channel layers 208a, b, c, [0016], Fig.12) on the lower pattern (upper-
202);
a source/drain pattern (228, source/drain feature, [0026], Fig.12) on both sides (Fig.12-
Annotated) of the channel pattern (208);
a gate structure (242, gate structures, [0018], Fig.12) surrounding (Fig.12) the channel pattern
(208);
a contact electrode (246, source/drain contact, [0037], Fig.12) electrically connected to the
source/drain pattern (228);
an interlayer insulation layer (236, an interlayer dielectric, [0030], Fig.12) between the gate structure (242) and the contact electrode (246); and
a contact interface layer (244, silicide layer, [0037], Fig.12) on the source/drain pattern (228),
wherein the contact interface layer (244) includes a first region (first region, a lower region of 244, Fig.12-Annotated) and a second region (second region, an upper and lateral regions of 244, Fig.12-Annotated), the first region (first region) is between the source/drain pattern (228) and the contact electrode (246), and the second region (second region) of the contact interface layer (244) overlaps the interlayer insulation layer (236) in a thickness direction of the substrate (202).
Fan does not expressly disclose the interlayer insulation layer on side surfaces of the source/drain pattern; the second region is between the side surfaces of the source/drain pattern and the interlayer insulation layer.
However, in the same semiconductor device field of endeavor, Bourjot discloses the interlayer insulation layer (3100 dielectric fill in [0052], Fig. 31B) on side surfaces of the source/drain pattern (370 S/D epitaxy structure in [0050], Fig. 31B); the second region (3200-lateral-top, lateral and top portions of the conformal contact layer 3200 made of silicide material in [0054], Fig. 31B-Annotated) is between the side surfaces of the source/drain pattern (370) and the interlayer insulation layer (3100).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Bourjot’s silicide layer wherein the interlayer insulation layer on side surfaces of the source/drain pattern; the second region is between the side surfaces of the source/drain pattern and the interlayer insulation layer to Fan’s device for increasing contact area and ultimately allowing for improved S/D contact resistance (abstract, Bourjot).
Re: Claim 19, Fan modified by Bourjot discloses the semiconductor device of claim 17, wherein an upper surface (upper-surface 228 Fig.12-Annotated, Fan) of the source/drain pattern (228, Fan) is farther from an upper surface of the substrate (202, Fan) than an upper surface (upper-surface 208 Fig.12-Annotated, Fan) of the channel pattern (208, Fan).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA MILENA RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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