DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species (a), (claims 1-5,9-14 and 16-19), in the reply filed on 02/09/2026 is acknowledged. Claim 18 include limitations “an external surface of the second region of the contact interface layer is in contact with the interlayer insulation layer” of non-elected Species (c), Fig.8, this claim is being joined with the withdrawn claims (6-8, 15 and 20).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-4,9-14,16-17 and 19 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Fan et al. (20230018266, hereinafter Fan).
Re: Independent Claim 1, Fan teaches a semiconductor device (Fig.12), comprising:
PNG
media_image1.png
496
599
media_image1.png
Greyscale
Fan’s Figure 12-Annotated.
a substrate (202, [0016], Fig.12);
a lower pattern (upper-202, [0016], Fig.12-Annotated) on the substrate (202);
a channel pattern (208, channel layers 208a, b, c, [0016], Fig.12) on the lower pattern (upper-
202);
a source/drain pattern (228, source/drain feature, [0026], Fig.12) on both sides (Fig.12-
Annotated) of the channel pattern (208);
a gate structure (242, gate structures, [0018], Fig.12) surrounding (Fig.12) the channel pattern
(208);
a contact electrode (246, source/drain contact, [0037], Fig.12) electrically connected to the
source/drain pattern (228);
an etch stop layer (234, etch stop layer, [0030], Fig.12) between the gate structure (242) and the contact electrode (246); and
a contact interface layer (244, silicide layer, [0037], Fig.12) on the source/drain pattern (228),
wherein the contact interface layer (244) includes a first region (first region, a lower region of 244, Fig.12-Annotated) and a second region (second region, an upper and lateral regions of 244, Fig.12-Annotated), the first region (first region) is between the source/drain pattern (228) and the contact electrode (246), and the second region (second region) is between the source/drain pattern (228) and the etch stop layer (234).
Re: Claim 2, Fan discloses the semiconductor device of claim 1, wherein the second region (second region Fig.12-Annotated) of the contact interface layer (244) extends along (Fig.12-Annotated) an upper surface of the source/drain pattern (228).
Re: Claim 3, Fan discloses the semiconductor device of claim 1, wherein the second region (second region Fig.12-Annotated) overlaps the etch stop layer (234) in a thickness direction of the substrate (202).
Re: Claim 4, Fan discloses the semiconductor device of claim 3, further comprising: an interlayer insulation layer (236, an interlayer dielectric, [0030], Fig.12) between the contact electrode (246) and the etch stop layer (234), wherein the second region (second region Fig.12-Annotated) of the contact interface layer (244) overlaps the interlayer insulation layer (236) in the thickness direction of the substrate (202).
Re: Claim 9, Fan discloses the semiconductor device of claim 1, wherein an upper surface (upper-surface 228 Fig.12-Annotated) of the source/drain pattern (228) is farther from an upper surface of the substrate (202) than an upper surface (upper-surface 208 Fig.12-Annotated) of the channel pattern (208).
Re: Independent Claim 10, Fan teaches a semiconductor device, comprising:
a substrate (202, [0016], Fig.12);
a lower pattern (upper-202, [0016], Fig.12-Annotated) on the substrate (202);
a channel pattern (208, channel layers 208a, b, c, [0016], Fig.12) on the lower pattern (upper-
202);
a source/drain pattern (228, source/drain feature, [0026], Fig.12) on both sides (Fig.12-
Annotated) of the channel pattern (208);
a gate structure (242, gate structures, [0018], Fig.12) surrounding (Fig.12) the channel pattern
(208);
a contact electrode (246, source/drain contact, [0037], Fig.12) electrically connected to the
source/drain pattern (228); and
a contact interface layer (244, silicide layer, [0037], Fig.12) between the source/drain pattern (228) and the contact electrode (246),
wherein the contact interface layer (244) includes a first region (first region, a lower region of 244, Fig.12-Annotated) and a second region (second region, an upper and lateral regions of 244, Fig.12-Annotated), the first region (first region) surrounds at least a portion of the contact electrode (246), and the second region (second region) extends from the first region (first region) along (Fig.12-Annotated) an upper surface of the source/drain pattern (228).
Re: Claim 11, Fan discloses the semiconductor device of claim 10, further comprising: an etch stop layer (234, etch stop layer, [0030], Fig.12) on both sides of the source/drain pattern (228), wherein the second region (second region) of the contact interface layer (244) is between the etch stop layer (234) and the source/drain pattern (228).
Re: Claim 12, Fan discloses the semiconductor device of claim 11, wherein the second region (second region Fig.12-Annotated) of the contact interface layer (244) overlaps the etch stop layer (234) in a thickness direction of the substrate (202).
Re: Claim 13, Fan discloses the semiconductor device of claim 11, further comprising: an interlayer insulation layer (236, an interlayer dielectric, [0030], Fig.12) on both sides of the etch stop layer (234), wherein the second region (second region Fig.12-Annotated) of the contact interface layer (244) is between the source/drain pattern (228) and the interlayer insulation layer (236).
Re: Claim 14, Fan discloses the semiconductor device of claim 13, wherein the second region (second region Fig.12-Annotated) of the contact interface layer (244) overlaps the interlayer insulation layer (236) in a thickness direction of the substrate (202).
Re: Claim 16, Fan discloses the semiconductor device of claim 10, wherein the second region (second region Fig.12-Annotated) of the contact interface layer (244) has a convex shape (Figure 12-enlarged-Annotated) toward a direction away from the substrate (202).
PNG
media_image2.png
656
396
media_image2.png
Greyscale
Fan’s Figure 12-enlarged-Annotated.
Re: Independent Claim 17, Fan teaches a semiconductor device, comprising:
a substrate (202, [0016], Fig.12);
a lower pattern (upper-202, [0016], Fig.12-Annotated) on the substrate (202);
a channel pattern (208, channel layers 208a, b, c, [0016], Fig.12) on the lower pattern (upper-
202);
a source/drain pattern (228, source/drain feature, [0026], Fig.12) on both sides (Fig.12-
Annotated) of the channel pattern (208);
a gate structure (242, gate structures, [0018], Fig.12) surrounding (Fig.12) the channel pattern
(208);
a contact electrode (246, source/drain contact, [0037], Fig.12) electrically connected to the
source/drain pattern (228);
an interlayer insulation layer (236, an interlayer dielectric, [0030], Fig.12) between the gate structure (242) and the contact electrode (246); and
a contact interface layer (244, silicide layer, [0037], Fig.12) on the source/drain pattern (228), wherein the contact interface layer (244) includes a first region (first region, a lower region of 244, Fig.12-Annotated) and a second region (second region, an upper and lateral regions of 244, Fig.12-Annotated), the first region (first region) is between the source/drain pattern (228) and the contact electrode (246), the second region (second region) is between the source/drain pattern (228) and the interlayer insulation layer (236), and the second region (second region) of the contact interface layer (244) overlaps the interlayer insulation layer (236) in a thickness direction of the substrate (202).
Re: Claim 19, Fan discloses the semiconductor device of claim 17, wherein an upper surface (upper-surface 228 Fig.12-Annotated) of the source/drain pattern (228) is farther from an upper surface of the substrate (202) than an upper surface (upper-surface 208 Fig.12-Annotated) of the channel pattern (208).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Fan.
Re: Claim 5, Fan discloses the semiconductor device of claim 1, but not disclose wherein a thickness of the second region of the contact interface layer is greater than a thickness of the first region of the contact interface layer.
However, the Applicant has not presented persuasive evidence that the claimed
“thickness of the second region of the contact interface layer greater than a thickness of the first region of the contact interface layer” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed thickness of the second region of the contact interface layer greater than a thickness of the first region of the contact interface layer). Also, the applicant has not shown that the claimed “difference of thickness of the second region of the contact interface layer greater than a thickness of the first region of the contact interface layer” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Fan discloses “a thickness of the second region of the contact interface layer similar to a thickness of the first region of the contact interface layer”, therefore, the thickness is a result effective variable. It has been held that is not inventive to discover the optimum thickness of the second region of the contact interface layer and the thickness of the first region of the contact interface layer by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to a thickness of the second region of the contact interface layer is greater than a thickness of the first region of the contact interface layer to improve the electrical connection between the contact electrode and the source and drain pattern ([0037], Fan).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lee et al. (US 20210082914 A1) teaches “INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME”. This document is related to an integrated circuit device including a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.
Chang et al. (US 20230138401 A1) teaches “METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE”. This document is related to a method of manufacturing a semiconductor device, a source/drain epitaxial layer is formed, one or more dielectric layers are formed over the source/drain epitaxial layer, an opening is formed in the one or more dielectric layers to expose the source/drain epitaxial layer, a first silicide layer is formed on the exposed source/drain epitaxial layer, a second silicide layer different from the first silicide layer is formed on the first silicide layer, and a source/drain contact is formed over the second silicide layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA MILENA RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
Prosecution Insights