DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10 in the reply filed on 05/18/26 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong(USPGPUB DOCUMENT: 2018/0358293, hereinafter Hong) in view of Kim (USPGPUB DOCUMENT: 2021/0028112, hereinafter Kim).
Re claim 1 Hong discloses in Fig 1B a semiconductor device comprising: a substrate(101); an active region(AR1/AR2) extending on the substrate(101) in a first direction(X); a device isolation layer(107) on the active region(AR1/AR2); a gate structure(GS1/GS2) extending in a second direction(Y), intersecting the first direction(X); a source/drain region(110/210) on the active region(AR1/AR2) on one side of the gate structure(GS1/GS2); an interlayer insulating layer(162)[0037] on the device isolation layer(107) and on the gate structure(GS1/GS2) and the source/drain region(110/210); a stopper layer(161) on the interlayer insulating layer(162)[0037]; a contact structure(CS1/CS2/195A/195B) passing through the interlayer insulating layer(162)[0037] and the stopper layer(161) and electrically connected to the source/drain region(110/210); wherein the stopper layer(161) is in contact with a portion of a side surface of the contact structure(CS1/CS2/195A/195B), and a lower surface of the stopper layer(161) is lower than an upper surface of the contact structure(CS1/CS2/195A/195B), relative to the substrate(101).
Hong does not disclose wherein the stopper layer(161) comprises a different material than the interlayer insulating layer(162)[0037]; and a conductive through-structure extending in the first direction(X), passing through the device isolation layer(107) and the interlayer insulating layer(162)[0037] from a lower surface of the substrate(101), and extending in a third direction(Z), perpendicular to the first and second direction(Y)s, to contact a lower surface of the contact structure(CS1/CS2/195A/195B) and the stopper layer(161),
Kim disclose in Fig 2 wherein the stopper layer(oxide)[0041 of Kim]; and a conductive through-structure(120/250 of Kim) extending in the first direction(X), and extending in a third direction(Z), perpendicular to the first and second direction(Y)s, to contact a lower surface of the contact structure(180 of Kim)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Kim to the teachings of Hong in order to minimize problems in which undesired short-circuits may occur in interconnecting the metal wiring and the active regions [0004, Kim]. In doing so, wherein the stopper layer(oxide)[0041 of Kim] comprises a different material than the interlayer insulating layer(borosilica glass)(162)[0036,0037]; and a conductive through-structure(120/250 of Kim) extending in the first direction(X), passing through the device isolation layer(107) and the interlayer insulating layer(162)[0037] from a lower surface of the substrate(101), and extending in a third direction(Z), perpendicular to the first and second direction(Y)s, to contact a lower surface of the contact structure(180 of Kim) and the stopper layer(161),
Regarding the limitation “a stopper layer on the interlayer insulating layer ". The interpretation of "on" is being interpreted as used to indicate immediate proximity. This interpretation is being based from a general purpose dictionary (see www.Dictionary.com) is the evidence that's being relied upon to show that it's a reasonable interpretation.
Re claim 2 Hong and Kim disclose the semiconductor device of claim 1, wherein a portion of the contact structure(CS1/CS2/195A/195B) that passes through the stopper layer(161) has a width that increases toward the substrate(101) in the third direction(Z).
Re claim 3 Hong and Kim disclose the semiconductor device of claim 1, wherein the lower surface of the stopper layer(161) is higher than the lower surface of the contact structure(CS1/CS2/195A/195B) and an uppermost end of the source/drain region(110/210) relative to the substrate(101).
Re claim 4 Hong and Kim disclose the semiconductor device of claim 1, wherein a width of the conductive through- structure decreases toward the stopper layer(161).
Re claim 5 Hong and Kim disclose the semiconductor device of claim 1, wherein the stopper layer(161) comprises a seam therein extending in the third direction(Z).
Re claim 6 Hong and Kim disclose the semiconductor device of claim 1, wherein an upper surface of the stopper layer(161) is substantially coplanar with the upper surface of the contact structure(CS1/CS2/195A/195B) and an upper surface of the gate structure(GS1/GS2).
Re claim 7 Hong and Kim disclose the semiconductor device of claim 1, wherein an upper surface of the stopper layer(161) is lower than an upper surface of the contact structure(CS1/CS2/195A/195B) relative to the substrate(101).
Re claim 8 Hong and Kim disclose the semiconductor device of claim 1, further comprising: a plurality of channel layers on the active region(AR1/AR2) and spaced apart from each other in the third direction(Z), wherein the gate structure(GS1/GS2) includes a gate electrode extending in the second direction(Y) and on each of the plurality of channel layers, and a gate dielectric layer(142) between each of the plurality of channel layers and the gate electrode.
Re claim 9 Hong and Kim disclose the semiconductor device of claim 1, further comprising: a lower interlayer insulating layer(162)[0037] on the lower surface of the substrate(101); and a power delivery structure extending from a lower surface of the lower interlayer insulating layer(162)[0037] toward an upper surface of the lower interlayer insulating layer(162)[0037], and electrically connected to the conductive through-structure(120/250 of Kim).
Re claim 10 Hong and Kim disclose the semiconductor device of claim 9, further comprising: a first interconnection portion[0048] on the stopper layer(161) and electrically connected to the contact structure(CS1/CS2/195A/195B); and a second interconnection portion[0048] electrically connected to the power delivery structure on a lower surface of the conductive through-structure(120/250 of Kim), wherein the conductive through-structure(120/250 of Kim) is spaced apart from the first interconnection portion[0048] by the stopper layer(161).
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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