DETAILED ACTION
This Office Action is in response to the Amendments filed 26 May 2026. Claims 15-18, 20-35 are pending in this application.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 29, 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et. al (US 2024/0008242 A1) (of record).
Regarding Claim 29, Xie discloses (as shown in Figs. 2-13) a method comprising:
forming a device layer, the device layer comprising:
a first transistor ([0034] a bottom nanosheet-containing material stack, NS1) ([0069] one bottom transistor BT1) comprising a first gate stack ([0050] The gate structure 33) along at least three sides of a channel region ([0039] the non-etched (i.e., remaining) portion of each semiconductor channel material layer 16L is referred to as a semiconductor channel material nanosheet 16), ([0050] The gate structure 33 wraps around the semiconductor channel material nanosheets 16)
wherein the first gate stack (33) comprises a first gate dielectric and a first gate electrode, ([0050] The gate structure 33 includes at least a gate dielectric material layer and a gate electrode)
and wherein the channel region (16) and the first gate dielectric overlaps a gate etch stop layer (ESL) (12); (See Fig. 7D, showing the gates 33 and the semiconductor channel material nanosheets 16 above the dielectric layer 12)
and a second transistor ([0034] a top nanosheet-containing material stack, NS2) ([0069] two top transistors, TT1 and TT2) vertically stacked with the first transistor (NS1); ([0039] each vertical material stack, MS, that now includes the dielectric device separating material layer is converted into a nanosheet-containing material stack including a bottom nanosheet-containing material stack, NS1, and a top nanosheet-containing material stack, NS2)
forming a first interconnect structure on a front side of the device layer; ([0065] The frontside contact structures include at least one frontside shared S/D contact structure 40C that contacts the top S/D region 32 and one of the bottom S/D structures 28S of the stacked field effect transistors (e.g., 100) that share a shared gate structure, at least one frontside gate contact structure 40A that contacts a topmost portion of the gate structure 33, and at least one frontside top S/D contact structure 40B that contacts one of the top S/D regions 32. [0066] The BEOL structure that forms a part of the BEOL/carrier wafer structure 44 includes one or more interconnect dielectric material layers that contact one or more wiring regions embedded thereon. The BEOL structure can be formed utilizing BEOL processing techniques that are well known to those skilled in the art.)
flipping an orientation of the device layer and the first interconnect structure; exposing the gate ESL (12); ([0068] after wafer flipping and removing the semiconductor substrate 10 to reveal a surface of the dielectric material layer 12)
and forming a gate contact on a backside of the device layer, ([0072] a backside gate contact structure 48A)
wherein the gate contact (48A) extends through the gate ESL (12) and the first gate dielectric to contact the first gate electrode (33). ([0072] The backside gate contact structure 48A and the backside bottom S/D contact structure 48B are formed within the dielectric material layer 12) ([0073] The backside gate contact structure 48A (which contacts a bottommost surface of gate structure 33))
However, Xie fails to disclose that the gate contact 48A extends through the gate dielectric.
Xie teaches that a continuous layer of gate dielectric is formed in the gate opening. ([0051] The forming of the gate structure 33 includes forming a continuous layer of gate dielectric material and a gate electrode material inside and the gate opening.) It would have been obvious to extend the backside gate contact 48A through the continuous gate dielectric layer in order to contact the gate electrode.
Regarding Claim 31, Xie further discloses (as shown in Fig. 2-13) wherein the first gate dielectric comprises a high-k dielectric material. ([0051] The continuous layer of gate dielectric material can include silicon oxide, or a dielectric material having a dielectric constant greater than 4.0 (such dielectric materials can be referred to as a high-k gate dielectric material).)
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie as applied to claim 29 above, and further in view of Taneja et. al (US 2023/0317615 A1) (of record).
Regarding Claim 32, Xie fails to disclose wherein the gate ESL (12) comprises a vertical interface between a first portion of the gate ESL and a second portion of the gate ESL.
Taneja discloses (as shown in Fig. 1C) a vertical interface between a first portion of the ESL ([0022] first etch stop layer 160) and a second portion of the ESL ([0022] second etch stop layer 162). (See Fig. 1C, showing a vertical interface where first etch stop layer 160 goes over second etch stop layer 162)
Taneja teaches that hybrid etch stop layers allows for spatially selective processing of sections of the device. ([0017] In an example, as the first dielectric material of the first etch stop layer is compositionally and/or structurally different from the second dielectric material of the second etch stop layer, spatially selective processing of sections of the underlayer is possible.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to substitute the hybrid etch stop layer of Taneja for the etch stop layer in Xie in order to allow for selective processing of sections of the device in Xie.
Allowable Subject Matter
Claims 15-18, 20-28, 35 allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 15, Amended Claim 15 properly incorporates the limitations of the previous Claim 19, which was indicated as containing allowable subject matter. Claim 15 is allowed for the same reasons.
Regarding Claims 16-18, 20, 35, Claims 16-18, 2-, 35 depend from Claim 15 and are allowed for the same reasons.
Regarding Claim 21, Amended Claim 21 incorporates the limitations of the previous Claim 19, which was indicated as containing allowable subject matter. Claim 21 is allowed for the same reasons.
Regarding Claims 22-28, Claims 22-28 depend from Claim 21 and are allowed for the same reasons.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 30, 33-34 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claims 30, 33-34, Claims 30, 33-34 were previously indicated as containing allowable subject matter. Claims 30, 33-34 continue to contain allowable subject matter for the same reasons.
Response to Arguments
Applicant's arguments regarding the rejection of Claim 29 filed 26 May 2026 have been fully considered but they are not persuasive.
Applicant argues (on Page 10 of their arguments) that Xie “merely teaches the asserted gate contact 48A reaches its gate dielectric material and does not teach or suggest that the asserted gate contact 48A extends through the gate dielectric to contact the gate electrode material.” This argument is not found persuasive. In semiconductor fabrication, a gate contact creates an electrical connection from the gate electrode to the metal wiring layers in order to supply voltage to the gate electrode. A person having ordinary skill in the art would understand that in order to function as a gate contact, the gate contact must be in electrical connection with the gate electrode in order to supply it voltage. If the gate contact merely reaches its gate dielectric material and does not extend through the gate dielectric to contact the gate electrode material, the gate contact is not in electrical connection with the gate electrode, and can thus not deliver voltage to the gate electrode and is incapable of functioning as a gate contact. Therefore, a person having ordinary skill in the art before the effective filing date of the application would understand that when Xie says “[0073] The backside gate contact structure 48A (which contacts a bottommost surface of gate structure 33)” it means that the backside gate contact structure 48A contacts a bottommost surface of the gate electrode, in order to make electrical connection with the gate electrode so as to function as a gate contact.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
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/JASON JAMES GREAVING/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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