DETAILED ACTION
This Office Action is in response to the Response to Election/Restriction filed 15 January 2025. Claims 15-34 are pending in this application. Claims 1-14 have been cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the method of Invention II in the reply filed on 15 January 2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 21-22 is/are rejected under 35 U.S.C. 102a(2) as being anticipated by Xie et. al (US 2024/0008242 A1)
Regarding Claim 21, Xie discloses (as shown in Figs. 2-13) a method comprising:
epitaxially growing a first source/drain region ([0042] Bottom S/D region 28 is of a first conductivity type (i.e., n-type or p-type) and is formed by an epitaxial growth process as defined below.) on sidewalls of a plurality of first nanostructures ([0034] bottom nanosheet-containing material stack, NS1) ([0039] NS1 and NS2, includes alternating sacrificial semiconductor material nanosheets 14 and semiconductor channel material nanosheets 16), ([0042] The bottom S/D region 28 grows outward from the physically exposed end sidewalls of each semiconductor channel material nanosheet 16.)
wherein the plurality of first nanostructures (16) overlaps an etch stop layer ([0044] The etch stops on the surface of the dielectric material layer 12 as is shown), (See Fig. 4D, showing the sources 28S formed above the dielectric material layer 12)
and wherein the plurality of first nanostructures (16) are alternatingly stacked with a first sacrificial material; ([0039] NS1 and NS2, includes alternating sacrificial semiconductor material nanosheets 14 and semiconductor channel material nanosheets 16)
replacing the first sacrificial material (14) with a first gate structure ([0050] The gate structure 33); ([0049] The removal of the sacrificial gate structure 20 and the sacrificial semiconductor material nanosheets 14 provides a gate opening above and below each suspended semiconductor channel material nanosheet 16 of the first and second nanosheet-containing material stacks, NS1 and NS2. [0050] The gate structure 33 is then formed into the gate openings.)
after replacing the first sacrificial material (14) with the first gate structure (33), exposing a surface of the etch stop layer (12) that is opposite to the plurality of first nanostructures (16); ([0068] after wafer flipping and removing the semiconductor substrate 10 to reveal a surface of the dielectric material layer 12. The removal of the semiconductor substrate typically includes a material removal process such as, for example, CMP or grinding.)
and forming a backside gate contact . ([0072] The backside gate contact structure 48A) extending through the etch stop layer (12) to the first gate structure (33). ([0072] The backside gate contact structure 48A … are formed within the dielectric material layer 12) ([0073] The backside gate contact structure 48A (which contacts a bottommost surface of gate structure 33))
Regarding Claim 22, Xie further discloses (as shown in Figs. 2-13) epitaxially growing a second source/drain region ([0045] The top S/D region 32 can be formed by an epitaxial growth process as defined above for the bottom S/D region 28) on sidewalls of a plurality of second nanostructures ([0045] semiconductor channel material nanosheet 16 of the top nanosheet-containing material stack, NS2), ([0045] The top S/D region 32 grows outward from the physically exposed end sidewalls of each semiconductor channel material nanosheet 16 of the top nanosheet-containing material stack, NS2.)
wherein the plurality of second nanostructures (16, NS2) overlaps the plurality of first nanostructures (16, NS1), (See Fig. 3C, showing the top nanosheet-containing stack NS2 on top of the bottom nanosheet-containing material NS1)
and wherein the plurality of second nanostructures (16, NS2) are alternatingly stacked with a second sacrificial material ([0034] sacrificial semiconductor material nanosheets 14); ([0034] each of the top and bottom nanosheet-containing material stacks, NS1 and NS2, includes alternating sacrificial semiconductor material nanosheets 14 and semiconductor channel material nanosheets 16)
and replacing the second sacrificial material (14) with a second gate structure. ([0049] The removal of the sacrificial gate structure 20 and the sacrificial semiconductor material nanosheets 14 provides a gate opening above and below each suspended semiconductor channel material nanosheet 16 of the first and second nanosheet-containing material stacks, NS1 and NS2. [0050] The gate structure 33 is then formed into the gate openings.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 15, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et. al (US 2024/0008242 A1) in view of Lee et. al (US 2024/0266256 A1).
Regarding Claim 15, Xie discloses (as shown in Figs.) A method comprising:
forming a first transistor ([0034] a bottom nanosheet-containing material stack, NS1) ([0069] one bottom transistor BT1) and a second transistor ([0034] a top nanosheet-containing material stack, NS2) ([0069] two top transistors, TT1 and TT2) over a semiconductor layer ([0025] semiconductor substrate 10),
wherein the first transistor (NS1) and the second transistor (NS2) are vertically stacked ([0039] each vertical material stack, MS, that now includes the dielectric device separating material layer is converted into a nanosheet-containing material stack including a bottom nanosheet-containing material stack, NS1, and a top nanosheet-containing material stack, NS2)
and wherein a backside gate etch stop layer (ESL) ([0044] The etch stops on the surface of the dielectric material layer 12) is disposed between a backside of a first gate structure ([0050] The gate structure 33) of the first transistor (NS1) and the semiconductor layer (10); ([0025] The exemplary semiconductor structure of FIG. 2 includes a pair of spaced apart vertical material stacks, MS, capped with a hard mask 18 and located on a surface of a dielectric material layer 12. The dielectric material layer 12 is located on a semiconductor substrate 10.)
removing the semiconductor layer (10) to expose the backside gate etch stop layer (12); ([0068] after wafer flipping and removing the semiconductor substrate 10 to reveal a surface of the dielectric material layer 12)
patterning an opening through backside gate ESL (12) to expose the first gate structure (33); and forming a backside gate contact ([0072] backside gate contact structure 48A) in the opening. ([0073] The backside contact structures can be formed by providing backside contact openings (typically by lithography and etching), filling the backside openings with at least the contact conductor material)
However, Xie fails to disclose depositing a backside interlayer dielectric (ILD) over the backside gate ESL (12);
patterning an opening through the backside ILD and the backside gate ESL (12) to expose the first gate structure (33);
Lee discloses (as shown in Figs. 13A-16) depositing a backside interlayer dielectric (ILD) ([0145] a dielectric material to form a substrate 105) over the backside gate ESL ([0142] the etch stop layer ESL); ([0145] an area where the semiconductor substrate 100 is removed may be filled with a dielectric material to form a substrate 105)
patterning an opening through the backside ILD (105) and the backside gate ESL (ESL) to expose the source/drain patterns; ([0146] The substrate 105 may undergo an anisotropic etching process such that the mask pattern MAP may be used as an etching mask to form first and second backside contact holes BCH1 and BCH2.)
Lee teaches that the dielectric substrate 105 (the backside ILD in the claim) the etch stop layer is used to replace a semiconductor substrate with a dielectric substrate in order to reduce leakage current. ([0155] According to the present disclosure, an etch stop layer may be used to replace a semiconductor substrate with a dielectric substrate. It may thus be possible to prevent and/or reduce a leakage current from a transistor to a substrate and/or to improve electrical properties of devices.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to replace the removed semiconductor substrate in Xie with a dielectric substrate in order to reduce leakage current. It would then be necessary to form the contact opening through the dielectric substrate 105 as disclosed in Lee.
Regarding Claim 20, Xie further discloses (as shown in Fig. 13B) wherein the backside gate contact (48A) overlaps first nanostructures (16) of the first transistor and second nanostructures (16) of the second transistor. (See Fig. 13B, showing the backside gate contact structure 48A below the semiconductor channel material nanosheets 16)
Claim(s) 29, 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et. al (US 2024/0008242 A1).
Regarding Claim 29, Xie discloses (as shown in Figs. 2-13) a method comprising:
forming a device layer, the device layer comprising:
a first transistor ([0034] a bottom nanosheet-containing material stack, NS1) ([0069] one bottom transistor BT1) comprising a first gate stack ([0050] The gate structure 33) along at least three sides of a channel region ([0039] the non-etched (i.e., remaining) portion of each semiconductor channel material layer 16L is referred to as a semiconductor channel material nanosheet 16), ([0050] The gate structure 33 wraps around the semiconductor channel material nanosheets 16)
wherein the first gate stack (33) comprises a first gate dielectric and a first gate electrode, ([0050] The gate structure 33 includes at least a gate dielectric material layer and a gate electrode)
and wherein the channel region (16) and the first gate dielectric overlaps a gate etch stop layer (ESL) (12); (See Fig. 7D, showing the gates 33 and the semiconductor channel material nanosheets 16 above the dielectric layer 12)
and a second transistor ([0034] a top nanosheet-containing material stack, NS2) ([0069] two top transistors, TT1 and TT2) vertically stacked with the first transistor (NS1); ([0039] each vertical material stack, MS, that now includes the dielectric device separating material layer is converted into a nanosheet-containing material stack including a bottom nanosheet-containing material stack, NS1, and a top nanosheet-containing material stack, NS2)
forming a first interconnect structure on a front side of the device layer; ([0065] The frontside contact structures include at least one frontside shared S/D contact structure 40C that contacts the top S/D region 32 and one of the bottom S/D structures 28S of the stacked field effect transistors (e.g., 100) that share a shared gate structure, at least one frontside gate contact structure 40A that contacts a topmost portion of the gate structure 33, and at least one frontside top S/D contact structure 40B that contacts one of the top S/D regions 32. [0066] The BEOL structure that forms a part of the BEOL/carrier wafer structure 44 includes one or more interconnect dielectric material layers that contact one or more wiring regions embedded thereon. The BEOL structure can be formed utilizing BEOL processing techniques that are well known to those skilled in the art.)
flipping an orientation of the device layer and the first interconnect structure; exposing the gate ESL (12); ([0068] after wafer flipping and removing the semiconductor substrate 10 to reveal a surface of the dielectric material layer 12)
and forming a gate contact on a backside of the device layer, ([0072] a backside gate contact structure 48A)
wherein the gate contact (48A) extends through the gate ESL (12) and the first gate dielectric to contact the first gate electrode (33). ([0072] The backside gate contact structure 48A and the backside bottom S/D contact structure 48B are formed within the dielectric material layer 12) ([0073] The backside gate contact structure 48A (which contacts a bottommost surface of gate structure 33))
However, Xie fails to disclose that the gate contact 48A extends through the gate dielectric.
Xie teaches that a continuous layer of gate dielectric is formed in the gate opening. ([0051] The forming of the gate structure 33 includes forming a continuous layer of gate dielectric material and a gate electrode material inside and the gate opening.) It would have been obvious for the backside gate contact 48A would have to extend through the continuous gate dielectric layer in order to contact the gate electrode.
Regarding Claim 31, Xie further discloses (as shown in Fig. 2-13) wherein the first gate dielectric comprises a high-k dielectric material. ([0051] The continuous layer of gate dielectric material can include silicon oxide, or a dielectric material having a dielectric constant greater than 4.0 (such dielectric materials can be referred to as a high-k gate dielectric material).)
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie as applied to claim 29 above, and further in view of Taneja et. al (US 2023/0317615 A1).
Regarding Claim 32, Xie fails to disclose wherein the gate ESL (12) comprises a vertical interface between a first portion of the gate ESL and a second portion of the gate ESL.
Taneja discloses (as shown in Fig. 1C) a vertical interface between a first portion of the ESL ([0022] first etch stop layer 160) and a second portion of the ESL ([0022] second etch stop layer 162). (See Fig. 1C, showing a vertical interface where first etch stop layer 160 goes over second etch stop layer 162)
Taneja teaches that hybrid etch stop layers allows for spatially selective processing of sections of the device. ([0017] In an example, as the first dielectric material of the first etch stop layer is compositionally and/or structurally different from the second dielectric material of the second etch stop layer, spatially selective processing of sections of the underlayer is possible.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to substitute the hybrid etch stop layer of Taneja for the etch stop layer in Xie in order to allow for selective processing of sections of the device in Xie.
Allowable Subject Matter
Claim 16-19,23-28,30 and 33-34 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 16, Xie in view of Lee further discloses forming a multi-layer stack ([0025] The exemplary semiconductor structure of FIG. 2 includes a pair of spaced apart vertical material stacks, MS) over a first semiconductor substrate ([0025] a semiconductor substrate 10), the multi-layer stack (MS) comprising a first semiconductor material ([0028] semiconductor channel material layers 16L) alternatingly arranged with a second semiconductor material ([0028] sacrificial semiconductor material layers 14L); ([0039] each vertical material stack, MS, that now includes the dielectric device separating material layer is converted into a nanosheet-containing material stack including a bottom nanosheet-containing material stack, NS1, and a top nanosheet-containing material stack, NS2 … NS1 and NS2, includes alternating sacrificial semiconductor material nanosheets 14 and semiconductor channel material nanosheets 16)
depositing a high-k dielectric layer over the multi-layer stack; ([0051] The forming of the gate structure 33 includes forming a continuous layer of gate dielectric material and a gate electrode material inside and the gate opening.)
patterning the multi-layer stack (MS), wherein patterning the multi-layer stack (MS) comprises forming semiconductor nanostructures ([0039] semiconductor channel material nanosheet 16) from the first semiconductor material ([0039] semiconductor channel material layer 16L) and dummy nanostructures ([0039] sacrificial semiconductor material nanosheet 14) from the second semiconductor material ([0039] sacrificial semiconductor material layer 14L) ([0039] The converting includes an etching process in which the sacrificial gate structure 20 and the dielectric spacer 22 are used as an etch mask. In the present application, the non-etched (i.e., remaining) portion of each sacrificial semiconductor material layer 14L is referred to as a sacrificial semiconductor material nanosheet 14, the non-etched (i.e., remaining) portion of each semiconductor channel material layer 16L is referred to as a semiconductor channel material nanosheet 16, and the non-etched (i.e., remaining) portion of the dielectric device separating material layer is referred to as dielectric material nanosheet 24.)
and wherein forming the first transistor comprises replacing the dummy nanostructures (14) with the first gate structure (33); ([0049] [0049] The sacrificial gate structure 20 and the surficial semiconductor material nanosheets 14 of both the first and second nanosheet-containing material stack, NS1 and NS2, are removed… The removal of the sacrificial gate structure 20 and the sacrificial semiconductor material nanosheets 14 provides a gate opening … [0050] The gate structure 33 is then formed into the gate openings.)
And patterning the high-k dielectric layer (12) to form the backside gate ESL. ([0056] The full gate cut structure 34 passes entirely through the gate structure 33 and entirely through the dielectric material layer 12 without passing through any of the semiconductor channel materials nanosheets 14 of both the bottom and top nanosheet-containing material stacks, NS1 and NS2. The full gate structure 34 defines device regions in which the semiconductor device of the present application is located… [0057] The full gate cut structure 34 and the top gate cut structure 36 can be formed by first defining a full gate cut trench and a top gate cut trench in the exemplary structure by lithography and etching)
However, Xie fails to disclose bonding a second semiconductor substrate over the multi-layer stack (MS);
thinning the first semiconductor substrate (10);
In Xie, the dielectric material layer 12 (which acts as the backside gate ESL) is formed as a solid layer underneath the multilayer stack (MS). There is no indication it is formed after the material stack by deposition and patterning of a high-k dielectric using the wafer flipping process claimed.
Since the Claim contains limitations not found in the prior art, it contains allowable subject matter.
Regarding Claim 17, Claim 17 depends from Claim 16 and contains allowable subject matter for the same reasons.
Regarding Claim 18, Xie in view of Lee further discloses forming a dummy semiconductor material ([0027] sacrificial semiconductor material layer 14L) over the semiconductor layer (10); ([0027] In such an embodiment, the thinned top semiconductor layer can be used as a bottom sacrificial semiconductor material layer 14L of the vertical material stacks shown in FIG. 2)
forming a multi-layer stack ([0025] The exemplary semiconductor structure of FIG. 2 includes a pair of spaced apart vertical material stacks, MS) over the dummy semiconductor material (14L), ([0027] In such an embodiment, the thinned top semiconductor layer can be used as a bottom sacrificial semiconductor material layer 14L of the vertical material stacks shown in FIG. 2)
the multi-layer stack (MS) comprising a first semiconductor material (16L) alternatingly arranged with a second semiconductor material (14L); ([0039] each vertical material stack, MS, that now includes the dielectric device separating material layer is converted into a nanosheet-containing material stack including a bottom nanosheet-containing material stack, NS1, and a top nanosheet-containing material stack, NS2 … NS1 and NS2, includes alternating sacrificial semiconductor material nanosheets 14 and semiconductor channel material nanosheets 16)
patterning the multi-layer stack (MS) and the dummy semiconductor material (14L),
wherein patterning the multi-layer stack (MS) and the dummy semiconductor material (14L) comprises forming a first dummy nanostructure ([0039] a sacrificial semiconductor material nanosheet 14) from the dummy semiconductor material (14L), ([0039] The converting includes an etching process in which the sacrificial gate structure 20 and the dielectric spacer 22 are used as an etch mask. In the present application, the non-etched (i.e., remaining) portion of each sacrificial semiconductor material layer 14L is referred to as a sacrificial semiconductor material nanosheet 14)
forming semiconductor nanostructures ([0039] semiconductor channel material nanosheet 16) from the first semiconductor material (16L), and forming second dummy nanostructures (sacrificial semiconductor material nanosheet 14) from the second semiconductor material (14L), and wherein forming the first transistor comprises replacing the second dummy nanostructures with the first gate structure; ([0039] The converting includes an etching process in which the sacrificial gate structure 20 and the dielectric spacer 22 are used as an etch mask. In the present application, the non-etched (i.e., remaining) portion of each sacrificial semiconductor material layer 14L is referred to as a sacrificial semiconductor material nanosheet 14, the non-etched (i.e., remaining) portion of each semiconductor channel material layer 16L is referred to as a semiconductor channel material nanosheet 16, and the non-etched (i.e., remaining) portion of the dielectric device separating material layer is referred to as dielectric material nanosheet 24.)
However, Xie in view of Lee fails to disclose replacing the first dummy nanostructure with a high-k material to form the backside gate ESL.
Since the Claim contains limitations not found in the prior art, it contains allowable subject matter.
Regarding Claim 19, Xie in view of Lee fails to disclose after removing the semiconductor layer (10), depositing an additional backside ESL over the backside gate ESL (12), wherein the backside ILD (52) is deposited over the additional backside ESL, and wherein patterning the opening further comprises patterning the opening through the additional backside ESL.
Since the Claim contains limitations not found in the prior art, it contains allowable subject matter.
Regarding Claim 23, Xie further discloses forming the plurality of first nanostructures (16) by patterning the plurality of semiconductor layers ([0028] semiconductor channel material layers 16L). ([0039] The converting includes an etching process in which the sacrificial gate structure 20 and the dielectric spacer 22 are used as an etch mask. In the present application, … the non-etched (i.e., remaining) portion of each semiconductor channel material layer 16L is referred to as a semiconductor channel material nanosheet 16…)
However, Xie in view of Lee fails to disclose depositing the etch stop layer (12) over a plurality of semiconductor layers ([0028] semiconductor channel material layers 16L);
flipping an orientation of the plurality of semiconductor layers (16L) and the etch stop layer (12) such that the plurality of semiconductor layers (16L) are disposed over the etch stop layer (12);
Since the Claim contains limitations not found in the prior art, it contains allowable subject matter.
Regarding Claim 24, Xie further discloses (as shown in Figs. 2-13) patterning a first recess through the plurality of first nanostructures (16, NS1), ([0034] removing the placeholder semiconductor material layer from the each vertical material stack, MS)
wherein the first recess exposes a second sacrificial material under the first plurality of nanostructures (16, NS1); ([0027] the thinned top semiconductor layer can be used as a bottom sacrificial semiconductor material layer 14L of the vertical material stacks shown in FIG. 2 of the present application.)
removing a first portion of the second sacrificial material (14L) through the first recess to define a second recess; ([0034] removing the placeholder semiconductor material layer from the each vertical material stack, MS)
However, Xie fails to disclose after removing the first portion of the second sacrificial material (14L), depositing a first etch stop material in the second recess, wherein the etch stop layer comprises the first etch stop material.
Since the Claim contains limitations not found in the prior art, it contains allowable subject matter.
Regarding Claims 25-28, Claims 25-28 depend from Claim 24 and contain allowable subject matter for the same reasons.
Regarding Claim 30, Xie fails to disclose wherein the first gate dielectric extends along sidewalls of the gate etch stop layer (11).
Other relevant prior art includes Galatage et. al (US 2023/0402513 A1). Galatage discloses (as shown in Fig. 1A) a first transistor ([0031] lower device 140) comprising a first gate stack ([0034] gate structure 172) along at least three sides of a channel region, ([0034] In one embodiment, each of gate structures 172 of the device 140 wraps around each of the nanoribbons 103b in the corresponding channel region.)
wherein the first gate stack (122) comprises a first gate dielectric and a first gate electrode; ([0035] each of the gate structures 122, 172 includes a corresponding gate electrode and a gate dielectric 120)
and a second transistor ([0031] upper device 101) vertically stacked with the first transistor (140); ([0031] The device configuration includes vertically stacked devices 101 and 140)
forming a gate contact on a backside of the device layer ([0034] backside conductive gate contacts 175a, 175b, and 175c),
and wherein the first gate dielectric (120) extends along sidewalls of the gate contact (175b). (See fig. 1A)
However, Galatage fail to disclose an etch stop layer, that the gate contact extends through the etch stop layer and dielectric layer, and that the first gate dielectric extends along sidewalls of the etch stop layer.
Since the Claim contains limitations not found in the prior art, it contains allowable subject matter.
Regarding Claim 33, Xie fails to disclose prior to forming the gate contact (48A), depositing an additional ESL interfacing a lateral surface of the gate ESL (12), wherein forming the gate contact (48A) comprises forming the gate contact (48A) through the additional ESL.
Since the Claim contains limitations not found in the prior art, it contains allowable subject matter.
Regarding Claim 34, Claim 34 depend from Claim 35 and contains allowable subject matter for the same reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON JAMES GREAVING/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893