DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 9 March 2026 is acknowledged.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 9 March 2026.
Information Disclosure Statements
The Information Disclosure Statements (IDS) submitted on 8 September 2023 and 27 January 2026 have been considered by the examiner and made of record in the application file.
Drawings
The drawings are objected to because the labels for layers 6B and 6F appear to be reversed in Figures 32 and 48. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 13 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. The claim states “...wherein a total number of electrically conductive layers within the subsets of the electrically conductive layers for the additional layer contact via structures are different of the subsets of the electrically conductive layers”, which appears to be a circular reference to the subsets of the electrically conductive layers with and incoherent usage of the phrase --of the subsets--. For the purpose of examination, the phrase will be interpreted as “...wherein a total number of electrically conductive layers within the subsets of the electrically conductive layers for the additional layer contact via structures varies.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, and 8-15 are rejected under 35 U.S.C. 103 as being unpatentable over Sel et al (US 20180350879 A1, hereinafter “Sel”), in view of Kaminaga (US 20200035694 A1, hereinafter “Kaminaga”).
Regarding Claim 1 - Sel discloses a semiconductor structure comprising: an alternating stack of insulating layers (60 Sel [0057] and Fig. 20A) and electrically conductive layers (30 Sel [0057] and Fig. 20A); a memory opening vertically extending through the alternating stack (Opening in which 45 is formed, Sel [0141 and Fig. 20A); a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel (45 Sel [0141] and Fig. 20A); and a layer contact via structure vertically extending through a subset of the electrically conductive layers and a subset of the insulating layers that includes the bottommost insulating layer (66 Sel [0143] and Fig. 20A), and contacting a surface of a topmost electrically conductive layer within the subset of the electrically conductive layers (Sel [0143] and Top Surface in annotated Fig. 20A).
Sel fails to disclose the electrically conductive layers have different lateral extents that decrease along an upward vertical direction from a bottommost insulating layer to a topmost insulating layer of the insulating layers.
However, Kaminaga discloses the electrically conductive layers have different lateral extents that decrease along an upward vertical direction from a bottommost insulating layer to a topmost insulating layer of the insulating layers (200 Kaminaga [0217] and Fig. 3).
Kaminaga discloses a similar memory structure to Sel. Kaminaga teaches a memory device integrating a staircase stack structure in the connection area for the benefits of reduced chip area and cost (Kaminaga [0180]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining Sel and Kaminaga to obtain the benefits of reduced chip area and cost.
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Regarding Claim 3 - Sel modified by Kaminaga discloses all the limitations of claim 1.
The combination of Sel and Kaminaga further discloses the topmost surface of the layer contact via structure is located below a horizontal plane including a topmost surface of the alternating stack (668 Kaminaga [420] and Fig. 60K).
Kaminaga discloses a similar memory structure to Sel. Kaminaga teaches a stair-stepped alternating stack structure that has contact structures with a topmost surface below the horizontal plane of the topmost surface of the alternating stack for the benefit of high density (Kaminaga [0003]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining Sel and Kaminaga to obtain the benefit of a high density memory structure.
Regarding Claim 4 - Sel modified by Kaminaga discloses all the limitations of claim 1.
The combination of Sel and Kaminaga further discloses a backside dielectric layer located over a bottom surface of the bottommost insulating layer (190A Sel [0068] and Fig. 20A), wherein the layer contact via structure vertically extends through the backside dielectric layer (Sel [0095] and Fig. 20A), wherein the layer contact via structure vertically extends through the backside dielectric layer (Sel [0095] and Fig. 20A).
Regarding Claim 5 - Sel modified by Kaminaga discloses all the limitations of claim 4.
The combination of Sel and Kaminaga further discloses the layer contact via structure comprises: a via portion that vertically extends through the subset of the electrically conductive layers and the subset of the insulating layers (66 Sel [0064] and Fig. 20A); and a plug portion that vertically extends through the backside dielectric layer, adjoined to a bottom end of the via portion, and having a greater lateral extent than the via portion (162C Sel [0057] and Fig. 20A).
Regarding Claim 8 – Sel modified by Kaminaga discloses all the limitations of claim 1.
The combination of Sel and Kaminaga further discloses the surface of the topmost electrically conductive layer comprises a sidewall surface, and the layer contact via structure contacts the sidewall surface of the topmost electrically conductive layer (Kaminaga [0436] and Fig. 60L).
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Regarding Claim 9 – Sel modified by Kaminaga discloses all the limitations of claim 8.
The combination of Sel and Kaminaga further discloses the layer contact via structure comprises: a metallic barrier liner in direct contact with the sidewall surface of the topmost electrically conductive layer within the subset of the electrically conductive layers (68A Kaminaga [0389] and Fig. 60L); and a metallic fill material portion that is laterally surrounded by the metallic barrier liner and laterally spaced from the topmost electrically conductive layer within the subset of the electrically conductive layers by a vertically-extending portion of the metallic barrier liner (68B Kaminaga [0389] and Fig. 60L).
Regarding Claim 10 – Sel modified by Kaminaga discloses all the limitations of claim 1.
The combination of Sel and Kaminaga further discloses a stepped dielectric material portion having a horizontal top surface and a stepped bottom surface that contacts the electrically conductive layers and a topmost surface of the layer contact via structure (A combination of 165 and 265, Kaminaga [0218], [0230], and Fig. 60K).
Regarding Claim 11 – Sel modified by Kaminaga discloses all the limitations of claim 10.
The combination of Sel and Kaminaga further discloses the stepped dielectric material portion is in direct contact with sidewalls of the electrically conductive layers and sidewalls of the insulating layers (165 and 265 contact sidewalls of 132, 146, 232, and 246 in Kaminaga Fig. 60K); and sidewalls of the electrically conductive layers are in direct contact with the stepped dielectric material portion, and are vertically coincident with a sidewall of a respective underlying insulating layer of the insulating layers (Kaminaga Figs. 57B (plan view) and 60K (cross section view)).
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Regarding Claim 12 – Sel modified by Kaminaga discloses all the limitations of claim 1.
The combination of Sel and Kaminaga further discloses a dielectric spacer (64 Sel [0102] and Fig. 13) laterally surrounding a via portion of the layer contact via structure and vertically extending through and contacting each electrically conductive layer and each insulating layer within the subset of the electrically conductive layers and the subset of the insulating layers (Sel [0102] and Fig. 13), wherein the layer contact via structure comprises a plate portion having a greater lateral extent than the via portion and contacting an annular top surface of the dielectric spacer (66U Sel [0105] and Fig. 20A).
Regarding Claim 13 – Sel modified by Kaminaga discloses all the limitations of claim 1.
The combination of Sel and Kaminaga further discloses additional layer contact via structures vertically extending through a respective subset of the electrically conductive layers and a respective subset of the insulating layers that includes the bottommost insulating layer of the insulating layers (66 Sel [0143] and Fig. 20A), contacting a sidewall surface of a respective topmost electrically conductive layer within the respective subset of the electrically conductive layers (68A in contact with sidewall of 46A, Kaminaga [0436] and Figs. 60K and 60L), wherein a total number of electrically conductive layers within the subsets of the electrically conductive layers for the additional layer contact via structures varies (Kaminaga Fig. 60K).
Regarding Claim 14 – Sel modified by Kaminaga discloses all the limitations of claim 1.
The combination of Sel and Kaminaga further discloses the alternating stack, the memory opening fill structure, and the layer contact via structures are located within a memory die (Sel [0056] and annotated Fig. 1B); and the semiconductor structure further comprises a logic die (integrated driver circuit Sel [0153] and annotated Fig. 1B) that is bonded to the memory die and comprises a peripheral circuit configured to control operation of the memory elements of the memory opening fill structure (Sel [0150]).
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Regarding Claim 15 – Sel modified by Kaminaga discloses all the limitations of claim 1.
The combination of Sel and Kaminaga further discloses a source contact layer (combination of 112, 114, and 116 Kaminaga [0271] and Fig. 52F) contacting a sidewall portion of the vertical semiconductor channel (60 Kaminaga [249] and Fig. 52F); and a source contact via structure (688 Kaminaga [0348] and Fig. 52F) contacting or electrically connected to the source contact layer (Kaminaga Fig. 52F) and comprising a same set of metallic materials as the layer contact via structure (liner 186A and fill material 186B are common across peripheral region contact via structures 488, array region contact via structures 588, and source contact via structures 688 Kaminaga [0348]).
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Claims 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Sel et al (US 20180350879 A1), in view of Kaminaga (US 20200035694 A1, hereinafter “Kaminaga”), and further in view of Kawaguchi (US 20240324217 A1, hereinafter “Kawaguchi”).
Regarding Claim 2 - Sel modified by Kaminaga discloses all the limitations of claim 1.
The combination of Sel and Kaminaga fails to disclose a topmost surface of the layer contact via structure is located at or below a horizontal plane including a top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers.
However, Kawaguchi discloses a topmost surface of the layer contact via structure is located at or below a horizontal plane including a top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers (CC Kawaguchi [0135-0136] and Fig. 36).
Kawaguchi discloses an analogous memory device to Sel. Kawaguchi teaches locating a topmost surface of the layer contact via structure at or below a horizontal plane including a top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers for the benefit of reducing chip area and the number of required process steps (Kawaguchi [0147]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Sel and Kawaguchi to locate a topmost surface of the layer contact via structure at or below a horizontal plane including a top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers for the benefit of reducing chip area and the number of required process steps.
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Regarding Claim 7 – Sel modified by Kaminaga discloses all the limitations of claim 1.
The combination of Sel and Kaminaga further discloses the layer contact via structure comprises: a via portion that vertically extends through the subset of the electrically conductive layers and the subset of the insulating layers (66L Sel [0105] and Fig. 20A).
The combination of Sel and Kaminaga fails to disclose a plate portion having an annular top surface located within or below a horizontal plane including a top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers and having a greater lateral extent than the via portion.
However, Kawaguchi discloses a plate portion having an annular top surface located within or below a horizontal plane including a top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers and having a greater lateral extent than the via portion (CC Kawaguchi [0135-0136] and Fig. 36).
Kawaguchi discloses an analogous memory device to Sel. Kawaguchi teaches locating a topmost surface of the layer contact via structure at or below a horizontal plane including a top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers for the benefit of reducing chip area and the number of required process steps (Kawaguchi [0147]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Sel and Kawaguchi to locate a topmost surface of the layer contact via structure at or below a horizontal plane including a top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers for the benefit of reducing chip area and the number of required process steps.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sel et al (US 20180350879 A1), in view of Kaminaga (US 20200035694 A1, hereinafter “Kaminaga”), and further in view of Wang et al (US 20210343639 A1, hereinafter “Wang”).
Regarding Claim 6 – Sel modified by Kaminaga discloses all the limitations of claim 5.
The combination of Sel and Kaminaga fails to disclose the plug portion comprises a tapered sidewall that vertically extends through the backside dielectric layer; and a lateral extent of the plug portion increase with a downward vertical distance from a horizontal plane including a top surface of the backside dielectric layer.
However, Wang discloses the plug portion comprises a tapered sidewall that vertically extends through the backside dielectric layer (318 Wang [0092] and Fig. 25); and a lateral extent of the plug portion increase with a downward vertical distance (away from the active device) from a horizontal plane including a top surface of the backside dielectric layer (Wang Fig. 25).
Wang describes a circuit with a similar via structure to Sel. Wang teaches a tapered via due to the nature of etching via openings in the backside IMD layers after the structure is flipped upside down (Wang [0092]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention that the backside vias would have a tapered sidewall as a natural consequence of etching via openings in the IMD layers after the structure is flipped upside down.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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