DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1, 5, 10, 13, and 15 have been amended in the reply dated 28 August 2026. Claims 4, and 16-20 have been cancelled. Claims 21-26 have been added.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8-9, 13-14, and 21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Baek (US 20230422527 A1, hereinafter “Baek”).
Regarding Claim 1 – Baek discloses a semiconductor structure comprising: a backside dielectric layer (labeled "Dielectric" in annotated Fig. 7; shown as combination of 120 and 120M in Fig. 9I [0118]); a source contact layer that comprises a semiconductor material overlying the backside dielectric layer (110 [0045] and Fig. 7); an alternating stack of insulating layers and electrically conductive layers overlying both the source contact layer and the backside dielectric layer (132 and 130 [0045] and Fig. 7), wherein the electrically conductive layers have different lateral extents that decrease along an upward vertical direction from a bottommost insulating layer to a topmost insulating layer of the insulating layers (130 decrease in lateral extent in the direction of peripheral circuit structure S1 [0040] and Fig. 7); a memory opening vertically extending through the alternating stack and overlying the backside dielectric layer (140H [0050]); a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel that is in contact with the source contact layer (140 [0049] and Figs. 5 and 7); and a layer contact via structure vertically extending through a subset of the electrically conductive layers and a subset of the insulating layers that includes the bottommost insulating layer (160 extends through a subset of 132 and 130 layers, including bottommost 132 [0058] and Fig. 7), and contacting a surface of a topmost electrically conductive layer within the subset of the electrically conductive layers (160 [0058] and Fig. 7), wherein the layer contact via structure comprises a metallic barrier liner that continuously extends from a first interface with the topmost electrically conductive layer within the subset of the electrically conductive layers through the subset of the insulating layers to a second interface with a sidewall of the backside dielectric layer (160B extends from each contacted 132 to sidewall of 120 [0059] and Figs. 4 and 7).
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Regarding Claim 8 - Baek discloses all the limitations of claim 1.
Baek further discloses the surface of the topmost electrically conductive layer comprises a sidewall surface, and the layer contact via structure contacts the sidewall surface of the topmost electrically conductive layer (Baek Fig. 7).
Regarding Claim 9 - Baek discloses all the limitations of claim 8.
Baek further discloses the layer contact via structure comprises: a metallic barrier liner in direct contact with the sidewall surface of the topmost electrically conductive layer within the subset of the electrically conductive layers (160B [0059] and Fig. 4); and a metallic fill material portion that is laterally surrounded by the metallic barrier liner and laterally spaced from the topmost electrically conductive layer within the subset of the electrically conductive layers by a vertically-extending portion of the metallic barrier liner (160A [0059] and Fig. 4).
Regarding Claim 13 - Baek discloses all the limitations of claim 1.
Baek further discloses additional layer contact via structures vertically extending through a respective subset of the electrically conductive layers and a respective subset of the insulating layers that includes the bottommost insulating layer of the insulating layers (160 extends through a subset of 132 and 130 layers, including bottommost 132 [0058] and Fig. 7), contacting a sidewall surface of a respective topmost electrically conductive layer within the respective subset of the electrically conductive layers (Baek Fig. 7), wherein the respective subsets of the electrically conductive layers through which the additional layer contact via structures vertically extend include different total numbers of the electrically conductive layers (Baek Fig. 7).
Regarding Claim 14 - Baek discloses all the limitations of claim 1.
Baek further discloses the alternating stack, the memory opening fill structure, and the layer contact via structures are located within a memory die (memory cell array 20 [0021-0023]); and the semiconductor structure further comprises a logic die that is bonded to the memory die and comprises a peripheral circuit configured to control operation of the memory elements of the memory opening fill structure (peripheral circuit 30 [0021] and [0024-0025]).
Regarding Claim 21 - Baek discloses all the limitations of claim 1.
Baek further discloses the via portion of the layer contact via structure is laterally encircled by the source contact layer (ends of 160 encircled by 110, Fig. 7).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 7, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Baek (US 20230422527 A1, hereinafter “Baek”), in view of Kawaguchi (US 20240324217 A1, hereinafter “Kawaguchi”).
Regarding Claim 2 – Baek discloses all the limitations of claim 1.
Baek fails to disclose a topmost surface of the layer contact via structure is located at or below a horizontal plane including a top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers.
However, Kawaguchi discloses a topmost surface of the layer contact via structure is located at or below a horizontal plane including a top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers (CC Kawaguchi [0135-0136] and Fig. 36).
Kawaguchi discloses an analogous memory device to Baek. Kawaguchi teaches locating a topmost surface of the layer contact via structure at or below a horizontal plane including a top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers for the benefit of reducing chip area and the number of required process steps (Kawaguchi [0147]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Baek and Kawaguchi to locate a topmost surface of the layer contact via structure at or below a horizontal plane including a top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers for the benefit of reducing chip area and the number of required process steps.
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Regarding Claim 3 – Baek discloses all the limitations of claim 1.
Baek fails to disclose the topmost surface of the layer contact via structure is located below a horizontal plane including a topmost surface of the alternating stack.
However, Kawaguchi discloses the topmost surface of the layer contact via structure is located below a horizontal plane including a topmost surface of the alternating stack (CC Kawaguchi [0135-0136] and Fig. 36).
Kawaguchi discloses an analogous memory device to Baek. Kawaguchi teaches locating a topmost surface of the layer contact via structure at or below a horizontal plane including a top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers for the benefit of reducing chip area and the number of required process steps (Kawaguchi [0147]). The topmost surface of the layer contact via structure being located below a horizontal plane including a topmost surface of the alternating stack is a consequence of this arrangement. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Baek and Kawaguchi to locate the topmost surface of the layer contact via structure below a horizontal plane including a topmost surface of the alternating stack for the benefit of reducing chip area and the number of required process steps.
Regarding Claim 7 – Baek discloses all the limitations of claim 1.
Baek further discloses the layer contact via structure comprises a via portion that vertically extends through the subset of the electrically conductive layers and the subset of the insulating layers (160 extends through a subset of 132 and 130 layers, including bottommost 132 [0058] and Fig. 7).
Baek fails to disclose a plate portion having an annular top surface located within or below a horizontal plane including a top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers and having a greater lateral extent than the via portion.
However, Kawaguchi discloses a plate portion having an annular top surface located within or below a horizontal plane including a top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers and having a greater lateral extent than the via portion (CC Kawaguchi [0135-0136] and Fig. 36).
Kawaguchi discloses an analogous memory device to Baek. Kawaguchi teaches locating a topmost surface of the layer contact via structure at or below a horizontal plane including a top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers for the benefit of reducing chip area and the number of required process steps (Kawaguchi [0147]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Baek and Kawaguchi to locate a topmost surface of the layer contact via structure at or below a horizontal plane including a top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers for the benefit of reducing chip area and the number of required process steps.
Regarding Claim 12 - Baek discloses all the limitations of claim 1.
Baek fails to disclose a dielectric spacer laterally surrounding a via portion of the layer contact via structure and vertically extending through and contacting each electrically conductive layer and each insulating layer within the subset of the electrically conductive layers and the subset of the insulating layers, wherein the layer contact via structure comprises a plate portion having a greater lateral extent than the via portion and contacting an annular top surface of the dielectric spacer.
However, Kawaguchi discloses a dielectric spacer laterally surrounding a via portion of the layer contact via structure and vertically extending through and contacting each electrically conductive layer and each insulating layer within the subset of the electrically conductive layers and the subset of the insulating layers (66 [0087] and Fig. 36), wherein the layer contact via structure comprises a plate portion having a greater lateral extent than the via portion and contacting an annular top surface of the dielectric spacer (CC Kawaguchi [0135-0136] and Fig. 36).
Kawaguchi discloses an analogous memory device to Baek. Kawaguchi teaches a dielectric spacer laterally surrounding a via portion of the layer contact via structure and vertically extending through and contacting each electrically conductive layer and each insulating layer within the subset of the electrically conductive layers and the subset of the insulating layers for the benefit of isolating each layer contact via structure from conductive layers intersected along its length (Kawaguchi [0087]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate a dielectric spacer laterally surrounding a via portion of the layer contact via structure and vertically extending through and contacting each electrically conductive layer and each insulating layer within the subset of the electrically conductive layers and the subset of the insulating layers for the benefit of isolating each layer contact via structure from conductive layers intersected along its length.
Regarding Claim 24 - Baek discloses all the limitations of claim 1.
Baek further discloses the layer contact via structure laterally surrounded by the source contact layer and the bottommost insulating layer and overlying the backside dielectric layer (160 [0058] and Fig. 7).
Baek fails to disclose a dielectric spacer laterally surrounding the layer contact via structure.
However, Kawaguchi discloses a dielectric spacer laterally surrounding the layer contact via structure (66 [0087] and Fig. 36).
Kawaguchi discloses an analogous memory device to Baek. Kawaguchi teaches a dielectric spacer laterally surrounding a via portion of the layer contact via structure and vertically extending through and contacting each electrically conductive layer and each insulating layer within the subset of the electrically conductive layers and the subset of the insulating layers for the benefit of isolating each layer contact via structure from conductive layers intersected along its length (Kawaguchi [0087]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate a dielectric spacer laterally surrounding a via portion of the layer contact via structure and vertically extending through and contacting each electrically conductive layer and each insulating layer within the subset of the electrically conductive layers and the subset of the insulating layers for the benefit of isolating each layer contact via structure from conductive layers intersected along its length.
Claims 5 is rejected under 35 U.S.C. 103 as being unpatentable over Baek (US 20230422527 A1, hereinafter “Baek”), in view of Sel et al (US 20180350879 A1, hereinafter “Sel”).
Regarding Claim 5 – Baek discloses all the limitations of claim 1.
Baek further discloses the layer contact via structure comprises a via portion that vertically extends through the subset of the electrically conductive layers and the subset of the insulating layers (160 [0058] and Fig. 7).
Baek fails to disclose a plug portion that vertically extends through the backside dielectric layer, adjoined to a bottom end of the via portion, and having a greater lateral extent than the via portion.
However, Sel discloses a plug portion that vertically extends through the backside dielectric layer, adjoined to a bottom end of the via portion, and having a greater lateral extent than the via portion (162C, Sel [0105] and Fig. 20A).
Sel describes a circuit with a similar via structure to Baek. Sel teaches a plug portion that vertically extends through the backside dielectric layer, having a greater lateral extent than the via portion, for the benefit of providing control signals to the electrically conductive layers within the alternating stack of insulating layers and electrically conductive layers (Sel [0068]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Baek and Sel to include a plug portion that vertically extends through the backside dielectric layer, having a greater lateral extent than the via portion, for the benefit of providing control signals to the electrically conductive layers within the alternating stack of insulating layers and electrically conductive layers.
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Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over Baek (US 20230422527 A1, hereinafter “Baek”), in view of Sel et al (US 20180350879 A1, hereinafter “Sel”), and further in view of Wang et al (US 20210343639 A1, hereinafter “Wang”).
Regarding Claim 6 – Baek modified by Sel discloses all the limitations of claim 5.
The combination of Baek and Sel fails to disclose the plug portion comprises a tapered sidewall that vertically extends through the backside dielectric layer; and a lateral extent of the plug portion increase with a downward vertical distance from a horizontal plane including a top surface of the backside dielectric layer.
However, Wang discloses the plug portion comprises a tapered sidewall that vertically extends through the backside dielectric layer (318 Wang [0092] and Fig. 25); and a lateral extent of the plug portion increase with a downward vertical distance (away from the active device) from a horizontal plane including a top surface of the backside dielectric layer (Wang Fig. 25).
Wang describes a circuit with a similar via structure to Baek. Wang teaches a tapered via due to the nature of etching via openings in the backside IMD layers after the structure is flipped upside down (Wang [0092]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention that the backside vias would have a tapered sidewall as a natural consequence of etching via openings in the IMD layers after the structure is flipped upside down.
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Allowable Subject Matter
Claims 10-11, 15, and 22-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 10 – The prior art pertinent to the instant application and known to the examiner does not teach nor render obvious the subject matter: "... a stepped dielectric material portion having a horizontal interface with a topmost surface of the layer contact via structure within a horizontal plane that is coplanar with a top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers."
Baek teaches: "A cover insulating layer 134 is disposed on the pad structure..." [0057], but the topmost surface of the layer contact via structure 160 has no interface with 134, as shown in Baek Fig. 7.
Kawaguchi teaches: "The insulating layer 24 covers an upper portion of the conductive layer 34." [0074] However, the interface between the insulating layer 24 and the layer contact via structure is not coplanar with a top of the last electrically conductive layer within the subset of electrically conductive layers due to the presence of layer 70 (Fig. 36 and [0136]).
Chen (US 20160204102 A1) teaches: "...a dielectric layer 21 is deposited on a staircase (r)egion..." [0036]. However, the dielectric layer cannot have an interface that is coplanar with the surface of electrically conductive layer 213 due to the presence of second conductive portions 315, 325, 335, and 345. See Fig. 15.
Claim 11 contains allowable subject matter at least because of its dependency on claim 10.
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Regarding Claims 15 and 26 – The prior art pertinent to the instant application and known to the examiner does not teach nor render obvious the subject matter: "... a source contact via structure contacting or electrically connected to the source contact layer and comprising a same set of metallic materials as the layer contact via structure." (Claim 15) and "... a source contact via structure ... comprising an additional metallic barrier liner having a same material composition and a same thickness as the metallic barrier liner." (Claim 26)
Baek teaches: "...a common source line contact 260 disposed in the cell region..." [0080], but fails to specify materials it comprises, whether a barrier liner is included, and thicknesses.
Kawaguchi teaches no source contact via structure.
Chen teaches no source via contact structure.
Regarding Claim 22 – The prior art pertinent to the instant application and known to the examiner does not teach nor render obvious the subject matter: "...a topmost surface of the layer contact via structure is a surface of a horizontally-extending portion of the metallic barrier liner."
Baek teaches the top (end toward the peripheral circuit) of the layer contact via structure 160 is not covered by the barrier layer, as shown in Figs. 7 and 4.
Kawaguchi teaches no metallic barrier liner.
Chen teaches no metallic barrier liner.
Claim 23 contains allowable subject matter at least because of its dependency on claim 22.
Regarding Claim 25 – The prior art pertinent to the instant application and known to the examiner does not teach nor render obvious the subject matter: "...the metallic barrier liner is in direct contact with an inner sidewall of the dielectric spacer, an annular top surface of the dielectric spacer, and an annular bottom surface of the dielectric spacer."
Baek teaches no continuous dielectric spacer (see Figs. 4 and 7), and combining Baek and Kawaguchi leaves the bottom of the dielectric spacer (the end of Baek 160 toward Baek 120/120M or Kawaguchi 27 or Sel 190A) without coverage by the barrier metal (Baek 160B).
Kawaguchi teaches no metallic barrier liner.
Chen teaches no metallic barrier liner.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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/JASON MCDONALD/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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