DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of claims 1-6 in the reply filed on 01/05/26 is acknowledged. By this election, claims 7-20 are withdrawn and claims 1-6 are pending in the application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamano (2009/0085222).
Regarding claim 1, Yamano (Fig. 24) discloses a semiconductor device comprising: a substrate 11 that includes an external terminal 14 ([0065]); a first semiconductor chip (31, 12-3) ([0071]) on or above which a first bonding pad 43 is arranged ([0075]); a second semiconductor chip (31, 12-2) that is arranged between the substrate 11 and the first semiconductor chip (31, 12-3) ([0071]), the second semiconductor chip (31, 12-2) on or above which a second bonding pad 43 and a first insulating film 44 being arranged ([0075]); a bonding wire 16 that connects the substrate 11, the first bonding pad 43, and the second bonding pad 43 ([0066]); and a sealing resin 13 that seals at least the first semiconductor chip 31, the second semiconductor chip 31, and the bonding wire 16 ([0064]), wherein: the second semiconductor chip (31, 12-2) includes a first surface 41B that faces the substrate 11, and a second surface 32A on an opposite side of the first surface; and the second surface 32A includes a first bonding region 43 where the second bonding pad 43 and the first insulating film 44 are arranged ([0075]), and a first lamination region 12-1 that has a first low-level surface formed that being lower than a surface of the first insulating film 44, the first semiconductor chip (31, 12-3) being arranged on or above at least a part of the first low-level surface (Fig. 24).
Regarding claim 2, Yamano (Fig. 24) discloses wherein the surface of the first insulating film 44 (#44 of the first semiconductor chip (31, 12-3)) is formed that being higher than a surface of the second bonding pad 43.
Regarding claim 3, Yamano (Fig. 24) discloses wherein: the first semiconductor chip (31, 12-3) includes a third surface that faces the substrate 11 across the second semiconductor chip (31, 12-2); and the semiconductor device 10 further comprises an adhesion layer 51 that performs adhesion between at least a part of the first lamination region on the second surface and at least a part of the third surface.
Regarding claim 5, Yamano (Fig. 24) discloses wherein: the second surface has a rectangular shape (Fig. 19); and the first bonding region 43 is positioned that being closer to one side of two facing sides of the rectangular shape than to the other side (Fig. 21).
Regarding claim 6, Yamano (Fig. 24) discloses wherein the first bonding region 43 abuts on the one side.
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record fails to disclose all the limitations recited in the above claim. Specifically, the prior art of record fails to disclose wherein a second insulating film is further arranged on or above the first semiconductor chip; the first semiconductor chip includes a third surface that faces the substrate across the second semiconductor chip, and a fourth surface on an opposite side of the third surface; and the fourth surface includes a second bonding region where the first bonding pad and the second insulating film are arranged, and a second lamination region that has a second low-level surface formed that being lower than a surface of the second insulating film, a third semiconductor chip being arranged on or above at least a part of the second low-level surface.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THERESA T DOAN whose telephone number is (571)272-1704. The examiner can normally be reached on Monday, Tuesday, Wednesday and Thursday from 7:00AM - 3:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WAEL FAHMY can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THERESA T DOAN/ Primary Examiner, Art Unit 2814