DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-20 in the reply filed on 12/22/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by OH et al. (US Pub. 2016/0181214).
Regarding claim 1, OH teaches a memory device, comprising:
a first memory die 304a and a second memory die 203a bonded together (Para [0272]) to form a first memory die package (see Fig. 19A below);
a third memory die 204a and a fourth memory die 203a bonded together (Para [0272]) to form a second memory die package (see Fig. 19A below), the second memory die package and the first memory die package forming a stack of memory die packages (see Fig. 19A below);
a switch (CBK, Fig. 6-7) electrically coupled to a top surface of the first memory die package 304a (Fig. 6-7 and respective text);
a first electrical connection electrically coupling the first memory die to the switch (note the electrical connection in the first memory die 304a as shown in Fig. 6-7 and Fig. 19A);
a second electrical connection (TSV) electrically coupling the second memory die 303a to the switch (it is understood that the second memory die 303a is connected to the switch, note TSV in 303a);
a third electrical connection (TSV) electrically coupling the third memory die 204a to the switch (it is understood that the third memory die 204a is connected to the switch, note TSV in 204a);
a fourth electrical connection TSV electrically coupling the fourth memory die 203a to the switch (it is understood that the fourth memory die 203a is connected to the switch, note TSV in 203a, see Fig 19A & Fig. 6-7B); and
a bond wire (e.g. the bond wire connecting 204a to the substrate 103) electrically coupling the switch to a substrate 103 of the memory device (see Fig. 19A below).
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Regarding claim 2, OH teaches the memory device of claim 1, wherein the switch CBK selectively electrically couples one of the first memory die, the second memory die, the third memory die and the fourth memory die to the substrate 103 using the bond wire (see Fig. 19A above).
Regarding claim 3, OH teaches the memory device of claim 1, further comprising a first pin pad (354 or 324) and a second pin pad (324 or 354) provided on the top surface of the first memory package 304, wherein: the first electrical connection extends from the first pin pad; and the second electrical connection extends from the second pin pad (see Fig. 18).
Regarding claim 4, OH teaches the memory device of claim 3, further comprising a redistribution layer electrically coupling the second memory die to the second pin pad (note the wiring layer/s that can be read as redistribution layer in Fig. 18).
Regarding claim 5, OH teaches the memory device of claim 1, wherein at least one of the first electrical connection, the second electrical connection, the third electrical connection and the fourth electrical connection is a bond wire (see Fig. 19A and note the bond wire/s).
Regarding claim 6, OH teaches the memory device of claim 1, wherein at least one of the first electrical connection, the second electrical connection, the third electrical connection and the fourth electrical connection is a bond pad (note any of the bond pads in Fig. 18-Fig. 19).
Regarding claim 7, OH teaches the memory device of claim 1, wherein the switch is a multiplexer (Para [0100 & 0104]).
Regarding claim 8, OH teaches the memory device of claim 1, further comprising a controller that provides a control signal to the switch, the control signal indicating which of the first memory die, the second memory die, the third memory die and the fourth memory die is electrically coupled to the substrate (Para [0016 & 0018 & 0028-0030]).
Regarding claim 9, OH teaches a semiconductor package, comprising:
a first semiconductor die 304a and a second semiconductor die 303a bonded together (Para [0272]) to form a first package (see Fig. 19 above);
a third semiconductor die 204a and a fourth semiconductor die 2063a bonded together (Para [0272]) to form a second package, the second package being stacked with the first package (see Fig. 19A above);
a switch (CBK, Fig. 6-7) electrically coupled to a top surface of the first package 304a;
a plurality of electrical connections electrically coupling the first semiconductor die 304a, the second semiconductor die 303a, the third semiconductor die 204a and the fourth semiconductor die 203a to the switch (see Fig. 18-19 and Fig. 6-7 and respective text); and
a bond wire electrically coupling the switch to a substrate 103 (note the bond wire connecting 304a to the substrate 103 in Fig. 19A).
Regarding claim 10, OH teaches the semiconductor package of claim 9, wherein the switch selectively electrically couples one of the semiconductor dies to the substrate 103 using the bond wire (Fig. 18-19).
Regarding claim 11, OH teaches the semiconductor package of claim 9, further comprising further comprising a first pin pad (354 or 334) and a second pin pad (334 or 354) provided on the top surface of the first memory package, wherein: the first electrical connection extends from the first pin pad; and the second electrical connection extends from the second pin pad (see Fig. 18-19).
Regarding claim 12, OH teaches the semiconductor package of claim 11, further comprising a redistribution layer electrically coupling the second memory die to the second pin pad (note the wiring layer that can be read as redistribution layer in Fig. 18).
Regarding claim 13, OH teaches the semiconductor package of claim 9, wherein at least one of the first electrical connection, the second electrical connection, the third electrical connection and the fourth electrical connection is a bond wire (Fig. 19A).
Regarding claim 14, OH teaches the semiconductor package of claim 9, wherein at least one of the first electrical connection, the second electrical connection, the third electrical connection and the fourth electrical connection is a bond pad (Fig. 19A).
Regarding claim 15, OH teaches the semiconductor package of claim 9, wherein the switch is a multiplexer (Para [0100 & 0104]).
Regarding claim 16, OH teaches the semiconductor package of claim 9, further comprising a controller that provides a control signal to the switch, the control signal indicating which of the first memory die, the second memory die, the third memory die and the fourth memory die is electrically coupled to the substrate (Para [0016 & 0018 & 0028-0030]).
Regarding claim 17, OH teaches a memory device, comprising:
a controller means (Para [0016 & 0018 & 0028-0030]);
a first semiconductor package having a first semiconductor die 304a bonded with (Para [0272]) a second semiconductor die 303a (see Fig. 19A below);
a second semiconductor package having a third semiconductor die 204a bonded with (Para [0272]) a fourth semiconductor die 203a, the second semiconductor package and the first semiconductor package arranged in a stacked configuration (see Fig. 19A below); and
a switching means (CBK, Fig. 6-7B) electrically coupled to the first semiconductor package and the second semiconductor package, the switching means selectively electrically coupling each of the first semiconductor die, the second semiconductor die, the third semiconductor die and the fourth semiconductor die to a substrate 103 of the memory device using a bond wire that electrically couples the switching means to the substrate 103 (see Fig. 18-19 and Fig. 6-7B and respective texts).
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Regarding claim 18, OH teaches the memory device of claim 17, wherein the switching means is electrically coupled to the first semiconductor package using a plurality of bond wires (Fig. 18-19A).
Regarding claim 19, OH teaches the memory device of claim 17, wherein the switching means is electrically coupled to the first semiconductor package using a plurality of bond pads (Fig. 18-19A).
Regarding claim 20, OH teaches the memory device of claim 17, wherein the switching means is a multiplexer Para [0100 & 0104]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818