Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 9-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/9/2026
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Niwa (US 20220005779 A1)
CLAIM 1, Niwa teaches a semiconductor device comprising: a wiring board [10+20+80] including a step (Step- 80+14) located at an outer peripheral part of the wiring board [10+20+80] (Fig. 12);
PNG
media_image1.png
430
732
media_image1.png
Greyscale
an adhesive 40 [40/41/42/43] provided on a surface of the wiring board (Fig. 12 & ¶[003
2]);
a semiconductor module 30 [30/31/32/33] disposed on an upper surface of the adhesive 40 (Figs. 12 & 1), the semiconductor module being mounted inward from the step of the wiring board (Figs. 12 & 1); and
a sealing member 91 covering the step 80, a side surface of the adhesive 40, and the semiconductor module 30, wherein the step includes a side surface 80 facing an outside of the wiring board, and a bottom surface 14 extending from a lower end of the side surface toward an end part of the wiring board (Figs. 12 & 1), and the side surface of the step and the side surface of the adhesive are positioned to overlap with one another in a view from a stacking direction of the adhesive and the semiconductor module (Fig. 1 – Note: At least adhesive layers 41 and 42 “overlap” the sidewall step 80. The language of the claim does not explicitly require the adhesive to be in “direct physical contact”, therefore under Broadest Reasonable Interpretation [BRI], the adhesives 41 and 42 adhering the overlying chips to the underlying surfaces meets the scope of the claimed subject matter.).
4. Niwa teaches a semiconductor device according to claim 1, wherein a surface roughness of a bottom surface of the step is rougher than a mounting surface of the wiring board (Note: the claim does not provide a explicit definition for the scale of “roughness”. Fig. 1 of Niwa demonstrate as smooth flat surface for the mounting surface S, while having etched openings for contact pads 10, demonstrating a “rougher” surface.).
CLAIM 5. Niwa teaches a semiconductor device according to claim 1, wherein the semiconductor module includes multiple semiconductor chips stacked in the stacking direction (Niwa, Figs. 1 & 12).
CLAIM 8. Niwa teaches a semiconductor device according to claim 1, wherein the semiconductor module includes a single semiconductor chip (Niwa, Fig. 12).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Niwa (US 20220005779 A1) in view of Chen et al. (US 20210225727 A1).
CLAIM 2. . Niwa teaches a semiconductor device according to claim 1, however may be silent upon wherein the sealing member is a metal-containing film, and the sealing member includes a drawn part extending outward from a side surface of the sealing member in a view from the stacking direction.
Niwa, as applied to claim 1, demonstrates sealing with a molding/encapsulating material, however at the time of the invention it was known to enhance chip-scale packages with metallic components to improve thermal management and EMI shielding.
Chen teaches two relevant configurations for a metal-containing sealing member:
1) The Lid:
Chen teaches a metal lid 420 (see Chen FIG. 3E and ¶ [0057]) mounted over the device. The lid includes a vertical and lateral extension that reaches outward and downward to contact the substrate/wiring layer 300, creating an enclosed accommodating space. Substrate/wiring board layer 300 forms a step shape with the wiring board sidewall UF.
2) The Conformal Film:
Chen further teaches a metal layer MX1-B (see Chen FIG. 3E and para [0050]) formed in direct contact with an encapsulation material 108'. This film includes a peripheral portion that extends outward from the side surface of the stack to interface with lower wiring levels.
It would have been obvious to a person of ordinary skill in the art at the time of the invention to modify the device of Niwa by providing a metal-containing film over the stack in either of the manners taught by Chen.
1) Motivation for Lid: A PHOSITA would be motivated to use the lid 420 of Chen to provide improved mechanical protection, thermal dissipation, electromagnetic shielding and/or hermetic seal over the Niwa stack, with the drawn part serving as the necessary structural bridge to contact the lower stepped wiring layer for grounding or heat sinking (Chen - ¶s[0049-59]).
2) Motivation for Conformal Film: Alternatively, a PHOSITA would be motivated to apply a metal layer MX1-B directly to the Niwa encapsulation (as seen in Chen) to achieve a lower-profile package while still providing EMI shielding and/or thermal conductivity/dissipation. In this structure, the metal layer contacts the and covers an analogous “step” shape at a periphery of the wiring board. The step shape is formed between the sidewall of the layers 120 and upper surface of the wiring layer UF, meeting the scope of the claimed subject matter.
The result of either modification is the predictable result providing a conventional metal containing sealing member with a outward-extending stepped wiring board. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the sealing parts of Niwa with to further include metal containing sealing parts, since applying a known technique to a known device ready for improvement to yield predictable results is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
CLAIM 3. . Niwa in view of Chen et al. teaches a semiconductor device according to claim 2, wherein the wiring board is provided with a ground wire at a predetermined depth, and the drawn part covers the ground wire exposed on the bottom surface of the step (Implicitly required when applying metal sealing layers/structures.).
Chen teaches that the lid 420 is bonded to the substrate via a conductive adhesive 430 [¶0057] It was well known a t the time of the invention that using a conductive adhesive to mount a metal lid serves to ground the structure for EMI shielding. To function, this conductive path requires a corresponding ground wire of plane located at a predetermined depth within the wiring board/substrate. Therefore, providing a grounded connection point at the lid’s/metal layer’s attachment sites a predictable and necessary structural requirement for the device taught by Chen. Therefore, modifying the device of Niwa as taught by Chen would be expected by a PHOSITA to be provided with a ground wire at a predetermined depth, and metal sealing part will contact and cover the ground wire exposed on the bottom surface of the step, in order to provide a properly grounded device structure.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Niwa (US 20220005779 A1) in view of Guo (US 20200066701 A1).
CLAIM 6. The semiconductor device according to claim 5, wherein the multiple semiconductor chips each include a semiconductor element provided on a surface of a corresponding one of the multiple semiconductor chips facing the wiring board, the semiconductor element being connected to the wiring board by a wire (Niwa Figs. 1 & 12).
The claim as a presented does not explicitly define what part of the chip is “facing”. Chips are understood to be capable of having active surfaces on either sides, thus simply reciting “facing” does not provide a clear and explicit distinction, thus may be open to interpretation. For the purpose of compact prosecution, the limitation as interpreted in light of the Applicant’s figures is also addressed in view of Guo.
Guo demonstrates in figure 1 wire bonding pads located on a surface of the chips may be “facing” a underlying wiring board. Stacking and orientating chips in this direction is a known arrangement used to shorten the wiring path to the interposer to improve speed, operation, resistance, or other known conventional benefits of shorter wiring.
PNG
media_image2.png
528
710
media_image2.png
Greyscale
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the stacking arrangement facing direction of Niwa with orientations as demonstrated in Gou, since applying a known technique to a known device ready for improvement to yield predictable results is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Niwa (US 20220005779 A1) in view of Huang et al. (US 20140183755 A1).
CLAIM 7. The semiconductor device according to claim 5, however is silent upon the capability of wherein the multiple semiconductor chips are connected to each other by a through-silicon via.
Niwa teaches the use of wire bonding to connect the chip and the wiring board. Huang et al. teaches TSVs were a known functionally equivalent alternative for the same purpose of providing connections between stacked chips and lower wiring boards, routinely practiced in the art by a PHOSITA at the time of the invention.
Huang teaches analogous stacked chips on a wiring board having a stepped profile. As shown in figure 2C, chips 10 and 19 may be connected via TSVs. Further note the teaching in paragraph [0014], chips are known to include “TSVs.”
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the chip connections of Niwa with known TSV connections as taught by Huang, since simple substitution of one known element for another to obtain predictable results (chip/device stacking for more complex/larger integrated devices) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JARRETT J. STARK
Primary Examiner
Art Unit 2822
3/9/2026
/JARRETT J STARK/ Primary Examiner, Art Unit 2898