DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 02/11/2026.
Claims 1-25 are pending in this application.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statements (IDS) filed on 09/08/2023, 09/18/2023, and 02/11/2026. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Specification
3. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112:
(a) IN GENERAL.— The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
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(b) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
5. Claim 13 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention.
In claim 13, the limitation “the metallization portion block” is not clearly defined, and the claim does not distinctly points out the subject matter which is claimed as the Applicant’s invention. It is unclear of where or how the claimed “the metallization portion block” structurally relates to other structures or elements of the package. The claim is therefore indefinite.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claims 1-12, and 14-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2022/0310577)
Regarding claim 1, Lee discloses a package comprising:
a package substrate (shown in fig. 4B) comprising:
an encapsulated portion comprising:
a first interconnection portion block 200, 300 (or a first interconnection portion block 410&350S formed by portion of mold layer 410 proximately surrounding, and including, conductive structure 350S located between structures 200 and 300; note that since the instant claim language fails to specify or limit the boundary of an interconnection portion block, any portion of mold layer 410 that includes at least one electrical path through interconnect, such as portion of mold layer 410 proximately surrounding, and including at least one of conductive structures 350S, 350PG in fig. 4B of Lee, would meet the claimed limitation “interconnection portion block”; see also paras. 0042, 0049, 0080 of the pending specification);
a second interconnection portion block 700 (or a second interconnection portion block 410 & 350 formed by portion of mold layer 410 proximately surrounding, and including, conductive structure 350, 350S & 350PG located on the right side of structure 700), wherein the second interconnection portion block 700/410&350 is a different type of interconnection portion block from the first interconnection portion block 200/300/410&350S;
a plurality of pillar interconnects 280, 380, 780 (and/or pillar interconnects 115), wherein the plurality of pillar interconnects comprises:
a first plurality of pillar interconnects 280/380/115 coupled to the first interconnection portion block 200/300/410&350S; and
a second plurality of pillar interconnects 780/115) coupled to the second interconnection portion block 700/410&350 and
an encapsulation layer 410 encapsulating the first interconnection portion block 200/300/410&350S, the second interconnection portion block 700/410&350, and the plurality of pillar interconnects 280, 380, 780, 115;
a first metallization portion 110 or 120 coupled to a first surface of the encapsulated portion 410;
a second metallization portion 120 or 110 coupled to a second surface of the encapsulated portion 410; and
a bridge and/or an interposer 200, or 430 (or interposer disclosed at para. 0028); and
a first integrated device 610 and/or 60 coupled to the package substrate through a first plurality of solder interconnects 510, 520.
Regarding claim 2, Lee discloses the package of claim 1, wherein the first interconnection portion block 200/300/410&350S includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallization portion block or a die block comprising through substrate vias. See fig. 4B.
Regarding claim 3, Lee discloses the package of claim 1, wherein the second interconnection portion block 700/410& 350 includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallization portion block or a die block comprising through substrate vias. See fig. 4B.
Regarding claim 4, Lee discloses the package of claim 1, wherein the bridge 200 and/or the interposer are located in the encapsulated portion 410. See fig. 4B.
Regarding claim 5, Lee discloses the package of claim 1, wherein the first integrated device 610 or 60 is coupled to the first metallization portion 120 of the package substrate through the first plurality of solder interconnects 510. See fig. 4B.
Regarding claim 6, Lee discloses the package of claim 5, wherein the first integrated device 601 or 60 includes a first core and a second core, wherein a first electrical path for a first signal to the first core of the first integrated device comprises the first interconnection portion block 200/300/410&350S, and wherein a second electrical path for a second signal to the second core of the first integrated device comprises the second interconnection portion block 700/410&350. See fig. 4B.
Regarding claim 7, Lee discloses the package of claim 5, further comprising a second integrated device 60 or 610 coupled to the first metallization portion 200 of the package substrate through a second plurality of solder interconnects 520. See fig. 4B.
Regarding claim 8, Lee discloses the package of claim 7, wherein a first electrical path for a first signal to the first integrated device comprises the first interconnection portion block 200, and wherein a second electrical path for a second signal to the second integrated device 610 comprises the second interconnection portion block 700. See fig. 4B.
Regarding claim 9, Lee discloses the package of claim 7, wherein a first electrical path for a first signal between the second metallization portion 110 and the first integrated device 60 comprises interconnects from the first interconnection portion block 200, an interconnect 125 from the interposer 430, a pillar interconnect 280 from the first plurality of pillar interconnects 280/380/115, metallization interconnects 123 from the first metallization portion 120, and a first solder interconnect 520 from the first plurality of solder interconnects 520, and
wherein a second electrical path for a second electrical signal between the second metallization portion 110 and the second integrated device 610 comprises interconnects from the second interconnection portion block 700, another interconnect 125 from the interposer 430, a pillar interconnect 780 from the second plurality of pillar interconnects 780/115, other metallization interconnects 123 from the first metallization portion 120, and a second solder interconnect 510 from the second plurality of solder interconnects 510/520. See fig. 4B.
Regarding claim 10, Lee discloses the package of claim 1, further comprising a third interconnection portion block (a third interconnection portion block 410 & 350 formed by portion of mold layer 410 proximately surrounding, and including, conductive structure 350, 350S & 350PG located on the right side of structure 700) located in the encapsulated portion 410, wherein the plurality of pillar interconnects comprises a third plurality of pillar interconnects 115 coupled to the third interconnection portion block. See fig. 4B.
Regarding claim 11, Lee discloses the package of claim 10, wherein the first interconnection portion block includes a coreless substrate block 200 or 300, wherein the second interconnection portion block includes a cored substrate block 700, and wherein the third interconnection portion block includes a metallization portion block 350. See fig. 4B.
Regarding claim 12, Lee discloses the package of claim 10, wherein a first electrical path for a first electrical signal between the second metallization portion 110 and the first integrated device 60 comprises interconnects 250 from the first interconnection portion block 200, an interconnect 125 from the interposer 430, a pillar interconnect 280 from the first plurality of pillar interconnects 280/380, first metallization interconnects 123 from the first metallization portion 120, and a first solder interconnect 520 from the first plurality of solder interconnects 510, 520,
wherein a second electrical path for a second electrical signal between the second metallization portion 110 and the first integrated device 610 comprises interconnects 750 from the second interconnection portion block 700, another interconnect 125 from the interposer 430, a pillar interconnect 780 from the second plurality of pillar interconnects 780/115, second metallization interconnects 123 from the first metallization portion 120, and a second solder interconnect 510 from the first plurality of solder interconnects 510, 520, and
wherein a third electrical path for a third electrical signal between the second metallization portion 110 and the first integrated device 60 comprises interconnects 350S, 350PG from the third interconnection portion block 350, another interconnect from the interposer 125, a pillar interconnect 115 from the third plurality of pillar interconnects, third metallization interconnects 125 from the first metallization portion 120, and a third solder interconnect 520 from the first plurality of solder interconnects. See fig. 4B.
Regarding claim 14, Lee discloses the package of claim 1, wherein a first electrical path for a first electrical signal between the second metallization portion 110 and the first integrated device 610/60 comprises interconnects from the first interconnection portion block 200/300/410&350S, an interconnect 125 from the interposer 430, a pillar interconnect 280 from the first plurality of pillar interconnects, metallization interconnects 123 from the first metallization portion 120, and a first solder interconnect 520 from the first plurality of solder interconnects, and
wherein a second electrical path for a second electrical signal between the second metallization portion 110 and the first integrated device 610/60 comprises interconnects from the second interconnection portion block 700/410&350, another interconnect 125 from the interposer 430, a pillar interconnect 780/115 from the second plurality of pillar interconnects, other metallization interconnects 123 from the first metallization portion 120, and a second solder interconnect 510/520 from the first plurality of solder interconnects. See fig. 4B.
Regarding claim 15, Lee discloses the package of claim 1, wherein a first electrical path for a first electrical signal between the second metallization portion 110 and the first integrated device 610/60 comprises interconnects from the first interconnection portion block 200/300/410&350S, an interconnect 125 from the interposer 430, a pillar interconnect 280/380/115 from the first plurality of pillar interconnects, metallization interconnects 123 from the first metallization portion 120, and a first solder interconnect 510/520 from the first plurality of solder interconnects, and
wherein a second electrical path for power between the second metallization portion 110 and the first integrated device 610/60 comprises interconnects from the second interconnection portion block, another interconnect from the interposer, a pillar interconnect from the second plurality of pillar interconnects, other metallization interconnects from the first metallization portion, and a second solder interconnect from the first plurality of solder interconnects. See fig. 4B.
Regarding claim 16, Lee discloses the package of claim 1, further comprising a second integrated device 60 or 610 coupled to the package through a second plurality of solder interconnects. See fig. 4B.
Regarding claim 17, Lee discloses the package of claim 16, wherein the first integrated device 610 is a first chiplet comprising a first technology node, and wherein the second integrated device 60/620 is a second chiplet comprising a second technology node. See fig. 4B.
Regarding claim 18, Lee discloses the package of claim 1, wherein the bridge 200 includes a silicon bridge and bridge interconnects. See para. 0038, and fig. 4B.
Regarding claim 19, Lee discloses the package of claim 1, further comprising: a second encapsulated portion 420 coupled to the first metallization portion 120; and a third metallization portion 625-627 coupled to the second encapsulated portion. See fig. 4B.
Regarding claim 20, Lee discloses the package of claim 19, wherein the bridge and/or the interposer 430 is located at least partially in the second encapsulated portion 420. See fig. 4B.
Regarding claim 21, Lee discloses the package of claim 19, further comprising a second integrated device 60/620 coupled to the package substrate through a second plurality of solder interconnects 520. See fig. 4B.
Regarding claim 22, Lee discloses the package of claim 21, wherein an electrical path between the first integrated device 610 and the second integrated device 60/620 includes the bridge 200. See fig. 4B.
Regarding claim 23, Lee discloses the package of claim 21, wherein a first electrical path between the first integrated device 610 and the second metallization portion 120/110 includes the interposer 430 and the first interconnection portion block, and wherein a second electrical path between the second integrated device 60/620 and the second metallization portion includes the interposer 430 and the second interconnection portion block. See fig. 4B.
Regarding claim 24, Lee discloses the package of claim 19, wherein the bridge 200 and/or the interposer 430 touches the third metallization portion. See fig. 4B.
Regarding claim 25, Lee discloses the package of claim 1, wherein the package is implemented in a device is that is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle. See para. 0052.
Conclusion
8. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 March 13, 2026