DETAILED ACTION
This Office action responds to Applicant’s election filed on 01/07/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-33. Claims 11-12, 17, and 24-33 were cancelled through the preliminary amendment when the instant application was filed.
Election/Restriction
The Applicant’s response on 01/07/2026 in reply to the restriction/election requirements mailed on 11/07/2025 has been entered. Applicant’s election without traverse of Species 7 corresponding to figs. 7A-7D, drawn to claims 1-7, 10, and 13-16, and 18-23, is acknowledged. Examiner agrees. Claims 8-9, are withdrawn by the Applicant, as being drawn to non-elected species.
Claims 11-12, 17 and 24-33 were cancelled by the Applicant through the preliminary amendment when the instant application was filed.
Claims 8-9 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/07/2026.
Information Disclosure Statement (IDS)
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Specification Objection
The specification has been checked to the extend necessary to determine the presence of possible minor errors. However, the Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 5, 7, 13-14, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Seko (US 2002/0043704) in view of Yanagisawa (US 2008/0237815).
Regarding claim 1, Seko shows (see, e.g., Seko: figs. 1-2, and annotated figs. 1-2) most aspects of the instant invention including a semiconductor structure, comprising:
A base film 11 including peripheral regions and an inner region disposed between the peripheral regions
The peripheral regions extending in a longitudinal direction and the inner region extending in the longitudinal direction
A unit film package disposed on the inner region of the base film 11 and defined by a cut line
Dummy patterns 19 disposed on the peripheral regions of the base film 11 and disposed between the cut line and opposite ends of the base film 11 in the width direction
A first solder resist layer 18 disposed on the base film 11
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However, Seko fails (see, e.g., Seko: figs. 1-2, and annotated figs. 1-2) to show that a first solder resist layer 18 is disposed on the base film 11. Seko also shows that a sealing resin layer 18 is disposed on the base film 11. Yanagisawa, in a similar device to Seko, teaches (see, e.g., Yanagisawa: fig. 1) that a solder resist layer 5 is disposed on the base film 1 (see, e.g., Yanagisawa: par. [0034]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either sealing resin layer of Seko or the solder resist layer of Yanagisawa because these were recognized in the semiconductor art for their use as protection layer in semiconductor device packages, as taught by Seko and by Yanagisawa, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Seko in view of Yanagisawa shows:
The first solder resist layer 5 is covering the unit film package inside the cut line 51 (see, e.g., Yanagisawa: fig. 1)
The first solder resist layer 18 extends in the width direction and runs across the cut line and covers the dummy patterns 19 (see, e.g., Seko: figs. 1-2, and annotated figs. 1-2)
Regarding claim 2, Seko in view of Yanagisawa shows (see, e.g., Seko: figs. 1-2, and annotated figs. 1-2) that:
A second solder resist layer 18 disposed on the inner region of the base film 11 and spaced apart in the longitudinal direction from one side of the cut line
wherein:
The second solder resist layer 18 extends in the width direction toward the peripheral regions and is connected to the first solder resist layer 18
Regarding claim 3, Seko in view of Yanagisawa shows (see, e.g., Seko: figs. 1-2, and annotated figs. 1-2) that:
The second solder resist layer 18 is provided in plural
The plurality of second solder resist layers 18 are spaced apart in the longitudinal direction from opposite ends of the cut line
Regarding claim 5, Seko in view of Yanagisawa shows (see, e.g., Seko: figs. 1-2, and annotated figs. 1-2) that the first solder layer 18 and the second solder layer 18 are connected to each other and constitute a single layer.
Regarding claim 7, Seko in view of Yanagisawa shows (see, e.g., Yanagisawa: fig. 1) that:
The base film 1 includes sprocket holes 2 on the peripheral regions and is arranged at a regular interval in the longitudinal direction
The first solder resist layer 5 is spaced apart in the width direction from the sprocket holes 2
Regarding claim 13, Seko shows (see, e.g., Seko: figs. 1-2, and annotated figs. 1-2) most aspects of the instant invention including a semiconductor structure, comprising:
A base film 11 that extends in a first direction and includes a first peripheral region, an inner region, and a second peripheral region that are arranged in a second direction orthogonal to the first direction
wherein:
The first peripheral region, the inner region, and the second peripheral region extends in the second direction
A unit film package disposed on the inner region of the base film 11 and defined by a cut line
A first dummy pattern 19 and a second dummy pattern 19 respectively provided on the first peripheral region and the second peripheral region of the base film 11
wherein:
Each of the first and second dummy patterns 19 is disposed between the cut line and one of opposite ends in the second direction of the base film 11
A first solder resist layer 18 disposed on the base film 11
However, Seko fails (see, e.g., Seko: figs. 1-2, and annotated figs. 1-2) to show that a first solder resist layer 18 is disposed on the base film 11. Seko also shows that a sealing resin layer 18 is disposed on the base film 11. Yanagisawa, in a similar device to Seko, teaches (see, e.g., Yanagisawa: fig. 1) that a solder resist layer 5 is disposed on the base film 1 (see, e.g., Yanagisawa: par. [0034]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either sealing resin layer of Seko or the solder resist layer of Yanagisawa because these were recognized in the semiconductor art for their use as protection layer in semiconductor device packages, as taught by Seko and by Yanagisawa, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Seko in view of Yanagisawa shows:
The first solder resist layer 5 is covering the unit film package inside the cut line 51 (see, e.g., Yanagisawa: fig. 1)
A second solder resist layer 18 that covers the first dummy pattern 19 on the first peripheral region of the base film 11 (see, e.g., Seko: figs. 1-2, and annotated figs. 1-2)
A third solder resist layer 18 that covers the second dummy pattern 19 on the second peripheral region of the base film 11 (see, e.g., Seko: figs. 1-2, and annotated figs. 1-2)
wherein:
The second solder resist layer 18 and the third solder resist layer 18 are connected to each other through a first extension part that is spaced apart in the first direction from the cut line and extends in the second direction to connect the second solder resist layer 18 to the third solder resist layer 18
Regarding claim 14, Seko in view of Yanagisawa shows (see, e.g., Seko: figs. 1-2, and annotated figs. 1-2) that a second extension part that extends in a direction that is opposite to the first direction and connects the second solder resist layer 18 to the third solder resist layer 18.
Regarding claim 18, Seko in view of Yanagisawa shows (see, e.g., Yanagisawa: fig. 1) that the base film 1 includes sprocket holes 2 on the peripheral regions and is arranged at a regular interval in the first direction, and the first solder resist layer 5 is spaced apart in the second direction from the sprocket holes 2.
Allowable Subject Matter
Claim 23 is allowed.
Claims 4, 6, 10, 15-16, and 19-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814