DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Remarks
Applicant’s arguments, filed 07/23/2026, with respect to the rejection(s) of claim(s) 1, 14-20, 22 and 23 under 35 U.S.C. 102 (a)(1) as being anticipated by Chen (US Publication No. 2020/0135708 have been fully considered and are persuasive. And the Applicant’s arguments, filed 07/23/2026, with respect to the rejection(s) of claim(s) 2-13, 21 and 24 under 35 U.S.C. 103 as being unpatentable over Chen, or Chen in view of Shen (U.S. Publication No. 2013/0193575) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Tu et al. (US 12165966) herein referred to as Tu.
Examiner acknowledges reference character (110) added to Specification. No new matter has been added. The drawing objection is withdrawn.
Claim Objections
Claim 8 is objected to because the numbering of claims is not in accordance with 37 CFR 1.126 which requires the original numbering of the claims to be preserved throughout the prosecution. When claims are canceled, the remaining claims must not be based on a cancelled claim. The Applicant has based claim 8 on cancelled claim 5. In order to advance prosecution, the Examiner assumes claim 8 depends from claim 1. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 14 -15, 17-20 and 22 -23 is/are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Tu et al. (US 12165966) herein referred to as Tu. (Fig. 2J, 6)
As to claim(s) 1, Tu teaches an assembly for fabricating a packaged module ([col 6 lines 61-67 and col 7, 1-10] package structure 100a), the assembly comprising:
a packaging substrate ([col 7, lines 10-15] package substrate 10) having a surface;
an array of conductive pads ([col 7, lines 10-15] conductive pad 20) implemented on the surface;
each conductive pad having one or more lateral dimensions (See Fig. 6);
a conductive post ([col 7, lines 10-15] conductive vias (24), formed over each conductive pad (20), the conductive post including a first portion (Annotated Fig 6, 1st portion) having one or more lateral dimensions formed over the conductive pad (20) and
a second portion (Annotated Fig 6, 2nd portion) having one or more lateral dimensions formed over the first portion (Annotated Fig 6, 1st portion),
the largest lateral dimension of the first portion (Annotated 1st portion), less than the largest lateral dimension of the second portion (Annotated 2nd portion);
the largest lateral dimension of the corresponding conductive pad (20) less than the largest lateral dimension of the second portion (Annotated Fig 6, 2nd portion);
a dielectric layer ([col 3, lines 54-59] layers 26 + 22: “The dielectric layer 26 may be formed of a material the same as, or different from, the material of the organic layer 22b. In some embodiments, the interconnect structure 12, the passivation layer 22, and the dielectric layer 26 are formed to extend into the scribe lines SL.) implemented over the surface to cover the conductive pads (20) and surround the first portion (Annotated 1st portion), of each conductive post.
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As to claim(s) 14, Tu teaches the assembly of claim 1 wherein
the dielectric layer (26 + 22) is dimensioned to surround substantially all of the first portion (Annotated Fig 6, 1st portion) of each conductive post (24).
As to claim(s) 15, Tu teaches the assembly of claim 14 wherein
the dielectric layer (26 + 22) includes a surface that is substantially coplanar with a plane where the first portion (Annotated Fig 6, 1st portion) transitions to the second portion (Annotated Fig 6, 2nd portion) of the conductive post (24).
As to claim(s) 17, Tu teaches the assembly of claim 1 wherein
each conductive pad (20) is formed from copper. ([col 3 lines 7-9]” The conductive pads 20 may include aluminum (Al), copper (Cu), silver (Ag), gold (Au), nickel (Ni), tungsten (W), alloys thereof, and/or multi-layers thereof. .”)
As to claim(s) 18, Tu teaches the assembly of claim 1 wherein
each conductive post is formed from copper. ([col 3 lines 32-34]” The conductive vias 24 may be formed of copper, aluminum, nickel, alloys thereof, and/or multi-layers thereof.”)
As to claim(s) 19, Tu teaches the assembly of claim 1 further comprising
a seed layer implemented between the surface and each conductive pad. ([col 3 line 34-36], “In some embodiments, a seed layer (not shown) is formed over, and extending into the openings of, the organic layer 22b. .”)
As to claim(s) 20, Tu teaches the assembly of claim 1 further comprising
a protective layer implemented to cover exposed portions of each conductive post. (col 6 lines 12-13 “an encapsulant 60 may be formed on the device dies 50A and 50B.”)
As to claim(s) 22, Tu teaches the assembly of claim 1 further comprising
one or more conductive traces (([col 6 lines 40-41] RDL may include metal trace) formed on the surface, at least one conductive trace being routed through a region between a pair of neighboring conductive pads ([col 6 lines 37-42] “The RDLs 70 may be formed to electrically couple to the conductive vias 24 and the electrical connectors (if there is any), and may interconnect the conductive vias 24 and the electrical connectors. The RDLs 70 may include metal traces (metal lines) and vias underlying and connected to the metal traces”).
As to claim(s) 23, Tu teaches the assembly of claim 1 wherein
the packaging substrate further includes another surface opposite from the surface, the other surface configured to allow mounting of one or more components thereon, such that a packaged module having the assembly is a dual-sided module. (col 6 lines 1-11 “ As shown in FIG. 2F, each of the device dies 50A and 50B is adhered in a package regions I′ and II′. In other embodiments, more device dies may be adhered in one region. Electrical connectors (not shown) may be formed before adhering the device dies 50A and 50B to the release layer 42. It is appreciated that the packaging is performed at the wafer level, and although the device dies 50A and 50B are illustrated, a plurality of device dies may be placed over the carrier 40, wherein the plurality of the placed device dies are arranged as an array including a plurality of rows and a plurality of columns.”)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. All obviousness rationales stated below are rationales that would have been obvious prior to the earliest effective filing date of the application.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-4, 8-9, 12 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tu et al. (US 12165966) herein referred to as Tu. (Fig. 2I, 11A and 11B)
As to claim(s) 2, Tu teaches the assembly of claim 1 wherein
the array of conductive pads (20) is arranged so that the corresponding conductive posts (24) allow mounting (obvious) of a packaged module having the assembly on a circuit board.
Tu does not appear to expressly disclose " a packaged module having the assembly on a circuit board." However, electrical connectors (74) in Fig. 2I and described in [col 6 lines 51-60] “Electrical connectors 74 may be formed on UBMs 72. The formation of the electrical connectors 74 may include placing solder balls over RDLs 70 and then reflowing the solder balls. ”, is a type of surface-mount packaging designed specifically to connect integrated circuits (ICs), such as processors, permanently to a circuit board (PCB).
Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the array of electrically conductive pads arranged to provide an inner region configured to allow mounting of a component on the surface of the Tu device so as to use an industrially tested and accepted device creating electrical, thermal, and mechanical connections of components.
As to claim(s) 3, Tu teaches the assembly of claim 2 wherein
the array of conductive pads (20) is arranged to provide an inner region configured allow mounting (obvious) of a component on the surface.
Tu does not appear to expressly disclose " the array of conductive pads is arranged to provide an inner region configured allow mounting of a component on the surface." However, conductive pads are placed on the inner region of a module (or PCB) primarily to enable high-density component placement (such as with Ball Grid Array (BGA) components) by allowing via-in-pad techniques. They also provide vital, direct electrical connections for power, improved signal integrity for high-speed circuits, and essential thermal dissipation.
Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to arrange the array of conductive pads so as to provide an inner region configured to allow mounting of a component on the surface of the Tu device so as to use an industrially tested and accepted device ensuring efficiency, and a compact design.
As to claim(s) 4, Tu teaches the assembly of claim 3 wherein
each conductive post (24) has a height dimension selected to provide a volume about the inner region, the volume having a height sufficiently large (obvious) to accommodate the component when the package module with the assembly is mounted on the circuit board.
Tu does not appear to expressly disclose "each conductive post has a height dimension selected to provide a volume about the inner region, having a height sufficiently large to accommodate the component when the package module with the assembly is mounted on the circuit board.” However, each conductive post (24) in Fig. 2I and described in [col 6 lines 51-60] is a part of “a plurality of metal posts or metal pillars formed between the redistribution layer (70) and the connectors (74) which are electrically connected to the connectors (24) of the two dies 50A and 50B through the interconnect structure (12).” Large conductive posts in the inner regions of electronic modules are designed to handle high current densities, dissipate significant heat, and ensure mechanical stability in densely packed areas.
Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the volume of the posts have a height sufficiently large enough to accommodate the component when the package module with the assembly is mounted on the circuit board of the Tu device, so as to use an industrially tested and accepted device creating electrical, thermal, and mechanical connections.
As to claim(s) 8, Tu teaches the assembly of claim 5 wherein
the increased lateral region between the neighboring conductive pads (Fig. 2I, Annotated lateral region increase) is sufficiently large (obvious) to allow routing of a conductive trace therethrough
Tu does not appear to expressly disclose " the increased lateral region between the neighboring conductive pads (Fig. 2I) is sufficiently large to allow routing of a conductive trace therethrough”. However, as shown in Fig. 2I, the neighboring conductive pads of dies 50A/50B is sufficiently large to allow routing of a conductive trace therethrough.
Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make an increased lateral region between the neighboring conductive pads sufficiently large to allow routing of a conductive trace therethrough the Tu device, so as to use an industrially tested and accepted device in the fan out package structure.
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As to claim(s) 9, Tu teaches the assembly of claim 3 wherein
at least two of the conductive posts (Fig 2I, 24) are electrically ([col 7 lines 16-19 “The conductive vias 24 may be disposed over the interconnect structure 12, and electrically coupled to the interconnect structure 12 through an underlying conductive pad 20”) connected through their respective conductive pads (Fig. 2I, pad 20).
As to claim(s) 12, Tu teaches the assembly of claim 3 wherein
the array of conductive pads includes the conductive pads being arranged to form a perimeter around the inner region (obvious to protect transistors)
Tu does not appear to expressly disclose” the conductive pads being arranged to form a perimeter around the inner region”. However, arranging conductive pads in an array that forms a perimeter around an inner region—often called a peripheral array or "pad frame"—is a standard layout technique designed to optimize electrical connection, structural integrity, and thermal management. Arranging pads around the perimeter acts as a strategic placement to manage stress, especially on flexible electronics, ensuring the inner sensitive area is not distorted.
Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to arrange the conductive pads being to form a perimeter around the inner region of the Tu device, so as to use an industrially tested and accepted device, defining a border which secures components to the board and protects against fatigue.
As to claim(s) 24, Tu teaches the assembly of claim 23 wherein
the packaging substrate is implemented as a laminate substrate (obvious) having a plurality of layers, and the surface is on an underside of the laminate substrate when the dual-sided module having the assembly is mounted on a circuit board.
Tu does not appear to expressly disclose "a laminate substrate." However, a laminate substrate is a layered composite material used as a base for electronic components, providing structural support and electrical connections. Laminate substrates are widely used in semiconductor packaging to provide cost-effective, high-density, and mechanically robust foundations that connect delicate silicon chips to motherboards.
Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to use a laminate substrate in the Tu device so as to use an industrially tested and accepted cost effective reliable device.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tu et al. (US 12165966) herein referred to as Tu in view of Shen, Hong (US 20130193575) herein referred to as Shen.
As to claim(s) 21, Tu teaches the assembly of claim 20 wherein
the protective layer includes an organic solderability preservative coating or a nickel/gold coating.
Tu does not appear to expressly disclose " the protective layer includes an organic solderability preservative coating or a nickel/gold coating ". Organic Solderability Preservatives (OSP) are used as a semiconductor and PCB protectant layer primarily to prevent copper oxidation, ensure excellent solderability, and provide a flat, cost-effective, and eco-friendly surface finish. Shen in [0090] discloses the protective layer (108) is an organic solder preservative (OSP)”.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the protective layer of the Tu device include an organic solderability preservative coating, such as is used in the Shen device. OSP is especially favored in consumer electronics and IC packaging substrates because it offers a cost-effective, flat surface that resists thermal shocks so as to use an industrially tested and accepted device.
Conclusion
THIS ACTION IS MADE FINAL. Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN SHAW MUSLIM whose telephone number is (571)270-0071. The examiner can normally be reached Mon-Fri 7 am - 4 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on (571) 272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897
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