DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 12/27/2023, is/are in compliance with the provisions 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group I (claims # 1-24 ), drawn to an assembly having a surface and an array of conductive pads implemented on the surface in the reply filed on 02/09/2026, is acknowledged.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: Component (110) is shown in Figs. 2, 4A, 4B, and 4C but is not mentioned in the Specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 14 -20, and 23 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chen, Wei-Yu et al. (US 20200135708) herein referred to as Chen. (Fig. 1D, 1J)
As to claim(s) 1, Chen teaches an assembly for fabricating a packaged module ([0057] package structure 50a), the assembly comprising:
a packaging substrate ([0012] package substrate 13) having a surface;
an array of conductive pads ([0012] pad 16) implemented on the surface;
a conductive post ([0021] conductive pillars (22), formed over each conductive pad ([0012] pad 16), the conductive post including a first portion ([0026] “the conductive pillar 22 includes a first portion P1”) having a lateral dimension formed over the conductive pad ([0012] pad 16) and
a second portion ([0026] the conductive pillar 22 includes a second portion P2) having a lateral dimension formed over the first portion (1st portion P1, Fig 1D),
the lateral dimension of the first portion (1st portion P1, Fig 1D), less than the lateral dimension of the second portion(2nd portion P1, Fig 1D),; and
a dielectric layer ([0016] passivation layer 17) implemented over the surface to cover the conductive pads ([0012] pad 16) and surround the first portion (1st portion P1, Fig 1D), of each conductive post.
As to claim(s) 14, Chen teaches the assembly of claim 1 wherein
the dielectric layer (Fig. 1J [0016] passivation layer 17) is dimensioned to surround substantially all of the first portion ([0016] passivation layer 17) of each conductive post (conductive pillar 22).
As to claim(s) 15, Chen teaches the assembly of claim 14 wherein
the dielectric layer (Fig. 1J [0016] passivation layer 17) includes a surface that is substantially coplanar with a plane where the first portion (Fig. 1D, P1) transitions to the second portion (Fig. 1D, P2) of the conductive post (conductive pillar 22).
As to claim(s) 16, Chen teaches the assembly of claim 14 wherein
the dielectric layer ([0016] passivation layer 17) includes a solder resist material or a prepreg material. ([0016]” The passivation layer 17 includes an insulating material such as silicon oxide, silicon nitride, polymer, or a combination thereof. The polymer is, for instance, polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof, or the like can act as the solder mask/resist in Redistribution Layer (RDL) structures. Si3N4 is a hard passivation layer often applied beneath the final solder mask or used for moisture protection)
As to claim(s) 17, Chen teaches the assembly of claim 1 wherein
each conductive pad is formed from copper. ([0015]” The material of the pads 16 may include metal or metal alloy, such as aluminum, copper, nickel, or alloys thereof.”)
As to claim(s) 18, Chen teaches the assembly of claim 1 wherein
each conductive post is formed from copper. ([0021]”The conductive pillars 22 may include copper, nickel, combinations thereof, or other suitable metal,…”)
As to claim(s) 19, Chen teaches the assembly of claim 1 further comprising
a seed layer implemented between the surface and each conductive pad. (Fig. 1J (19a), [0023] “a seed layer 19a underlying the conductive pillar 22 is formed.”)
As to claim(s) 20, Chen teaches the assembly of claim 1 further comprising
a protective layer implemented to cover exposed portions of each conductive post. (Polymer layer (PM1) serves as a protectant over the exposed parts of the conductive post. [0051] “[0051] The material of the polymer layer PM1, PM2, PM3, PM4 may be the same as or different from the material of the protection layer 27 of the die 30b, or the material of the encapsulant 31”)
As to claim(s) 23, Chen teaches the assembly of claim 1 wherein
the packaging substrate further includes another surface opposite from the surface, the other surface configured to allow mounting of one or more components thereon, such that a packaged module having the assembly is a dual-sided module. (Connectors (33) allow for mounting [0055] “The connectors 33 are electrically connected to the connectors 25a of the two dies 30b and 30c through the RDL structure 32.”)
Claim(s) 1 and 22 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chen, Wei-Yu et al. (US 20200135708) herein referred to as Chen. (Fig. 1D)
As to claim(s) 1, Chen teaches an assembly for fabricating a packaged module ([0057] package structure 50a), the assembly comprising:
a packaging substrate ([0012] package substrate 13) having a surface;
an array of conductive pads ([0012] pad 16) implemented on the surface;
a conductive post ([0021] conductive pillars (22), formed over each conductive pad ([0012] pad 16), the conductive post including a first portion ([0026] “the conductive pillar 22 includes a first portion P1”) having a lateral dimension formed over the conductive pad ([0012] pad 16) and
a second portion ([0026] the conductive pillar 22 includes a second portion P2) having a lateral dimension formed over the first portion (1st portion P1, Fig 1D),
the lateral dimension of the first portion (1st portion P1, Fig 1D), less than the lateral dimension of the second portion(2nd portion P1, Fig 1D),; and
a dielectric layer ([0016] passivation layer 17) implemented over the surface to cover the conductive pads ([0012] pad 16) and surround the first portion (1st portion P1, Fig 1D), of each conductive post.
As to claim(s) 22, Chen teaches the assembly of claim 1 further comprising
one or more conductive traces (Fig. 1D, 15) formed on the surface, at least one conductive trace (Fig. 1D, 15) being routed through a region between a pair of neighboring conductive pads (Fig. 1D, pad 16).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. All obviousness rationales stated below are rationales that would have been obvious prior to the earliest effective filing date of the application.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 – 13 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, Wei-Yu et al. (US 20200135708) herein referred to as Chen.
As to claim(s) 2, Chen teaches the assembly of claim 1 wherein
the array of conductive pads ([0012] pad 16) is arranged so that the corresponding conductive posts ([0021] conductive pillars (22) allow mounting (obvious) of a packaged module having the assembly on a circuit board.
Chen does not appear to expressly disclose " a packaged module having the assembly on a circuit board." However, a Ball Grid Array (BGA), (33) in Fig. 1J and described in [0055] “a plurality of connectors 33 are formed over and electrically connected to the redistribution layer RDL4 of the RDL structure 32”, is a type of surface-mount packaging designed specifically to connect integrated circuits (ICs), such as processors, permanently to a circuit board (PCB).
Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the array of conductive pads arranged to provide an inner region configured to allow mounting of a component on the surface of the Chen device so as to use an industrially tested and accepted device creating electrical, thermal, and mechanical connections of components.
As to claim(s) 3, Chen teaches the assembly of claim 2 wherein
the array of conductive pads ([0012] pad 16) is arranged to provide an inner region configured allow mounting (obvious) of a component on the surface.
Chen does not appear to expressly disclose " the array of conductive pads is arranged to provide an inner region configured allow mounting of a component on the surface." However, conductive pads are placed on the inner region of a module (or PCB) primarily to enable high-density component placement (such as with Ball Grid Array (BGA) components) by allowing via-in-pad techniques. They also provide vital, direct electrical connections for power, improved signal integrity for high-speed circuits, and essential thermal dissipation.
Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to arrange the array of conductive pads so as to provide an inner region configured to allow mounting of a component on the surface of the Chen device so as to use an industrially tested and accepted device ensuring efficiency, and a compact design.
As to claim(s) 4, Chen teaches the assembly of claim 3 wherein
each conductive post ([0021] conductive pillars (22) has a height dimension selected to provide a volume about the inner region, the volume having a height sufficiently large (obvious) to accommodate the component when the package module with the assembly is mounted on the circuit board.
Chen does not appear to expressly disclose "each conductive post has a height dimension selected to provide a volume about the inner region, having a height sufficiently large to accommodate the component when the package module with the assembly is mounted on the circuit board.” However, each conductive post (22) in Fig. 1J and described in [0055] is a part of “a plurality of metal posts or metal pillars formed between the redistribution layer RDL4 and the connectors 33 which are electrically connected to the connectors 25a of the two dies 30b and 30c through the RDL structure 32.” Large conductive posts in the inner regions of electronic modules are designed to handle high current densities, dissipate significant heat, and ensure mechanical stability in densely packed areas.
Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the volume of the posts have a height sufficiently large enough to accommodate the component when the package module with the assembly is mounted on the circuit board of the Chen device, so as to use an industrially tested and accepted device creating electrical, thermal, and mechanical connections.
As to claim(s) 5, Chen teaches the assembly of claim 3 wherein
a lateral dimension (Annotated conductive pad lateral dimension, W2)) of each of at least some of the conductive pads ([0012] pad 16) is less than the lateral dimension of second portion (second portion P2) of the respective conductive post (conductive pillars (22))
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As to claim(s) 6, Chen teaches the assembly of claim 5 wherein
the lateral dimension (Annotated Fig. 1D conductive pad lateral dimension) of the respective conductive pad ([0012] pad 16) being less than the lateral dimension (Annotated Fig. 1D conductive post lateral dimension) of the second portion (conductive pillar P2 of 22) of the respective conductive post results in a post pitch between neighboring conductive posts not being limited by a minimum lateral. separation distance (obvious) between the respective conductive pads.
Chen does not appear to expressly disclose “the lateral dimension of the respective conductive pad being less than the lateral dimension of the second portion of the respective conductive post results in a post pitch between neighboring conductive posts not being limited by a minimum lateral separation distance between the respective conductive pads.” However, as shown by the lateral dimension between posts and pads in Fig. 1J, the posts are the limiting factor between post and pad placement, not the pads. The conductive posts (or pillars) as the limiting factor in the lateral distance (pitch) between semiconductor posts, is primarily due to the need to circumvent challenges in photolithography, structural stability, and fabrication defects. As the posts become smaller to accommodate tighter spacing, the fabrication process becomes highly susceptible to defects, and the posts themselves become structurally weak.
Thus, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the posts of the Chen device, the limiting factor between post and pad placement, not the pads themselves so as to use an industrially tested and accepted device.
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As to claim(s) 7, Chen teaches the assembly of claim 6 wherein
the neighboring conductive posts (conductive pillar 22) having a post pitch similar to a comparable pair of conductive posts (conductive pillars 22), formed over respective conductive pads (pad 16) each having a lateral dimension (Fig. 1J, lateral dimension) larger than a lateral dimension of each comparable conductive post results in an increased lateral region between the neighboring conductive pads.
As to claim(s) 8, Chen teaches the assembly of claim 7 wherein
the increased lateral region between the neighboring conductive pads (Fig. 1J, Annotated lateral region increase) is sufficiently large (obvious) to allow routing of a conductive trace therethrough
Chen does not appear to expressly disclose " the increased lateral region between the neighboring conductive pads (Fig. 1J) is sufficiently large to allow routing of a conductive trace therethrough”. However, each conductive pad (16) in Fig. 1J and described in [0057] is a part of the package structure 50a providing the encapsulant 31, the RDL structure 32 and the connectors 33. The conductive trace can be routed between the two dies 30b and the die 30c and connected through to the RDL structure 32, in the ample space provided. Though not pictured in Fig.1J, the increased lateral region between the neighboring conductive pads of die 30b and 30c is sufficiently large to allow routing of a conductive trace therethrough.
Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the increased lateral region between the neighboring conductive pads sufficiently large to allow routing of a conductive trace therethrough of the Chen device, so as to use an industrially tested and accepted device in the fan out package structure.
As to claim(s) 9, Chen teaches the assembly of claim 3 wherein
at least two of the conductive posts (Fig 1J, conductive pillar 22) are electrically ([0057] “The connector 25a is in electrical contact with the pads 16) connected through their respective conductive pads (Fig. 1J, pad 16).
As to claim(s) 10, Chen teaches the assembly of claim 9 wherein
the at least two electrically-connected conductive posts include a pair of neighboring conductive posts, (obvious) such that an extended conductive pad form an electrically-connected pair of conductive pads for the pair of neighboring conductive posts ([0057]“The connector 25a is in electrical contact with the pads 16, and further electrically connected to the interconnection structure 15”)
Chen does not appear to expressly disclose “a pair of neighboring conductive posts” such that an extended conductive pad form an electrically-connected pair of conductive pads for the pair of neighboring conductive posts. However, modern semiconductor packages frequently contain duplicate components, particularly in high-density, multi-chip modules (MCMs), SiP (System-in-Package), and 3D stacking technologies. Stacking identical components is standard practice to increase capacity. Since it has been held that “mere duplication of parts has no patentable significance unless a new and unexpected result is produced” (See MPEP 2144.04(VI)(B)), the Chen device obviously meets the limitations of claim 10.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to include a pair of neighboring conductive posts form an electrically-connected pair of conductive pads for the pair of neighboring conductive posts of the Chen device. These techniques allow manufacturers to boost performance and storage within a limited footprint so as to use an industrially tested and accepted device.
As to claim(s) 11, Chen teaches the assembly of claim 9 wherein
the at least two electrically-connected conductive posts (conductive pillar 22) are electrically connected to ([0052] “The redistribution layer RDL2 penetrates through the polymer layer PM2 and is electrically connected to the redistribution layer RDL.”) or connectable to a ground node (obvious).
Chen does not appear to expressly disclose “the at least two electrically-connected conductive posts are connectable to a ground node.” However, grounding conductive posts (e.g., package leads, heat sinks, or bonding wires) in a semiconductor device is crucial to establish a stable reference potential, reduce electromagnetic interference (EMI), and prevent electric shock. Properly grounding conductive elements ensures charges do not build up, protecting sensitive components from ESD damage.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the conductive posts electrically connected to or connectable to a ground node of the Chen device so as to use an industrially tested and accepted device ensuring charges do not build up, and protecting sensitive components from ESD damage.
As to claim(s) 12, Chen teaches the assembly of claim 3 wherein
the array of conductive pads includes the conductive pads being arranged to form a perimeter around the inner region (obvious to protect transistors)
Chen does not appear to expressly disclose” the conductive pads being arranged to form a perimeter around the inner region”. However, arranging conductive pads in an array that forms a perimeter around an inner region—often called a peripheral array or "pad frame"—is a standard layout technique designed to optimize electrical connection, structural integrity, and thermal management. Arranging pads around the perimeter acts as a strategic placement to manage stress, especially on flexible electronics, ensuring the inner sensitive area is not distorted.
Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to arrange the conductive pads being to form a perimeter around the inner region of the Chen device so as to use an industrially tested and accepted device, defining a border which secures components to the board and protects against fatigue.
As to claim(s) 13, Chen teaches the assembly of claim 12 wherein
the array of conductive pads (Fig. 1D, Fig. 1J conductive pad 16) further includes additional conductive pads arranged in a section adjacent to a respective section of the perimeter. (Fig. 1D, Fig. 1J conductive pad 16)
As to claim(s) 24, the assembly of claim 23 wherein
the packaging substrate is implemented as a laminate substrate (obvious) having a plurality of layers, and the surface is on an underside of the laminate substrate when the dual-sided module having the assembly is mounted on a circuit board.
Chen does not appear to expressly disclose " a laminate substrate." However, a laminate substrate is a layered composite material used as a base for electronic components, providing structural support and electrical connections. [0070] discloses that the package structure 63 may be any kind of package structures according to the functional demand of the Package on Package (PoP) device 100. Laminate substrates are widely used in semiconductor packaging to provide cost-effective, high-density, and mechanically robust foundations that connect delicate silicon chips to motherboards.
Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to use a laminate substrate in the Chen device so as to use an industrially tested and accepted cost effective reliable device.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, Wei-Yu et al. (US 20200135708) herein referred to as Chen in view of Shen, Hong (US 20130193575) herein referred to as Shen.
As to claim(s) 21, Chen teaches the assembly of claim 20 wherein
the protective layer includes an organic solderability preservative coating or a nickel/gold coating.
Chen does not appear to expressly disclose " the protective layer includes an organic solderability preservative coating or a nickel/gold coating ". Organic Solderability Preservatives (OSP) are used as a semiconductor and PCB protectant layer primarily to prevent copper oxidation, ensure excellent solderability, and provide a flat, cost-effective, and eco-friendly surface finish. Shen in [0090] discloses the protective layer (108) is an organic solder preservative (OSP)”.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the protective layer of the Chen device include an organic solderability preservative coating, such as is used in the of the Shen device. OSP is especially favored in consumer electronics and IC packaging substrates because it offers a cost-effective, flat surface that resists thermal shocks so as to use an industrially tested and accepted device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN SHAW MUSLIM whose telephone number is (571)270-0071. The examiner can normally be reached Mon-Fri 7 am - 4 pm.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897