DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 02/09/2026 Amendment and RCE.
Claims 1-7, 10-15, 17 are pending and examined. Claims 8-9, and 16 have been cancelled.
Claim Rejections - 35 USC § 112
Claims 1-7, 10-15, 17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites limitations “or in a parallel transmission operation, the plurality of second circuits transmit the status information of all of the second circuits through the plurality of second parallel
input and output interfaces, and the first circuit obtains the status information of all of the second circuits through the first parallel input and output interface according to the read command of status information” on lines 17-21.
Specification describes, in paragraphs [0019] and [0022]:
“[0019] In detail, when the first circuit 110 needs to read the status information of the second circuits 120-1 to 120-N, the first circuit 110 may send related commands to the second circuits 120-1 to 120-N through the parallel input and output port IOP. Correspondingly, the second circuits 120-1 to 120-N may load status information thereof into a plurality of data shifters therein. Then, the first circuit 110 may transmit the read clock signal RE #to the second circuits 120-1 to 120-N, and make the multiple data shifters in the second circuits 120-1 to 120-N to shift out the stored status information to the data output port OUT[0] thereof according to the clock cycle of the read clock signal RE #.”
[0022] On the other hand, in an embodiment of the present disclosure, when the first circuit 110 only needs to read the status information of one of the second circuits 120-1 to 120-N, the relevant commands may be sent to the second circuits 120-1 to 120-N through the parallel input and output port IOP. The selected second circuit (one of the second circuits 120-1 to 120-N) may be notified through the transmitted data packet, so as to send the status information thereof to the first circuit 110 through the parallel input and output port IOP. In addition, when the first circuit 110 reads the status information of the selected second circuit through the parallel input and output port IOP thereof, the shifting operation of the status information of the second circuits 120-1 to 120-N may be prepared simultaneously. In this manner, the data input port IN[0] may be disconnected with the data output port OUT[0] of the second circuit 120-1.
Response to Arguments
Applicant's arguments filed 02/09/2026 have been fully considered. However, amendment to independent claims 1 and 12 have introduced new claim rejections under 35 USC § 112, first paragraph as stated above. As the result, there is art rejection applied to claims 1-7, 10-15, 17 in this Office Action.
Conclusion
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February 26, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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