Prosecution Insights
Last updated: April 19, 2026
Application No. 18/464,262

MULTI-CIRCUIT CONTROL SYSTEM AND READING METHOD FOR STATUS INFORMATION THEREOF

Non-Final OA §112
Filed
Sep 11, 2023
Examiner
NGUYEN, VAN THU T
Art Unit
2824
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Macronix International Co. Ltd.
OA Round
3 (Non-Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
2y 4m
To Grant
89%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
785 granted / 950 resolved
+14.6% vs TC avg
Moderate +7% lift
Without
With
+6.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
31 currently pending
Career history
981
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
44.8%
+4.8% vs TC avg
§102
33.2%
-6.8% vs TC avg
§112
14.5%
-25.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 950 resolved cases

Office Action

§112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action is in response to 02/09/2026 Amendment and RCE. Claims 1-7, 10-15, 17 are pending and examined. Claims 8-9, and 16 have been cancelled. Claim Rejections - 35 USC § 112 Claims 1-7, 10-15, 17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 recites limitations “or in a parallel transmission operation, the plurality of second circuits transmit the status information of all of the second circuits through the plurality of second parallel input and output interfaces, and the first circuit obtains the status information of all of the second circuits through the first parallel input and output interface according to the read command of status information” on lines 17-21. Specification describes, in paragraphs [0019] and [0022]: “[0019] In detail, when the first circuit 110 needs to read the status information of the second circuits 120-1 to 120-N, the first circuit 110 may send related commands to the second circuits 120-1 to 120-N through the parallel input and output port IOP. Correspondingly, the second circuits 120-1 to 120-N may load status information thereof into a plurality of data shifters therein. Then, the first circuit 110 may transmit the read clock signal RE #to the second circuits 120-1 to 120-N, and make the multiple data shifters in the second circuits 120-1 to 120-N to shift out the stored status information to the data output port OUT[0] thereof according to the clock cycle of the read clock signal RE #.” [0022] On the other hand, in an embodiment of the present disclosure, when the first circuit 110 only needs to read the status information of one of the second circuits 120-1 to 120-N, the relevant commands may be sent to the second circuits 120-1 to 120-N through the parallel input and output port IOP. The selected second circuit (one of the second circuits 120-1 to 120-N) may be notified through the transmitted data packet, so as to send the status information thereof to the first circuit 110 through the parallel input and output port IOP. In addition, when the first circuit 110 reads the status information of the selected second circuit through the parallel input and output port IOP thereof, the shifting operation of the status information of the second circuits 120-1 to 120-N may be prepared simultaneously. In this manner, the data input port IN[0] may be disconnected with the data output port OUT[0] of the second circuit 120-1. Response to Arguments Applicant's arguments filed 02/09/2026 have been fully considered. However, amendment to independent claims 1 and 12 have introduced new claim rejections under 35 USC § 112, first paragraph as stated above. As the result, there is art rejection applied to claims 1-7, 10-15, 17 in this Office Action. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. February 26, 2026 /VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
Read full office action

Prosecution Timeline

Sep 11, 2023
Application Filed
Jul 01, 2025
Non-Final Rejection — §112
Sep 03, 2025
Interview Requested
Sep 11, 2025
Applicant Interview (Telephonic)
Sep 11, 2025
Examiner Interview Summary
Oct 02, 2025
Response Filed
Nov 13, 2025
Final Rejection — §112
Jan 08, 2026
Response after Non-Final Action
Feb 09, 2026
Request for Continued Examination
Feb 17, 2026
Response after Non-Final Action
Feb 26, 2026
Non-Final Rejection — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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MEMORY DEVICE INCLUDING INTERFACE CIRCUIT AND METHOD OF OPERATING THE SAME
2y 5m to grant Granted Mar 31, 2026
Patent 12587418
MULTIPLEXING DISTINCT SIGNALS ON A SINGLE PIN OF A MEMORY DEVICE
2y 5m to grant Granted Mar 24, 2026
Patent 12573450
SRAM COLUMN SLEEP CIRCUITS FOR LEAKAGE SAVINGS WITH RAPID WAKE
2y 5m to grant Granted Mar 10, 2026
Patent 12573449
METHODS OF TESTING NONVOLATILE MEMORY DEVICES AND NONVOLATILE MEMORY DEVICES
2y 5m to grant Granted Mar 10, 2026
Patent 12567470
SYSTEM AND METHOD FOR DYNAMIC INTER-CELL INTERFERENCE COMPENSATION IN NON-VOLATILE MEMORY STORAGE DEVICES
2y 5m to grant Granted Mar 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
89%
With Interview (+6.6%)
2y 4m
Median Time to Grant
High
PTA Risk
Based on 950 resolved cases by this examiner. Grant probability derived from career allow rate.

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