Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 12, and 30-33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20230301101, hereafter ‘Lee’ in view of Fayrushin et al, US 20220238547, hereafter ‘Fayrushin’.
Regarding claim 1, Lee discloses : A semiconductor device comprising: a gate structure(Fig. 3A, #ST); a source structure that is disposed on the gate structure(#105); channel structures that extend into the source structure through the gate structure(#CH), wherein the channel structures comprise a channel layer and a memory layer surrounding the channel layer(Fig. 5, #140 and #142, respectively), the memory layer comprising a cut area that exposes the channel layer(#142 a part of #145 where #145 may be removed to expose a portion of #140 [0096]);
Lee does not disclose : a slit structure that extends into the source structure through the gate structure between the channel structures, an upper surface of the slit structure being disposed at a lower level than the cut area.
However, in the same field of endeavor, Fayrushin teaches : a slit structure(#116) that extends into the source structure(#124) through the gate structure(#108) between the channel structures(Fig. 2, #116 extending through #108 into #124 between #122), an upper surface of the slit structure being disposed at a lower level than the cut area(Fig. 7, a case where #702 is formed in a depth that does not extend wholly through #502 and only exposing a portion of #502 [0105] and Fig. 8, where #802 may be partially in #504 [0108]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Fayrushin to Lee to adjust a slit structure’s depth into a source structure, since it has been held that the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 101 USPQ 284 (CCPA 1954). See MPEP 2144.04.
Regarding claim 2, Lee as modified by Fayrushin discloses : The semiconductor device of claim 1.
Lee teaches : wherein the source structure is in contact with the channel layer through the cut area(#140 may be in contact with #102 [0049]).
Regarding claim 12, Lee as modified by Fayrushin: The semiconductor device of claim 1.
Lee teaches : further comprising a second semiconductor structure that is bonded to a first semiconductor structure(Fig. 10, #1 bonded to #2), wherein the first semiconductor structure comprises the gate structure, the source structure, the channel structures, and the slit structure(#2 to include #CH, #ST, #105 and #160), and wherein the second semiconductor structure comprises a peripheral circuit(#1 is a peripheral circuit [0027]).
Regarding claim 30, Lee as modified by Fayrushin discloses : The semiconductor device of claim 1.
Lee teaches : wherein heights of the channel structures are greater than a height of the slit structure and wherein the heights of the channel structures are measured from an upper surface of the gate structure opposite to the source structure(Fig. 5, #CH shown to penetrate #105 while Fig. 4, #160 shown to contact a top surface of #105).
Regarding claim 31, Lee as modified by Fayrushin discloses : The semiconductor device of claim 30.
Lee teaches : wherein a height of each of the channel structures, is measured including the channel layer and the memory layer(Fig. 5, #CH measured from top of #ST to bottom of #101).
Regarding claim 32, Lee as modified by Fayrushin discloses : The semiconductor device of claim 1.
Lee teaches : wherein the slit structure is in contact with the source structure(Fig. 4, #160 contacting #105).
Regarding claim 33, Lee as modified by Fayrushin discloses : The semiconductor device of claim 1.
Lee teaches : wherein the slit structure is in contact with the source structure(Fig. 3a, #CH disposed on same level in #105).
Claims 3-11 and 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20230301101, hereafter ‘Lee’ in view of Fayrushin et al, US 20220238547, hereafter ‘Fayrushin’ in further view of Lee et al, US 20230005954, hereafter ‘954’.
Regarding claim 3, Lee as modified by Fayrushin discloses : The semiconductor device of claim 1.
Lee as modified by Fayrushin does not disclose : wherein the channel structures comprise: a first channel structure comprising a first protruding part that protrudes into the source structure by a first height; and a second channel structure comprising a second protruding part that protrudes into the source structure by a second height.
However, in the same field of endeavor, 954 teaches : wherein the channel structures comprise: a first channel structure comprising a first protruding part that protrudes into the source structure by a first height; and a second channel structure comprising a second protruding part that protrudes into the source structure by a second height(Fig. 6, #CS1 and #CS3 having different depths into #100 where a source structure may be included on or in #100 [0060]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of 954 to Lee and Fayrushin to include channel structures that protrude into a source structure at different depths.
Regarding claim 4, Lee as modified by Fayrushin and 954 discloses : The semiconductor device of claim 3.
954 teaches : wherein the first height and the second height are different from each other(Fig.6, #CS1 and #CS3 having different heights).
Regarding claim 5, Lee as modified by Fayrushin and 954 discloses : The semiconductor device of claim 3.
Lee as modified by 954 teaches : wherein the source structure comprises: a first part that surrounds the first protruding part; a second part that surrounds the second protruding part; and a third part that is in contact with the first channel structure and the second channel structure and protrudes between the first part and the second part(Lee, Fig 5, #105 to include different layers #101, #102, and #103 with #103 surrounding a cut and #101 surrounding a protruding part. 954, Fig. 6, channel structures with protruding into #100 with different depths where a source structure in or on top of #100 [0060]).
Regarding claim 6, Lee as modified by Fayrushin and 954 discloses : The semiconductor device of claim 5.
Fayrushin teaches : wherein the third part comprises: a horizontal part that extends between the gate structure and the first part and between the gate structure and the second part; and a vertical part that protrudes between the first part and the second part and protrudes from the horizontal part(Fig. 2, a part of #124 below #116 and a part between #122 in a case where a slit for the slit structure of Fig. 7, where #702 is formed in a depth that does not extend wholly through #502 and only exposing a portion of #502 [0105] and Fig. 8, where #802 may be partially in #504 [0108]).
Regarding claim 7, Lee as modified by Fayrushin and 954 discloses : The semiconductor device of claim 5.
Fayrushin discloses : wherein the memory layer comprises: a first memory pattern that is disposed between the channel layer and the source structure; and a second memory pattern that is disposed between the channel layer and the gate structure, and wherein the cut area is defined between the first memory pattern and the second memory pattern(Fig. 1, #142 above #146 disposed between #106 and #142 below #146 disposed between #106 and #124).
Regarding claim 8, Lee as modified by Fayrushin and 954 discloses : The semiconductor device of claim 7.
Lee teaches : wherein the first part or the second part surrounds the first memory pattern(Fig. 5, #101 surrounds a bottom most part of #CH).
Regarding claim 9, Lee as modified by Fayrushin and 954 discloses : The semiconductor device of claim 5.
Lee teaches : wherein the third part is in contact with the channel layer(Fig. 5, #102 in contact with #140 [0096]).
Regarding claim 10, Lee as modified by Fayrushin and 954 discloses : The semiconductor device of claim 5.
Lee teaches : wherein the source structure further comprises a fourth part that is disposed between the third part and the gate structure(Fig. 5, #103 disposed between #ST and #102).
Regarding claim 11, Lee as modified by Fayrushin and 954 discloses : The semiconductor device of claim 5.
Lee teaches : further comprising a junction that is disposed within the channel layer of each of the channel structures having different heights(#192 to include #163 and #165 [0070]).
Regarding claim 34, Lee as modified by Fayrushin and 954 discloses : The semiconductor device of claim 7.
954 teaches : wherein the first memory pattern and the second memory pattern have different heights(The ends of #CS1 and #CS3 in #100 are at different depths).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : US 20230269938 : Cuts in memory cells in the source region.
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/D.T./Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897