Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Acknowledgment is made of the amendment filed 06/26/2026, in which: claim 1 is amended; claims 13-29 are cancelled; and the rejection of the claims are traversed. Claims 1-12 and 30-34 are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant’s arguments with respect to claims 1-12 and 30-34 have been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 12, and 30-33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20230301101 in view of Guo et al, US 20230269938.
Regarding claim 1, Lee discloses : A semiconductor device comprising: a gate structure(Fig. 3a, #ST); a source structure that is disposed on the gate structure(#105); channel structures that extend into the source structure through the gate structure(#CH), wherein the channel structures comprise a channel layer and a memory layer surrounding the channel layer(Fig. 5, #140 and #142), the memory layer comprising a cut area that is disposed within the source structure and exposes the channel layer(#142 a part of #145 where #145 may be removed to expose a portion of #140 [0096] disposed in #105).
Lee does not disclose : a slit structure that extends into the source structure through the gate structure between the channel structures, an upper surface of the slit structure being disposed between the gate structure and the cut area.
However, in the same field of endeavor, Guo teaches : a slit structure that extends into the source structure through the gate structure between the channel structures(Fig. 19, #350 extending into #330), an upper surface of the slit structure being disposed between the gate structure and the cut area(#350 between cut area and gate structure #240 and #340).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Guo to Lee to improve structural integrity of a three-dimensional memory device (Guo [0060-0061]).
Regarding claim 2, Lee as modified by Guo discloses : The semiconductor device of claim 1.
Lee teaches : wherein the source structure is in contact with the channel layer through the cut area(#140 may be in contact with #102 [0049]).
Regarding claim 12, Lee as modified by Guo: The semiconductor device of claim 1.
Lee teaches : further comprising a second semiconductor structure that is bonded to a first semiconductor structure(Fig. 10, #1 bonded to #2), wherein the first semiconductor structure comprises the gate structure, the source structure, the channel structures, and the slit structure(#2 to include #CH, #ST, #105 and #160), and wherein the second semiconductor structure comprises a peripheral circuit(#1 is a peripheral circuit [0027]).
Regarding claim 30, Lee as modified by Guo discloses : The semiconductor device of claim 1.
Lee teaches : wherein heights of the channel structures are greater than a height of the slit structure and wherein the heights of the channel structures are measured from an upper surface of the gate structure opposite to the source structure(Fig. 5, #CH shown to penetrate #105 while Fig. 4, #160 shown to contact a top surface of #105).
Regarding claim 31, Lee as modified by Guo discloses : The semiconductor device of claim 30.
Lee teaches : wherein a height of each of the channel structures, is measured including the channel layer and the memory layer(Fig. 5, #CH measured from top of #ST to bottom of #101).
Regarding claim 32, Lee as modified by Guo discloses : The semiconductor device of claim 1.
Lee teaches : wherein the slit structure is in contact with the source structure(Fig. 4, #160 contacting #105).
Regarding claim 33, Lee as modified by Guo discloses : The semiconductor device of claim 1.
Lee teaches : wherein the slit structure is in contact with the source structure(Fig. 3a, #CH disposed on same level in #105).
Claims 3-11 and 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20230301101, hereafter ‘Lee’ in view of Guo et al, US 20230269938, hereafter ‘Guo’ in further view of Lee et al, US 20230005954, hereafter ‘954’.
Regarding claim 3, Lee as modified by Guo discloses : The semiconductor device of claim 1.
Lee as modified by Guo does not disclose : wherein the channel structures comprise: a first channel structure comprising a first protruding part that protrudes into the source structure by a first height; and a second channel structure comprising a second protruding part that protrudes into the source structure by a second height.
However, in the same field of endeavor, 954 teaches : wherein the channel structures comprise: a first channel structure comprising a first protruding part that protrudes into the source structure by a first height; and a second channel structure comprising a second protruding part that protrudes into the source structure by a second height(Fig. 6, #CS1 and #CS3 having different depths into #100 where a source structure may be included on or in #100 [0060]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of 954 to Lee and Guo to include channel structures that protrude into a source structure at different depths.
Regarding claim 4, Lee as modified by Guo and 954 discloses : The semiconductor device of claim 3.
954 teaches : wherein the first height and the second height are different from each other(Fig.6, #CS1 and #CS3 having different heights).
Regarding claim 5, Lee as modified by Guo and 954 discloses : The semiconductor device of claim 3.
Lee as modified by 954 teaches : wherein the source structure comprises: a first part that surrounds the first protruding part; a second part that surrounds the second protruding part; and a third part that is in contact with the first channel structure and the second channel structure and protrudes between the first part and the second part(Lee, Fig 5, #105 to include different layers #101, #102, and #103 with #103 surrounding a cut and #101 surrounding a protruding part. 954, Fig. 6, channel structures with protruding into #100 with different depths where a source structure in or on top of #100 [0060]).
Regarding claim 6, Lee as modified by Guo and 954 discloses : The semiconductor device of claim 5.
Lee as modified by 954 teaches : wherein the third part comprises: a horizontal part that extends between the gate structure and the first part and between the gate structure and the second part(#103 between #ST and #101); and a vertical part that protrudes between the first part and the second part and protrudes from the horizontal part(#101 and #103 protrudes due to cut in #102).
Regarding claim 7, Lee as modified by Guo and 954 discloses : The semiconductor device of claim 5.
Lee discloses : wherein the memory layer comprises: a first memory pattern that is disposed between the channel layer and the source structure(Fig. 5, #145 between #140 and #101); and a second memory pattern that is disposed between the channel layer and the gate structure(#145 between #140 and #ST), and wherein the cut area is defined between the first memory pattern and the second memory pattern(cut area in #102).
Regarding claim 8, Lee as modified by Guo and 954 discloses : The semiconductor device of claim 7.
Lee teaches : wherein the first part or the second part surrounds the first memory pattern(Fig. 5, #101 surrounds a bottom most part of #CH).
Regarding claim 9, Lee as modified by Guo and 954 discloses : The semiconductor device of claim 5.
Lee teaches : wherein the third part is in contact with the channel layer(Fig. 5, #102 in contact with #140 [0096]).
Regarding claim 10, Lee as modified by Guo and 954 discloses : The semiconductor device of claim 5.
Lee teaches : wherein the source structure further comprises a fourth part that is disposed between the third part and the gate structure(Fig. 5, #103 disposed between #ST and #102).
Regarding claim 11, Lee as modified by Guo and 954 discloses : The semiconductor device of claim 5.
Lee teaches : further comprising a junction that is disposed within the channel layer of each of the channel structures having different heights(#192 to include #163 and #165 [0070]).
Regarding claim 34, Lee as modified by Guo and 954 discloses : The semiconductor device of claim 7.
954 teaches : wherein the first memory pattern and the second memory pattern have different heights(The ends of #CS1 and #CS3 in #100 are at different depths).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.T./Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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