Attorney’s Docket Number: TWT09722/US
Filing Date: 9/11/2023
Claimed Priority Date: N/A
Applicant(s): Tsai
Examiner: Rianna B. Greer
DETAILED ACTION
This Office action respond to the election filed on 1/20/2026.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I, directed to a semiconductor structure in the reply filed on 1/20/2026, is acknowledged. Applicant canceled claims 12-20 and indicated that claims 1-11 read on the elected invention. The examiner agrees. Accordingly, pending in this application are claims 1-11.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed arrangement of a word line over and electrically connected to the gate of the transistor in claim 1 must be shown or the feature(s) canceled from the claim(s). The drawings instead depict a word line 154 over gate dielectric layer 152 (see, e.g., Figs. 1-2). No new matter should be entered.
The drawings are additionally objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "142" (associated with a semiconductive layer) and "144" have both been used to designate the drain in Figs. 11-13. Accordingly, reference character “142” should be removed from Fig. 12 and replaced with reference character “144” to indicate the drain.
The drawings are additionally objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: IMP2. Fig. 12 instead uses the reference characters “HM2” (associated with a second hard mask layer) and “IMP1” (associated with a first implantation process) to depict a second implantation process. Accordingly, reference characters “HM2” and “IMP1” should be removed from Fig. 12 and replaced with reference character “IMP2” to indicate the second implantation process.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: the specification must provide written description of the claimed arrangement of a word line over and electrically connected to the gate of the transistor in claim 1.
The disclosure is additionally objected to because of the following informalities:
- In Par. [0029], “In some embodiments, the memory array of Fig. 1 is a DRAM array, which includes a plurality of DRAM cell.” should read --In some embodiments, the memory array of Fig. 1 is a DRAM array, which includes a plurality of DRAM cells.--
- In Par. [0029], “A typical DRAM cell incorporates capacitor 110 and a transistor (such as transistor 140 discussed in Fig. 2) in which the capacitor 110 temporarily store data based on the charged state of the capacitor 110.” should read --A typical DRAM cell incorporates capacitor 110 and a transistor (such as transistor 140 discussed in Fig. 2) in which the capacitor 110 temporarily stores data based on the charged state of the capacitor 110.--
- In Par. [0032], “Each of the word line 154 is electrically connected to the transistors 140 that are arranged along Y-direction.” should read --Each of the word lines 154 is electrically connected to the transistors 140 that are arranged along Y-direction.--
- In Par. [0032], “Each of the bit line 170 is electrically connected to the transistors 140 that are arranged along X-direction through the respective bit line contacts 160, in which each of the bit line contacts 160 is electrically connected to the transistor 140 of a respective one of the memory cells MC.” should read --Each of the bit lines 170 is electrically connected to the transistors 140 that are arranged along X-direction through the respective bit line contacts 160, in which each of the bit line contacts 160 is electrically connected to the transistor 140 of a respective one of the memory cells MC.--
- In Par. [0032], “Each of The body contact 130 is vertically below the bit line contacts 160.” should read --Each of the body contact 130 is vertically below the bit line contacts 160.--
- In Par. [0033], “However, the holes may be swept toward the first dielectric layer 104 and as a transient storage.” should read --However, the holes may be swept toward the first dielectric layer 104 and cause a transient storage.--
- In Par. [0034], “In some embodiments, the semiconductor substrate 100 may be made of semiconductor material, such as polysilicon but the present disclosure is not limited thereto, the conductive layer 102 may be made of tungsten (W), Titanium nitride (TiN), tantalum nitride (TaN), but the present disclosure is not limited thereto, and the first dielectric layer 104 may be made of silicon oxide, silicon nitride, but the present disclosure is not limited thereto.” should read --In some embodiments, the semiconductor substrate 100 may be made of semiconductor material, such as polysilicon but the present disclosure is not limited thereto, the conductive layer 102 may be made of tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), but the present disclosure is not limited thereto, and the first dielectric layer 104 may be made of silicon oxide, silicon nitride, but the present disclosure is not limited thereto.--
- In Par. [0036], “Then, a body contact material layer 130’ is formed overfilling the recess R (see Fig. 6) and extending to top surface of the second dielectric layer 120.” should read --Then, a body contact material layer 130’ is formed by overfilling the recess R (see Fig. 6) and extending to top surface of the second dielectric layer 120.--
- In Par. [0039], “Subsequently, the conductive material layer is patterned to form the word line 154, and then the dielectric material layer is etched by using the word line 154 as etch mask to form the gate dielectric layer 152.” should read --Subsequently, the conductive material layer is patterned to form the word line 154, and then the dielectric material layer is etched by using the word line 154 as an etch mask to form the gate dielectric layer 152.--
- In Par. [0040], “Subsequently, a first implantation process IMP1 is performed to form the drain 144 through the opening O2 of the second hard mask layer.” should read --Subsequently, a first implantation process IMP1 is performed to form the drain 144 through the opening O2 of the second hard mask layer HM2.--
- In Par. [0043], “In some embodiments, the bit line contact 160 is made of conductive material, such as tungsten (W), Titanium nitride (TiN), tantalum nitride (TaN), doped semiconductor material (e.g., p-doped or n-doped silicon), and/or other CMOS contact metals.” should read --In some embodiments, the bit line contact 160 is made of conductive material, such as tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), doped semiconductor material (e.g., p-doped or n-doped silicon), and/or other CMOS contact metals.--
Appropriate corrections are required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-6 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites an arrangement of a word line over and electrically connected to the gate of the transistor; however, in Fig. 2 and Par. [0030], it is disclosed that a word line may also serve as a gate of the transistor, and thus the word line may be interchangeably referred to as gate of each transistor. The word line cannot simultaneously be the gate of the transistor and over the gate of the transistor.
The applicant may cancel the claim, amend the claim, or demonstrate explicit support for the claimed subject matter in the original disclosure (e.g., by citing specific excerpts from Specification or features in Drawings related to the claimed embodiment, as originally filed). A broad statement alleging support for the claimed subject matter will be considered non-persuasive.
Claims 2-6 depend from claim 1 and therefore inherit the deficiencies identified supra.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Gonzalez (US2003/0111680, hereinafter Gonzalez-680) in view of Gonzalez (US2004/0041265, hereinafter Gonzalez-265).
Regarding Claim 1, Gonzalez-680 (see, e.g., portion 12 in Figs. 15-16) shows most aspects of the instant invention including a memory device comprising:
- a substrate (e.g., silicon substrate 48)
- a capacitor (e.g., capacitor construction 114 comprising 32, 40, and 42) over the substrate
- a transistor over the capacitor, wherein the transistor comprises:
- a channel region (e.g., channel region 112)
- a gate over the channel region (e.g., transistor gate 110)
- a source (e.g., source/drain diffusion region 84) and a drain (e.g., source/drain diffusion region 20) on opposite sides of the channel region, wherein the drain is over the capacitor
- a word line (e.g., wordline of conductive material 64) over and electrically connected to the gate of the transistor
- a bit line contact (e.g., bitline interconnection 160) over and electrically connected to the source of the transistor
However, Gonzalez-680 is silent about a body contact below the source of the transistor. Gonzalez-265 (see, e.g., Pars. [0005], [0039] and Fig. 2), on the other hand and in the same field of endeavor, teaches a semiconductor structure having a body contact (e.g., conductive biasing layer 215) below a source (e.g., source/drain region 235) of a transistor (e.g., gate oxide layer 239 and transistor gate 241) in a silicon on insulator (SOI) structure to provide a bias voltage to the body region of the transistor and avoid floating body effects that hinder device performance.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a body contact below the source of the transistor in the structure of Gonzalez-680, as taught by Gonzalez-265, to provide a bias voltage to the body region of the transistor and avoid floating body effects that hinder device performance.
Regarding Claim 2, Gonzalez-680 (see, e.g., portion 12 in Figs. 15-16) shows that a bottom of the drain (e.g., 20) is lower than a bottom of the source (e.g., 84).
Regarding Claim 3, Gonzalez-265 (see, e.g., Fig. 2) teaches that a bottom of the source (e.g., 235) is vertically spaced apart from the body contact (e.g., 215).
Regarding Claim 4, Gonzalez-265 (see, e.g., Fig. 2) teaches that the bit line contact (e.g., conductive bitline interconnect 247) vertically overlaps the body contact (e.g., 215).
Regarding Claim 5, Gonzalez-680 (see, e.g., portion 12 in Figs. 15-16) shows that the drain (e.g., 20) is in contact with the capacitor (e.g., 114 comprising 32, 40, and 42).
Regarding Claim 6, Gonzalez-680 (see, e.g., portion 12 in Fig. 15) shows a bit line (e.g., bitline 400) over and in contact with the bit line contact (e.g., 160).
Regarding Claim 7, Gonzalez-680 (see, e.g., portion 12 in Figs. 15-16) shows most aspects of the instant invention including a memory device comprising:
- a plurality of memory cells (e.g., Par. [0004]: the invention encompasses an array of memory cells), wherein each of the memory cells comprises:
- a transistor (e.g., transistor gate 110, channel region 112, and source/drain diffusion regions 20 and 84)
- a capacitor (e.g., capacitor construction 114 comprising 32, 40, and 42) electrically connected to the transistor
- a word line (e.g., wordline of conductive material 64) electrically connected to the transistor of each of the memory cells
- a plurality of bit line contacts (e.g., bitline interconnection 160), wherein each of the bit line contacts is electrically connected to the transistor of a respective one of the memory cells
However, Gonzalez-680 is silent about a body contact vertically below the bit line contacts. Gonzalez-265 (see, e.g., Pars. [0005], [0039] and Fig. 2), on the other hand and in the same field of endeavor, teaches a semiconductor structure having a body contact (e.g., conductive biasing layer 215) vertically below a bit line contact (e.g., conductive bitline interconnect 247) in a silicon on insulator (SOI) structure to provide a bias voltage to the body region of a transistor and avoid floating body effects that hinder device performance.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a body contact vertically below the bit line contacts of the transistor in the structure of Gonzalez-680, as taught by Gonzalez-265, to provide a bias voltage to the body region of a transistor and avoid floating body effects that hinder device performance.
Regarding Claim 8, Gonzalez-680 (see, e.g., portion 12 in Figs. 15-16) shows that the capacitor (e.g., 114 comprising 32, 40, and 42) is in contact with a bottom of a drain (e.g., 20) of the transistor (e.g., transistor gate 110, channel region 112, and 20 and 84).
Regarding Claim 9, Gonzalez-680 (see, e.g., portion 12 in Figs. 15-16) shows that the transistor (e.g., 110, 112, 20, and 84) is at a higher level than the capacitor (e.g., 114 comprising 32, 40, and 42).
Regarding Claim 10, Gonzalez-265 (see, e.g., Fig. 2) teaches that the bit line contacts (e.g., 247) and the body contact (e.g., 215) are at opposite sides of a source (e.g., source/drain region 235) of the transistor (e.g., gate oxide layer 239 and transistor gate 241).
Regarding Claim 11, Gonzalez-265 (see, e.g., Fig. 2) teaches that the body contact (e.g., 215) and the capacitor (e.g., conductive layer 223, dielectric layer 224, and conductive layer 226) are at a lower level than the transistor (e.g., 239 and 241).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. The additional references cited disclose one-transistor, one-capacitor (1T1C) dynamic random-access memory (DRAM) cells having arrangements of features similar to the instant inventions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Rianna B. Greer whose telephone number is (571) 272-7985. The examiner can normally be reached Monday - Friday, 8 AM - 6 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.B.G./Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814