Attorney’s Docket Number: TWT09722/US
Filing Date: 09/11/2023
Claimed Foreign Priority Date: none
Applicant: Tsai
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Amendment filed on 05/28/2026.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The Amendment filed on 05/28/2026, responding to the Office action mailed on 03/04/2026, has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this application are claims 1-11.
Response to Amendment
Applicant’s amendments to the Drawings and Specification have overcome the respective objections to Drawings and Specification, as previously formulated in the Non-Final Office action mailed on 03/04/2026. Accordingly, all prior objections are hereby withdrawn.
Applicant’s amendments to the claims have overcome the claim rejections under 35 U.S.C. 112 and 35 U.S.C. 103, as previously formulated in the same Office action. Accordingly, all prior claim rejections are also withdrawn. However, applicant’s amendments have raised new issues, and new grounds for rejection are presented below, as necessitated by Applicant’s amendments to the claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et. al (US2007/0235801, hereinafter Cheng-801).
Regarding Claim 1, Cheng-801 (see, e.g., Figs. 17A-B) shows all aspects of the instant invention, including a memory device, comprising:
- a substrate (e.g., lower layer 105)
- a capacitor (e.g., trench capacitor comprising buried plate 145, dielectric layer 150, and conducting plate 155) over the substrate
- a transistor (e.g., vertical FET) over the capacitor, wherein the transistor comprises:
a channel region (e.g., portion of p-well 155 proximate to gate dielectric layer 175)
a gate (e.g., polysilicon gate 180) over the channel region
a source (e.g., source/drain 230) and a drain (e.g., source/drain 185) on opposite sides of the channel region, wherein the drain is over the capacitor
- a word line (e.g., wordline 240) electrically connected to the gate of the transistor
- a bit line contact (e.g., bitline contact 275) over and electrically connected to the source of the transistor
- a body contact (e.g., body contact 215) below the source of the transistor, wherein the body contact does not vertically overlap the capacitor
Regarding Claim 2, Cheng-801 (see, e.g., Figs. 17A-B) shows that a bottom of the drain (e.g., 185) is lower than a bottom of the source (e.g., 230).
Regarding Claim 3, Cheng-801 (see, e.g., Figs. 17A-B) shows that a bottom of the source (e.g., 230) is vertically spaced apart from the body contact (e.g., 215).
Regarding Claim 4, Cheng-801 (see, e.g., Figs. 17A-B) shows that the bit line contact (e.g., 275) vertically overlaps the body contact (e.g., 215).
Regarding Claim 5, Cheng-801 (see, e.g., Figs. 17A-B) shows that the drain (e.g., 185) is in contact with the capacitor (e.g., by electrical contact through buried strap 165).
Regarding Claim 6, Cheng-801 (see, e.g., Figs. 17A-B and 19 and Par. [0044]) discloses connecting a bitline BL to a bitline contact 275. Accordingly, Chen also shows that a bit line over and in contact with the bit line contact.
Regarding Claim 7, Cheng-801 (see, e.g., Figs. 17A-B) shows all aspects of the instant invention, including a memory device, comprising:
- a plurality of memory cells (see, e.g., [0028]: the pattern of 4 DRAM cells is repeated to form a larger DRAM array), wherein each of the memory cells comprises:
a transistor (e.g., vertical FET)
a capacitor (e.g., trench capacitor comprising buried plate 145, dielectric layer 150, and conducting plate 155) electrically connected to the transistor
- a word line (e.g., wordline 240) electrically connected to the transistor of each of the memory cells
- a plurality of bit line contacts (e.g., bitline contacts 275), wherein each of the bit line contacts is electrically connected to the transistor of a respective one of the memory cells
- a body contact (e.g., body contact 215) vertically below the bit line contacts, wherein the body contact does not vertically overlap the capacitor.
Regarding Claim 8, Cheng-801 (see, e.g., Figs. 17A-B) shows the capacitor is in contact with a bottom of a drain (e.g., source/drain 185) of the transistor (e.g., by electrical contact through buried strap 165).
Regarding Claim 9, Cheng-801 (see, e.g., Figs. 17A-B) shows that the transistor is at a higher level than the capacitor.
Regarding Claim 10, Cheng-801 (see, e.g., Figs. 17A-B) shows that the bit line contacts (e.g., 275) and the body contact (e.g., 215) are at opposite sides of a source (e.g., source/drain 230) of the transistor.
Regarding Claim 11, Cheng-801 (see, e.g., Figs. 17A-B) shows that the body contact (e.g., 215) and the capacitor are at a lower level than the transistor.
Claims 1-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et. al (US2007/0045698, hereinafter Cheng-698).
Regarding Claim 1, Cheng-698 (see, e.g., Figs. 1 and 12) shows all aspects of the instant invention, including a memory device, comprising:
- a substrate (e.g., substrate 14)
- a capacitor (e.g., storage capacitor 28) over the substrate
- a transistor (e.g., transistor/access device 30) over the capacitor, wherein the transistor comprises:
a channel region (e.g., channel region 64)
a gate (e.g., gate 40) over the channel region
a source (e.g., source/drain 62) and a drain (e.g., source/drain 44) on opposite sides of the channel region, wherein the drain is over the capacitor
- a word line (e.g., word line 68) electrically connected to the gate of the transistor
- a bit line contact (e.g., bit line contact 80) over and electrically connected to the source of the transistor (see, Par. [0053]: bit line contact 80 establishes an electrical contact with the corresponding source/drain region 62)
- a body contact (e.g., body contact 54) below the source of the transistor, wherein the body contact does not vertically overlap the capacitor
Regarding Claim 2, Cheng-698 (see, e.g., Figs. 1 and 12) shows that a bottom of the drain (e.g., 44) is lower than a bottom of the source (e.g., 62).
Regarding Claim 3, Cheng-698 (see, e.g., Figs. 1 and 12) shows that a bottom of the source (e.g., 62) is vertically spaced apart from the body contact (e.g., 54).
Regarding Claim 4, Cheng-698 (see, e.g., Figs. 1 and 12) shows that the bit line contact (e.g., 80) vertically overlaps the body contact (e.g., 54).
Regarding Claim 5, Cheng-698 (see, e.g., Figs. 1 and 12) shows that the drain (e.g., 44) is in contact with the capacitor (e.g., by electrical contact through buried strap 43).
Regarding Claim 6, Cheng-698 (see, e.g., Figs. 1 and 12, and Par. [0054]) discloses the deposition of an interlayer dielectric, and the formation of bit lines thereupon that contact the bit line contacts 80. Accordingly, Chen also shows that a bit line over and in contact with the bit line contact.
Regarding Claim 7, Cheng-698 (see, e.g., Figs. 1 and 12) shows all aspects of the instant invention, including a memory device, comprising:
- a plurality of memory cells (e.g., memory cells 12), wherein each of the memory cells comprises:
a transistor (e.g., transistor/access device 30)
a capacitor (e.g., storage capacitor 28) electrically connected to the transistor
- a word line (e.g., word line 68) electrically connected to the transistor of each of the memory cells
- a plurality of bit line contacts (e.g., bit line contacts 80), wherein each of the bit line contacts is electrically connected to the transistor of a respective one of the memory cells
- a body contact (e.g., body contact 54) vertically below the bit line contacts, wherein the body contact does not vertically overlap the capacitor.
Regarding Claim 8, Cheng-698 (see, e.g., Figs. 1 and 12) shows the capacitor is in contact with a bottom of a drain (e.g., source/drain 44) of the transistor (e.g., by electrical contact through buried strap 42).
Regarding Claim 9, Cheng-698 (see, e.g., Figs. 1 and 12) shows that the transistor is at a higher level than the capacitor.
Regarding Claim 10, Cheng-698 (see, e.g., Figs. 1 and 12) shows that the bit line contacts (e.g., 80) and the body contact (e.g., 54) are at opposite sides of a source (e.g., source/drain 62) of the transistor.
Regarding Claim 11, Cheng-698 (see, e.g., Figs. 1 and 12) shows that the body contact (e.g., 54) and the capacitor are at a lower level than the transistor.
Response to Arguments
Applicant’s remarks with respect to the claims filed on 05/28/2026 have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul whose telephone number is (571) 270-5514. The examiner can normally be reached Monday-Friday 9am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
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