DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II., there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/26/2026.
Applicant’s election without traverse of Invention I. in the reply filed on 01/26/2026 is acknowledged.
Examiner’s Note
Examiner notes that the limitations in Claim 1 that define the first and second direction align to direction D3 (which aligns to first direction as it is perpendicular to the bottom surface of the semiconductor substrate (10 of the instant application) and D1 (which aligns to the second direction as it is parallel to the semiconductor substrate (10 of the instant application) and the lengths of the gate electrodes are aligned in that direction) as shown in the axis of Fig 6A. Referencing the specification of the instant application, Para [0050] defines D1 as the first direction and Para [0055] defines D3 as the third direction. This could lead to a lack of antecedent basis within the claim with respect to the specification. Further the non-matching of direction labels between the claim and the specification may cause confusion.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 and 9-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ogawa et al. (US 2022/0139878 A1, hereinafter Ogawa ‘878).
PNG
media_image1.png
781
1509
media_image1.png
Greyscale
PNG
media_image2.png
685
1116
media_image2.png
Greyscale
With respect to Claim 1 Ogawa ‘878 discloses a three-dimensional semiconductor memory device (Figs 1-16A, 17, 19-20 and 22B), comprising:
a bottom structure (901, Fig 19, Para [0048]) and a top structure (902, Fig 19, Para [0098]) on the bottom structure (901)(902 on 901 disclosed in Fig 19), the bottom structure (901) comprising:
a semiconductor substrate (712, Fig 19, Para [0048]) that includes a cell array region (100, Fig 3, Para [0063]) and a connection region (200, Fig 3, Para [0063]) extending from the cell array region (100)(200 extending from 100 disclosed in Fig 3); and
a first stack (32/46 of 901, Fig 3, Para [0055], note Para [0086] discloses sacrificial layer 42 of Fig 3 is replaced with conductive layer 46) that includes first gate electrodes (46 of 901, Fig 8, Para [0087] discloses 46 as gate electrodes) and first interlayer insulating layers (32 of 901, Fig 8, Para [0055]) alternately stacked (disclosed in Fig 8) on the semiconductor substrate (712), wherein the top structure (902) comprises a second stack (32/46 of 902, Fig 19, Para [0099]) that includes second gate electrodes (46 of 902, Para [0098] discloses structure of 902 is derived from structure of 901) and second interlayer insulating layers (32 of 902, Para [0098] discloses structure of 902 is derived from structure of 901) alternately stacked (disclosed in Fig 19) on the first stack (901)(arrangement disclosed in Fig 19),
wherein respective lengths (lengths of 46 of 901 as shown in annotated Fig 19 of Ogawa ‘878) of the first gate electrodes (46 of 901) in a second direction (second direction as shown in annotated Fig 19 of Ogawa ‘878, hereinafter 2D) decrease as a distance in a first direction (first direction as shown in annotated Fig 19 of Ogawa ‘878, hereinafter 1D) from a bottom surface (bottom of 712 as shown in annotated Fig 19 of Ogawa ‘878) of the semiconductor substrate (712) increases (annotated Fig 19 of Ogawa ‘878 discloses that the gate electrodes of 901 decrease in length as the distance from bottom of 712 along 1D increases),
wherein respective lengths (lengths of 46 of 902 as shown in annotated Fig 19 of Ogawa ‘878) of the second gate electrodes (46 of 902) in the second direction (2D) increase as a distance in the first direction (1D) from the bottom surface (bottom of 712 as shown in annotated Fig 19 of Ogawa ‘878) of the semiconductor substrate (712) increases (annotated Fig 19 of Ogawa ‘878 discloses that the gate electrodes of 902 increase in length as the distance from bottom of 712 along 1D increases), and
wherein the first direction (1D) is perpendicular to the bottom surface (bottom of 712 as shown in annotated Fig 19 of Ogawa ‘878) of the semiconductor substrate (712), and the second direction (2D) is parallel to the bottom surface (bottom of 712 as shown in annotated Fig 10 of Ogawa ‘878) of the semiconductor substrate (712)(annotated Fig 19 of Ogawa ‘878 discloses 1D is perpendicular to the bottom of 712 and 2D is parallel to the bottom of 712).
With respect to Claim 2 Ogawa ‘878 discloses all limitations of the semiconductor memory device of claim 1, and Ogawa ‘878 further discloses wherein the bottom structure (901) further comprises a first vertical channel structure (55 of 901, Fig 10, Para [0078] discloses that vertical channel structures 55 are in the element 58 as shown in annotated Fig 19 of Ogawa ‘878, hereinafter 1VCS) that extends in the first stack (32/46 of 901), and a first bonding pad (98 of 1VCS, annotated Fig 19 of Ogawa ‘878, Para [0122]) that is on the first vertical channel structure (1VCS) and is electrically connected (disclosed in Para [0097]) to the first vertical channel structure (1VCS),
wherein the top structure (902) further comprises a second vertical channel structure (55 of 902, Fig 10, Para [0078] discloses that vertical channel structures 55 are in the element 58 as shown in Fig 10, hereinafter 2VCS) that extends in the second stack (32/46 of 902), and a second bonding pad (98 of 2VCS, Fig 19 and annotated Fig 22B of Ogawa ‘878, Para [0122]) that is on a lower surface (bottom of 2VCS as shown in annotated Fig 19 of Ogawa ‘878) of the second vertical channel structure (2VCS) and is electrically connected (disclosed in Para [0097]) to the second vertical channel structure (2VCS), and
wherein the first bonding pad (98 of 1VCS) and the second bonding pad (98 of 2VCS) are electrically connected to each other (disclosed in Para [0104]).
With respect to Claim 3 Ogawa ‘878 discloses all limitations of the semiconductor memory device of claim 2, wherein a width (width of 1VCS) of the first vertical channel structure (1VCS) in the second direction (2D) increases as a distance in the first direction (1D) from the bottom surface (bottom of 712) of the semiconductor substrate (712) increases (Para [0065] discloses opening 49 wherein vertical channel structures are formed as tapered, therefore the width of 1VCS would increase in second direction as the as the distance from bottom of 712 along 1D increases), and
wherein a width (width of 2VCS) of the second vertical channel structure (2VCS) in the second direction (2D) decreases as a distance in the first direction (1D) from the bottom surface (bottom of 712) of the semiconductor substrate (712) increases (Para [0065] discloses opening 49 wherein vertical channel structures are formed as tapered, therefore the width of 2VCS, being inverted, would decrease in second direction as the as the distance from bottom of 712 along 1D increases).
With respect to Claim 4 Ogawa ‘878 discloses all limitations of the semiconductor memory device of claim 2, and Ogawa ‘878 further discloses wherein the top structure (902) further comprises a bit line (92, Fig 22B, Para [0122]) on the second vertical channel structure (2VCS as shown in annotated Fig 22B of Ogawa ‘878), and an upper conductive pad (88 of 901, Fig 10, Para [0097] discloses 88 connected to 55 and 92) between (shown in annotated Fig 19 of Ogawa ‘878 and disclosed in Para [0097]) the second vertical channel structure (2VCS) and the bit line (92), and
wherein the second vertical channel structure (2VCS) is electrically connected (disclosed in Para [0097]) to the bit line (92) through the upper conductive pad (88 of 901).
With respect to Claim 5 Ogawa ‘878 discloses all limitations of the semiconductor memory device of claim 2, and Ogawa ‘878 discloses further comprising:
a first channel plug (63 in 55 of 901, Fig 4H, Para [0076]) between the first vertical channel structure (1VCS) and the first bonding pad (98 of 1VCS), wherein the first vertical channel structure (1VCS) is electrically connected (Para 0094] discloses 63 electrically connected to 88 and Para [0097] discloses 88 connected to 92 and Para [0122] discloses 92 connected to 98) to the first bonding pad (98 of 1VCS) through the first channel plug (63 in 55 of 901)(connection of 63 and 98 described above); and
a second channel plug (63 in 55 of 902, Fig 4H, Para [0076]) between the second vertical channel structure (2VCS) and the second bonding pad (98 of 2VCS), wherein the second vertical channel structure (2VCS) is electrically connected (Para [0094] discloses 63 electrically connected to 88 and Para [0097] discloses 88 connected to 92 and Para [0122] discloses 92 connected to 98) to the second bonding pad (98 of 2VCS) through the second channel plug (63 in 55 of 902)(connection of 63 and 98 described above).
With respect to Claim 6 Ogawa ‘878 discloses all limitations of the semiconductor memory device of claim 1, and Ogawa ‘878 discloses further wherein the first gate electrodes (46 of 901) comprise respective first pad portions (pad portion where contact 86 contacts 46 as shown in annotated Fig 22B of Ogawa ‘878, hereinafter 1PP) on the connection region (200),
wherein the bottom structure (901) further comprises:
a first cell contact plug (86 of 901, as shown in annotated Fig 19 of Ogawa ‘878, Para [0123]) that extends in the first direction (1D) and is electrically connected (disclosed in Para [0123]) to one of the first pad portions (1PP)(shown in annotated Fig 19 of Ogawa ‘878); and
a first bonding pad (98 of 86, as shown in annotated Fig 19 of Ogawa ‘878, Para [0122]) that is on the first cell contact plug (86 of 901) and is electrically connected (disclosed in Para [0123]) to the first cell contact plug (86 of 901),
wherein the top structure (902) further comprises:
a first penetration electrode (82 of 902, as shown in annotated Fig 19 of Ogawa ‘878, Para [0094]) that is on the first bonding pad (98 of 86)(annotated Fig 19 of Ogawa ‘878 discloses first penetration electrode on first bonding pad of first cell contact plug) and extends in the first direction (1D); and
a second bonding pad (98 of 82, as shown in annotated Fig 19 of Ogawa ‘878) that is between the first bonding pad (98 of 86 as shown in annotated Fig 19 of Ogawa ‘878) and the first penetration electrode (82 of 902) and is electrically connected (Para [0094] discloses 82 electrically connected to 88 and Para [0097] discloses 88 connected to 92 and Para [0122] discloses 92 connected to 98) to the first penetration electrode (82 of 902), and
wherein the first bonding pad (98 of 86) and the second bonding pad (98 of 82) are electrically connected to each other (Para [0103 and 0104] discloses pad 98s are bonded, therefore electrically connected).
With respect to Claim 7 Ogawa ‘878 discloses all limitations of the semiconductor memory device of claim 6, and Ogawa ‘878 discloses further wherein the top structure (902) further comprises an interconnection layer (interconnect layer of 902, as shown in annotated Fig 19 of Ogawa ‘878, Para [0099], hereinafter ICL) on the first penetration electrode (82 of 902), and a first conductive line (780 of 902, Fig 19, Para [0099], note that this element is labeled as 78 on Fig 19 but referenced as 780 in the text including in Para [0099]) between the first penetration electrode (82 of 902) and the interconnection layer (ICL)(780 of 902 being between 82 and the interconnect layer disclosed on annotated Fig 19), and
wherein the first conductive line (780 of 902) is electrically connected (annotated Fig 19 and Para [0099] discloses 780 connected to ICL) to the interconnection layer (ICL), and the first penetration electrode (82 of 902) is electrically connected (annotated Fig 19 and Para [0099] discloses 82 of 902 connected to 780 of 902) to the first conductive line (780 of 902).
With respect to Claim 9 Ogawa ‘878 discloses all limitations of the semiconductor memory device of claim 6, and Ogawa ‘878 further discloses wherein the second gate electrodes (46 of 902) comprise respective second pad portions (pad portion where contact 86 contacts 46 as shown in annotated Fig 22B of Ogawa ‘878, hereinafter 2PP) on the connection region (200),
wherein the top structure (902) further comprises:
a second cell contact plug (86 of 902, as shown in annotated Fig 22B of Ogawa ‘878, Para [0123]) electrically connected (disclosed in Para [0123]) to one of the second pad portions (2PP);
a second penetration electrode (84, as shown in annotated Fig 19 of Ogawa ‘878, Para [0094]) that is spaced apart (disclosed in annotated Fig 19 of Ogawa ‘878) from the second stack (32/46 of 902) in the second direction (2D) and extends in the first direction (1D)(annotated Fig 19 of Ogawa ‘878 discloses 84 extends in the first direction and is spaced apart from second stack); and
a redistribution layer (90, as shown in annotated Fig 19 of Ogawa ‘878, Para [0095 and 0099]) between the first stack (32/46 of 901) and the second stack (32/46 of 902)(90 between first and second stack shown in Fig 10), and
wherein the redistribution layer (90) comprises a first redistribution pattern (contacts in 90 of 902 shown in annotated Fig 19 of Ogawa ‘878, hereinafter 1RDP) electrically connected (disclosed in Fig 19 and Para [0099]) to the second cell contact plug (86 of 902), and a second redistribution pattern (contacts in 90 of 901 shown in annotated Fig 19 of Ogawa ‘878, hereinafter 2RDP) electrically connected (disclosed in Fig 19 and Para [0097]) to the second penetration electrode (84, as shown in annotated Fig 19 of Ogawa ‘878.
With respect to Claim 10 Ogawa ‘878 discloses all limitations of the semiconductor memory device of claim 9, and Ogawa ‘878 further discloses wherein the top structure (902) further comprises an interconnection layer (interconnect layer of 902, as shown in annotated Fig 19 of Ogawa ‘878, Para [0099], hereinafter ICL) on the second penetration electrode (84), and a first conductive line (780 of 902, Fig 19, Para [0099], note that this element is labeled as 78 on Fig 19 but referenced as 780 in the text including in Para [0099) between the second penetration electrode (84) and the interconnection layer (ICL),
wherein the second penetration electrode (84) is electrically connected to the first conductive line (780 of 902), and the first conductive line (780 of 902) is electrically connected (annotated Fig 19 and Para [0099] discloses 780 connected to ICL)to the interconnection layer (ICL), and
wherein the first redistribution pattern (1RDP) and the second redistribution pattern (2RDP) are electrically connected to each other (Fig 19 and Para [0103] disclose 901 and 902 are bonded to each other at the pads, therefore 1RDP and 2RDP are electrically connected).
With respect to Claim 11 Ogawa ‘878 discloses all limitations of the semiconductor memory device of claim 9, and Ogawa ‘878 further discloses wherein the redistribution layer (90) is at a level in the first direction (1D) that is different from a level of the first bonding pad (98 of 1VCS) in the first direction (1D) and a level of the second bonding pad (98 of 2VCS) in the first direction (1D) (annotated Fig 22B of Ogawa ‘878 discloses layer 90 is at a level different from the level of the first bonding pad and a level of the second bonding pad in the first direction).
PNG
media_image1.png
781
1509
media_image1.png
Greyscale
PNG
media_image2.png
685
1116
media_image2.png
Greyscale
With respect to Claim 12 Ogawa ‘878 discloses a three-dimensional semiconductor memory device (Figs 1-16A, 17, 19-20 and 22B), comprising:
a bottom structure (901, Fig 19, Para [0048]) and a top structure (902, Fig 19, Para [0098]) on the bottom structure (901)(902 on 901 disclosed in Fig 19), the bottom structure (901) comprising:
a peripheral circuit structure (720, Fig 19, Para [0049]) on a semiconductor substrate (silicon wafer of 712, Fig 19, Para [0048]); and
a first cell array structure (first cell array structure disclosed in annotated Fig 19 of Ogawa ‘878, Para [0049], hereinafter 1CAS) on the peripheral circuit structure (720),
wherein the top structure (902) comprises:
a second cell array structure (second cell array structure disclosed in annotated Fig 19 of Ogawa ‘878, Para [0049], hereinafter 2CAS); and
an interconnection layer (interconnect layer of 902, as shown in annotated Fig 19 of Ogawa ‘878, Para [0099], hereinafter ICL) on the second cell array structure (2CAS),
wherein the first cell array structure (1CAS) comprises:
a semiconductor layer (semiconductor layer of 712, Fig 19, Para [0048] discloses 712 contains an epitaxial silicon layer formed on the silicon wafer);
a first stack (32/46 of 901, Fig 3, Para [0055], note Para [0086] discloses sacrificial layer 42 of Fig 3 is replaced with conductive layer 46) that includes first gate electrodes (46 of 901, Fig 8, Para [0087] discloses 46 as gate electrodes) and first interlayer insulating layers (32 of 901, Fig 8, Para [0055]) alternately stacked (disclosed in Fig 8) on the semiconductor layer (semiconductor layer of 712);
a cell contact plug (86 of 901, as shown in annotated Fig 22B of Ogawa ‘878, Para [0123]) electrically connected (disclosed in Para [0123]) to one of the first gate electrodes (46 of 901);
a source contact plug (source contact plug shown in annotated Fig 19 of Ogawa ‘878, Para [0101], SCP) that is laterally spaced apart (disclosed in annotated Fig 19) from the first stack (32/46 of 901) and is electrically connected (Para [0101] discloses SCP contacts 720S) to the semiconductor layer (semiconductor layer of 712); and
a peripheral penetration plug (82 of 901, as shown in annotated Fig 19 of Ogawa ‘878, Para [0094], hereinafter PPP) that is laterally spaced apart (disclosed in Fig 19) from the semiconductor layer (semiconductor layer of 712) and is electrically connected (annotated Fig 19 of Ogawa ‘878 discloses PPP connected to 720) to the peripheral circuit structure (720),
wherein the second cell array structure (2CAS) comprises:
a second stack (32/46 of 902, Fig 10, Para [0099]) that includes second gate electrodes (46 of 902, Para [0098] discloses structure of 902 is derived from structure of 901) and second interlayer insulating layers (32 of 902, Para [0098] discloses structure of 902 is derived from structure of 901) alternately stacked (disclosed in Fig 10) on the first cell array structure (1CAS)(arrangement disclosed in Fig 19);
a first penetration electrode (first 84 in 902, as shown in annotated Fig 19 of Ogawa ‘878, Para [0094], hereinafter 1PE) that is laterally spaced apart (disclosed in Fig 19) from the second stack (32/46 of 902) and is electrically connected (annotated Fig 19 discloses 1PE connected to 86 of 901 through conductive portion) to the cell contact plug (86 of 901);
a second penetration electrode (first 84 in 902, as shown in annotated Fig 19 of Ogawa ‘878, Para [0094], hereinafter 2PE) that is laterally spaced apart (disclosed in Fig 19) from the second stack (32/46 of 902) and the first penetration electrode (1PE) and is electrically connected (annotated Fig 19 of Ogawa ‘878 discloses 2PE connected to SCP by conductive portion) to the source contact plug (SCP); and
a third penetration electrode (third penetration electrode shown in annotated Fig 19 of Ogawa ‘878, hereinafter 3PE) that is laterally spaced apart (shown in Fig 19) from the second stack (32/46 of 902), the first penetration electrode (1PE), and the second penetration electrode (2PE) and is electrically connected to the peripheral penetration plug (PPP)(annotated Fig 19 of Ogawa ‘878 discloses 3PE spaced form second stack, 1PE, 2PE and connected to PPP through bonded contacts, Para [0103] discloses pads of 901 bonded to pads of 902, therefore they are electrically connected), and
wherein the first penetration electrode (1PE), the second penetration electrode (2PE), and the third penetration electrode (3PE) are electrically connected to the interconnection layer (ICL)(annotated Fig 19 of Ogawa ‘878 discloses 1PE, 2PE and 3PE connected to ICL).
With respect to Claim 13 Ogawa ‘878 discloses all limitations of the semiconductor memory device of claim 12, and Ogawa ‘878 further discloses wherein respective lengths (lengths of 46 of 901 as shown in annotated Fig 10 of Ogawa ‘878) of the first gate electrodes (46 of 901) in a second direction (second direction as shown in annotated Fig 10 of Ogawa ‘878, hereinafter 2D) decrease as a distance in a first direction (first direction as shown in annotated Fig 10 of Ogawa ‘878, hereinafter 1D) from a bottom surface (bottom of 712 as shown in annotated Fig 10 of Ogawa ‘878) of the semiconductor substrate (silicon wafer of 712) increases (annotated Fig 10 of Ogawa ‘878 discloses that the gate electrodes of 901 decrease in length as the distance from bottom of 712 along 1D increases,
wherein respective lengths (lengths of 46 of 902 as shown in annotated Fig 10 of Ogawa ‘878) of the second gate electrodes (46 of 902) in the second direction (2D) increase as a distance in the first direction (1D) from the bottom surface (bottom of 712 as shown in annotated Fig 10 of Ogawa ‘878) of the semiconductor substrate (silicon wafer of 712) increases (annotated Fig 10 of Ogawa ‘878 discloses that the gate electrodes of 902 increase in length as the distance from bottom of 712 along 1D increases), and
wherein the first direction (1D) is perpendicular to the bottom surface (bottom of 712 as shown in annotated Fig 10 of Ogawa ‘878) of the semiconductor substrate (silicon wafer of 712), and the second direction (2D) is parallel to the bottom surface (bottom of 712 as shown in annotated Fig 10 of Ogawa ‘878) of the semiconductor substrate (silicon wafer of 712)(annotated Fig 10 of Ogawa ‘878 discloses 1D is perpendicular to the bottom of 712 and 2D is parallel to the bottom of 712).
With respect to Claim 14 Ogawa ‘878 discloses all limitations of the semiconductor memory device of claim 12, and Ogawa ‘878 further discloses wherein the top structure (902) further comprises a redistribution layer (90, as shown in annotated Fig 19 of Ogawa ‘878, Para [0095 and 0099]) between (shown in annotated Fig 19 of Ogawa ‘878) the first stack (32/46 of 901) and the second stack (32/46 of 902), and
wherein a bottom surface (bottom of 90) of the redistribution layer (90) is higher than a bottom surface (bottom of 1PE) of the first penetration electrode (1PE), relative to the bottom surface of the semiconductor substrate (bottom of 712)(annotated Fig 19 of Ogawa ‘878 discloses above arrangement).
With respect to Claim 15 Ogawa ‘878 discloses all limitations of the semiconductor memory device of claim 12, and Ogawa ‘878 further discloses wherein the first cell array structure (1CAS) further comprises a first vertical channel structure (55 of 901, Fig 10, Para [0078] discloses that vertical channel structures 55 are in the element 58 as shown in Fig 10, hereinafter 1VCS) that extends in the first stack (32/46 of 901),
wherein the second cell array structure (2CAS) further comprises a second vertical channel structure (55 of 902, Fig 10, Para [0078] discloses that vertical channel structures 55 are in the element 58 as shown in Fig 10, hereinafter 2VCS) that extends in the second stack (32/46 of 902),
wherein the bottom structure (901) further comprises a first bonding pad (98 of 1VCS, Fig 19 and annotated Fig 22B of Ogawa ‘878, Para [0122]) between the first vertical channel structure (1VCS) and the second cell array structure (2CAS)(arrangement disclosed in annotated Fig 22B of Ogawa ‘878),
wherein the top structure (902) further comprises a second bonding pad (98 of 2VCS, Fig 19 and annotated Fig 22B of Ogawa ‘878, Para [0122]) between the second vertical channel structure (2VCS) and the first bonding pad (98 of 1VCS)(arrangement disclosed in annotated Fig 22B of Ogawa ‘878),
wherein the first vertical channel structure (1VCS) is electrically connected (disclosed in Para [0097]) to the first bonding pad (98 of 1VCS), and the second vertical channel structure (2VCS) is electrically connected (disclosed in Para [0097]) to the second bonding pad (98 of 2VCS), and
wherein the first bonding pad (98 of 1VCS) and the second bonding pad (98 of 2VCS) are in contact with each other (disclosed in annotated Fig 22B of Ogawa ‘878).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ogawa ‘878 in view of Park et al. (US 2020/0105735 A1, hereinafter Park ‘735), in view of the following arguments.
With respect to Claim 8 Ogawa ‘878 discloses all limitations of the semiconductor memory device of claim 6, but Ogawa ‘878 fails to explicitly discloses wherein a width of the first cell contact plug in the second direction increases as a distance in the first direction from the bottom surface of the semiconductor substrate increases, and wherein a width of the first penetration electrode in the second direction decreases as a distance in the first direction from the bottom surface of the semiconductor substrate increases.
Nevertheless, in a related endeavor (Fig 4 and 12 of Park ‘735), Park ‘735 teaches wherein a width (width of 260) of the first cell contact plug (260, Fig 4 of Park ‘735, Para [0056]) in the second direction (X as shown in Fig 4 of Park ‘735) increases as a distance in the first direction (Z as shown in Fig 4 of Park ‘735) from the bottom surface (bottom of 201) of the semiconductor substrate (201, Fig 4 of Park ‘735, Para [0040]) increases (Fig 4 and Para [0056] disclose plugs 260 are tapered, therefore the width of the via will increase in the second direction as the distance from the bottom of 201 increases in the first direction), and wherein a width (width of 261) of the first penetration electrode (top of 261, Fig 12 of Park ‘735, Para [0040]) in the second direction (X direction) decreases as a distance in the first direction (Z direction) from the bottom surface (bottom of 201) of the semiconductor substrate (201) increases (Fig 12 and Para [0056] disclose plugs 261 are tapered, therefore the width of the via will decrease in the second direction as the distance from the bottom of 201 increases in the first direction).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Park ‘735’steaching of a width of the first cell contact plug in the second direction increases as a distance in the first direction from the bottom surface of the semiconductor substrate increases, and wherein a width of the first penetration electrode in the second direction decreases as a distance in the first direction from the bottom surface of the semiconductor substrate increases into Ogawa ‘878’s device. Ogawa ‘878 teaches a memory device with contacts to the structure. Park ‘735 also teaches a memory device with contacts and teaches tapering the shape of the contact as it gets deeper in the structure. The ordinary artisan would have been motivated to modify Ogawa ‘878 in the manner set forth above, at least, because tapering the shape of the contacts as the contact gets deeper into the structure would help to keep contacts from making unwanted contacts with parts of the structure, as one of ordinary skill in the art will know that spacing between structures reduces the deeper in the structure.
As incorporated, the teaching of Park ‘735 of forming contacts with tapered side walls would be used in the contact plugs (86) and penetration electrodes (82) of Ogawa ‘878.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898