DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "a first penetration electrode" in ninth line of the claim. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, Examiner interprets "a first penetration electrode" as "the first penetration electrode".
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tang et al. (US 2021/0327482 A1, hereinafter Tang ‘482).
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With respect to Claim 1 Tang ‘482 discloses a three-dimensional semiconductor memory device (Fig 2), comprising:
a bottom structure (bottom structure as shown in annotated Fig 2 of Tang ‘482, Para [0047]), hereinafter BS) and a top structure (top structure as shown in annotated Fig 2 of Tang ‘482, Para [0047]), hereinafter TS) on the bottom structure (BS), the bottom structure (BS) comprising:
a semiconductor substrate (100, Fig 2, Para [0047]) that includes a cell array region (cell array region as shown in annotated Fig 2 of Tang ‘482 and disclosed in Para [0048], hereinafter CAR) and a connection region (region of P1/P2, as shown in annotated Fig 2, Para [0048], hereinafter CNR) extending from the cell array region (CAR);
a first stack (110, Fig 2, Para [0048]) that includes first gate electrodes (114, Fig 2, Para [0048]) and first interlayer insulating layers (112, Fig 2, Para [0048]) alternately stacked (disclosed in Fig 2 and in Para [0048]) on the semiconductor substrate (100); and
a cell contact plug (122, Fig 2, Para [0048]) electrically connected (122 electrically connected to 114 disclosed in Para [0048]) to one of the first gate electrodes (lowermost 114 as shown in Fig 2, Para [0048]),
wherein the top structure (TS) comprises;
a second stack (210, Fig 2, Para [0053]) that includes second gate electrodes (214, Fig 2, Para [0054]) and second interlayer insulating layers (212, Fig 2, Para [0054]) alternately stacked on (disclosed in Fig 2 and Para [0053-0054]) the first stack (110); and
a first penetration electrode (CS1, Fig 2, Para [0051]) electrically connected (CS1 connected to 114 via 122 disclosed in Para [0051]) to the cell contact plug (122), the first penetration electrode (CS1) vertically overlapping the cell contact plug (122)(CS1 vertically overlapping 122 is disclosed in Fig 2),
wherein respective lengths (lengths of 114) of the first gate electrodes (114) in a second direction (D2 as shown in axis of Fig 2) decrease as a distance in a first direction (D1 as shown in axis of Fig 2) from a bottom surface (bottom of 100) of the semiconductor substrate (100) increases (lengths of 114 decreasing in D2 as D1 from bottom of 100 increases is disclosed in Fig 2),
wherein respective lengths (lengths of 214) of the second gate electrodes (214) in the second direction (D2) increase as a distance in the first direction (D1) from the bottom surface (bottom of 100) of the semiconductor substrate (100) increases (lengths of 214 increasing in D2 as D1 from bottom of 100 increases is disclosed in Fig 2), and
wherein the first direction (D1) is perpendicular (disclosed in Fig 2) to the bottom surface (bottom of 100) of the semiconductor substrate (100), and the second direction (D2) is parallel to (disclosed in Fig 2) the bottom surface (bottom of 100) of the semiconductor substrate (100).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Tang ‘482 in view of Ogawa et al. (US 2022/0139878 A1, hereinafter Ogawa ‘878), in view of the following arguments.
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With respect to Claim 2 Tang ‘482 discloses all limitations of the semiconductor memory device of claim 1, but Tang ‘482 fails to explicitly disclose wherein the bottom structure further comprises a first vertical channel structure that extends in the first stack, and a first bonding pad that is on the first vertical channel structure and is electrically connected to the first vertical channel structure,
wherein the top structure further comprises a second vertical channel structure that extends in the second stack, and a second bonding pad that is on a lower surface of the second vertical channel structure and is electrically connected to the second vertical channel structure, and
wherein the first bonding pad and the second bonding pad are electrically connected to each other.
Nevertheless, in a related endeavor (Fig 1-16A, 17, 19-20 and 22B of Ogawa ‘878), Ogawa ‘878 teaches wherein the bottom structure (901, Fig 19, Para [0048]) further comprises a first vertical channel structure (55 of 901, Fig 10 of Ogawa ‘878, Para [0078] discloses that vertical channel structures 55 are in the element 58 as shown in annotated Fig 19 of Ogawa ‘878, hereinafter 1VCS) that extends in the first stack (32/46 of 901, Fig 3 of Ogawa ‘878, Para [0055], note Para [0086] discloses sacrificial layer 42 of Fig 3 is replaced with conductive layer 46), and a first bonding pad (98 of 1VCS, annotated Fig 19 of Ogawa ‘878, Para [0122]) that is on the first vertical channel structure (1VCS) and is electrically connected (disclosed in Para [0097]) to the first vertical channel structure (1VCS),
wherein the top structure (902, Fig 19 of Ogawa ‘878, Para [0098]) further comprises a second vertical channel structure (55 of 902, Fig 10 of Ogawa ‘878, Para [0078] discloses that vertical channel structures 55 are in the element 58 as shown in Fig 10, hereinafter 2VCS) that extends in the second stack (32/46 of 902, Fig 19 of Ogawa ‘878, Para [0099]), and a second bonding pad (98 of 2VCS, Fig 19 and annotated Fig 22B of Ogawa ‘878, Para [0122]) that is on a lower surface (bottom of 2VCS as shown in annotated Fig 19 of Ogawa ‘878) of the second vertical channel structure (2VCS) and is electrically connected (disclosed in Para [0097]) to the second vertical channel structure (2VCS), and
wherein the first bonding pad (98 of 1VCS) and the second bonding pad (98 of 2VCS) are electrically connected to each other (disclosed in Para [0104]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ogawa ‘878’s teaching of wherein the bottom structure further comprises a first vertical channel structure that extends in the first stack, and a first bonding pad that is on the first vertical channel structure and is electrically connected to the first vertical channel structure, wherein the top structure further comprises a second vertical channel structure that extends in the second stack, and a second bonding pad that is on a lower surface of the second vertical channel structure and is electrically connected to the second vertical channel structure, and wherein the first bonding pad and the second bonding pad are electrically connected to each other into Tang ‘482’s device. Tang ‘482 teaches a three-dimensional semiconductor memory device with a cell array region and a connection region and Tang ‘482 is open to the details of the cell array region. Ogawa ‘878 also teaches a three-dimensional semiconductor memory device with a cell array region and a connection region and provides details on the structure of the cell array region. The ordinary artisan would have been motivated to modify Tang ‘482 in the manner set forth above, at least, because this the details of the cell array region taught by Ogawa ‘878 would reduce the amount of research and development time and money a person of ordinary skill in the art would need to determine the structure of the cell array region.
As incorporated, the teaching of Ogawa ‘878 of a first vertical channel structure in the first stack, a first bonding pad on the first vertical channel structure electrically connected to the first vertical channel structure, a second vertical channel structure in the second stack, a second bonding pad on the second vertical channel structure electrically connected to the second vertical channel structure wherein the first bonding pad and the second bonding pad are electrically connected to each other, as described above would be used in the cell array region (CAR) of Tang ‘482.
With respect to Claim 3 Tang ‘482 as modified by Ogawa ‘878 discloses all limitations of the semiconductor memory device of claim 2, and Ogawa ‘878 further discloses wherein a width (width of 1VCS) of the first vertical channel structure (1VCS) in the second direction (second direction as shown in annotated Fig 19 of Ogawa ‘878, hereinafter 2D) increases as a distance in the first direction (first direction as shown in annotated Fig 19 of Ogawa ‘878, hereinafter 1D) from the bottom surface (bottom of 712) of the semiconductor substrate (712) increases (Para [0065] discloses opening 49 wherein vertical channel structures are formed as tapered, therefore the width of 1VCS would increase in second direction as the as the distance from bottom of 712 along 1D increases), and
wherein a width (width of 2VCS) of the second vertical channel structure (2VCS) in the second direction (2D) decreases as a distance in the first direction (1D) from the bottom surface (bottom of 712) of the semiconductor substrate (712) increases (Para [0065] discloses opening 49 wherein vertical channel structures are formed as tapered, therefore the width of 2VCS, being inverted, would decrease in second direction as the as the distance from bottom of 712 along 1D increases).
With respect to Claim 4 Tang ‘482 as modified by Ogawa ‘878 discloses all limitations of the semiconductor memory device of claim 2, wherein the top structure (902) further comprises a bit line (92, Fig 22B of Ogawa ‘878, Para [0122]) on the second vertical channel structure (2VCS as shown in annotated Fig 22B of Ogawa ‘878), and an upper conductive pad (88 of 901, Fig 10 of Ogawa ‘878, Para [0097] discloses 88 connected to 55 and 92) between (shown in annotated Fig 19 of Ogawa ‘878 and disclosed in Para [0097]) the second vertical channel structure (2VCS) and the bit line (92), and
wherein the second vertical channel structure (2VCS) is electrically connected (disclosed in Para [0097]) to the bit line (92) through the upper conductive pad (88 of 901).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ogawa ‘878’s further teaching of the top structure further comprises a bit line on the second vertical channel structure, and an upper conductive pad between the second vertical channel structure and the bit line, and wherein the second vertical channel structure is electrically connected to the bit line through the upper conductive pad into Tang ‘482 as modified by Ogawa ‘878’s device. The ordinary artisan would have been motivated to further modify Tang ‘482 as modified by Ogawa ‘878 in the manner set forth above, at least, because these teachings provide further detail on the structure of the cell array region that would again reduce the amount of research and development time and money a person of ordinary skill in the art would need to determine the structure of the cell array region.
As incorporated, the further teaching of Ogawa ‘878 of the top structure further comprises a bit line on the second vertical channel structure, and an upper conductive pad between the second vertical channel structure and the bit line, and wherein the second vertical channel structure is electrically connected to the bit line through the upper conductive pad, as described above would be used in the cell array region (CAR) of Tang ‘482 as modified by Ogawa ‘878.
With respect to Claim 5 Tang ‘482 as modified by Ogawa ‘878 discloses all limitations of the semiconductor memory device of claim 2, and Ogawa ‘878 discloses further comprising:
a first channel plug (63 in 55 of 901, Fig 4H of Ogawa ‘878, Para [0076]) between the first vertical channel structure (1VCS) and the first bonding pad (98 of 1VCS), wherein the first vertical channel structure (1VCS) is electrically connected (Para [0094] of Ogawa ‘878 discloses 63 electrically connected to 88 and Para [0097] discloses 88 connected to 92 and Para [0122] discloses 92 connected to 98) to the first bonding pad (98 of 1VCS) through the first channel plug (63 in 55 of 901)(connection of 63 and 98 described above); and
a second channel plug (63 in 55 of 902, Fig 4H of Ogawa ‘878, Para [0076]) between the second vertical channel structure (2VCS) and the second bonding pad (98 of 2VCS), wherein the second vertical channel structure (2VCS) is electrically connected (Para [0094] discloses 63 electrically connected to 88 and Para [0097] discloses 88 connected to 92 and Para [0122] discloses 92 connected to 98) to the second bonding pad (98 of 2VCS) through the second channel plug (63 in 55 of 902)(connection of 63 and 98 described above).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ogawa ‘878’s further teaching of a first channel plug between the first vertical channel structure and the first bonding pad, wherein the first vertical channel structure is electrically connected to the first bonding pad through the first channel plug; and a second channel plug between the second vertical channel structure and the second bonding pad, wherein the second vertical channel structure is electrically connected to the second bonding pad through the second channel plug into Tang ‘482 as modified by Ogawa ‘878’s device. The ordinary artisan would have been motivated to further modify Tang ‘482 as modified by Ogawa ‘878 in the manner set forth above, at least, because these teachings provide further detail on the structure of the cell array region that would again reduce the amount of research and development time and money a person of ordinary skill in the art would need to determine the structure of the cell array region.
As incorporated, the further teaching of Ogawa ‘878 a first channel plug between the first vertical channel structure and the first bonding pad, wherein the first vertical channel structure is electrically connected to the first bonding pad through the first channel plug; and a second channel plug between the second vertical channel structure and the second bonding pad, wherein the second vertical channel structure is electrically connected to the second bonding pad through the second channel plug, as described above would be used in the cell array region (CAR) of Tang ‘482 as modified by Ogawa ‘878.
With respect to Claim 6 Tang ‘482 as modified by Ogawa ‘878 discloses all limitations of the semiconductor memory device of claim 1, and Tang ‘482 further discloses wherein the first gate electrodes (114) comprise respective first pad portions (pad portion where contact 122 contacts 114 as shown in annotated Fig 2 of Tang ‘482, hereinafter 1PP) on the connection region (CNR),
wherein the bottom structure (BS) further comprises:
a first cell contact plug (rightmost 122 as shown in annotated Fig 2 of Tang ‘482) that extends in the first direction (D1) and is electrically connected to (122 electrically connected to 114 disclosed in Para [0048]) one of the first pad portions (1PP)(122 connecting to 1PP of 114 disclosed in annotated Fig 2 of Tang ‘482); and
wherein the top structure (TS) further comprises:
a first penetration electrode (CS1) (Note Examiner’s interpretation, above, of “a first penetration electrode” as “the first penetration electrode”) and extends in the first direction (D1); and
And Ogawa ‘878 further teaches a first bonding pad (98 of 86, as shown in annotated Fig 19 of Ogawa ‘878, Para [0122]) that is on the first cell contact plug (86 of 901, as shown in annotated Fig 19 of Ogawa ‘878, Para [0123]) and is electrically connected (disclosed in Para [0123]) to the first cell contact plug (86 of 901), a first penetration electrode (82 of 902, as shown in annotated Fig 19 of Ogawa ‘878, Para [0094]) (Note Examiner’s interpretation, above, of “a first penetration electrode” as “the first penetration electrode”) that is on the first bonding pad (98 of 86)(annotated Fig 19 of Ogawa ‘878 discloses first penetration electrode on first bonding pad of first cell contact plug), a second bonding pad (98 of 82, as shown in annotated Fig 19 of Ogawa ‘878) that is between the first bonding pad (98 of 86 as shown in annotated Fig 19 of Ogawa ‘878) and the first penetration electrode (82 of 902) and is electrically connected (Para [0094] discloses 82 electrically connected to 88 and Para [0097] discloses 88 connected to 92 and Para [0122] discloses 92 connected to 98) to the first penetration electrode (82 of 902), and wherein the first bonding pad (98 of 86) and the second bonding pad (98 of 82) are electrically connected to each other (Para [0103 and 0104] discloses pad 98s are bonded, therefore electrically connected).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ogawa ‘878’s further teaching of a first bonding pad that is on the first cell contact plug and is electrically connected to the first cell contact plug, the first penetration electrode that is on the first bonding pad, a second bonding pad that is between the first bonding pad and the first penetration electrode and is electrically connected to the first penetration electrode, and wherein the first bonding pad and the second bonding pad are electrically connected to each other into Tang ‘482 as modified by Ogawa ‘878’s device. The ordinary artisan would have been motivated to modify Tang ‘482 as modified by Ogawa ‘878 in the manner set forth above, at least, because the teaching of the bond pad on the electrodes and contact plugs would provide a larger area to connect the electrodes and contact plugs thereby improving the ability to make good electrical connections which would increase device yield and reliably.
As incorporated, the further teaching of Ogawa ‘878 of the use of bond pads would be used on the cell contact plug (122) and the penetration electrode (CS1) of Tang ‘482 as modified by Ogawa ‘878 such that cell contact plug (122) is electrically connected to the first cell contact plug (rightmost 122), and the first bonding pad (98 of 86) and the second bonding pad (98 of 82) of Ogawa ‘878 are electrically connected.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Tang ‘482 in view of Ogawa ‘878 in further view of Park et al. (US 2020/0105735 A1, hereinafter Park ‘735), in view of the following arguments.
With respect to Claim 8 Tang ‘482 as modified by Ogawa ‘878 discloses all limitations of the semiconductor memory device of claim 6, but Tang ‘482 as modified by Ogawa ‘878 fails to explicitly disclose wherein a width of the first cell contact plug in the second direction increases as a distance in the first direction from the bottom surface of the semiconductor substrate increases, and
wherein a width of the first penetration electrode in the second direction decreases as a distance in the first direction from the bottom surface of the semiconductor substrate increases.
Nevertheless, in a related endeavor (Fig 4 and 12 of Park ‘735), Park ‘735 teaches wherein a width (width of 260) of the first cell contact plug (260, Fig 4 of Park ‘735, Para [0056]) in the second direction (X as shown in Fig 4 of Park ‘735) increases as a distance in the first direction (Z as shown in Fig 4 of Park ‘735) from the bottom surface (bottom of 201) of the semiconductor substrate (201, Fig 4 of Park ‘735, Para [0040]) increases (Fig 4 and Para [0056] disclose plugs 260 are tapered, therefore the width of the via will increase in the second direction as the distance from the bottom of 201 increases in the first direction), and wherein a width (width of 261) of the first penetration electrode (top of 261, Fig 12 of Park ‘735, Para [0040]) in the second direction (X direction) decreases as a distance in the first direction (Z direction) from the bottom surface (bottom of 201) of the semiconductor substrate (201) increases (Fig 12 and Para [0056] disclose plugs 261 are tapered, therefore the width of the via will decrease in the second direction as the distance from the bottom of 201 increases in the first direction).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Park ‘735’steaching of a width of the first cell contact plug in the second direction increases as a distance in the first direction from the bottom surface of the semiconductor substrate increases, and wherein a width of the first penetration electrode in the second direction decreases as a distance in the first direction from the bottom surface of the semiconductor substrate increases into Ogawa ‘878’s device. Ogawa ‘878 teaches a memory device with contacts to the structure. Park ‘735 also teaches a memory device with contacts and teaches tapering the shape of the contact as it gets deeper in the structure. The ordinary artisan would have been motivated to modify Ogawa ‘878 in the manner set forth above, at least, because tapering the shape of the contacts as the contact gets deeper into the structure would help to keep contacts from making unwanted contacts with parts of the structure, as one of ordinary skill in the art will know that spacing between structures reduces the deeper in the structure.
As incorporated, the teaching of Park ‘735 of forming contacts with tapered side walls would be used in the contact plugs (86) and penetration electrodes (82) of Ogawa ‘878.
Allowable Subject Matter
Claims 12-15 are allowed.
Claims 7 and 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding Claims 12-15: Allowable subject matter has been indicated because the closest prior art of record, either alone or in combination, fails to teach or fairly suggest the feature: “an interconnection layer on the second cell array structure” and “a first penetration electrode that is laterally spaced apart from the second stack and is electrically connected to the cell contact plug, the first penetration electrode vertically overlapping the cell contact plug” along with the rest of the limitations of said claims.
Closest prior art of record Tang ‘482 teaches a three-dimensional semiconductor memory system with a bottom memory stack structure and a top memory stack structure. Tang ‘482 further teaches that the top memory stack structure has a horizontal offset in a vertical direction from the bottom memory stack structure which enables a first penetration electrode, electrically connected to a cell contact plug to vertically overlap. However, Tang ‘482 fails to disclose an interconnection layer on the second cell array structure. Tang teaches a connection layer between the bottom memory stack structure and a top memory stack structure.
Closest prior art of record Ogawa ‘878 teaches a three-dimensional semiconductor memory system with a bottom memory stack structure and a top memory stack structure. Ogawa ‘878 further teaches an interconnection layer on the second cell array structure. However, Ogawa ‘878 fails to disclose “a first penetration electrode that is laterally spaced apart from the second stack and is electrically connected to the cell contact plug, the first penetration electrode vertically overlapping the cell contact plug”. Ogawa ‘878 fails to disclose the horizontal offset in a vertical direction of the upper memory stack structure and the bottom memory stack structure which would allow the vertical overlap of the cell contact plug and first penetration electrode. Further it is not obvious to modify the structure of Tang ‘482 having the connection region between the upper memory stack structure and the bottom memory stack structure with the interconnect region above the upper memory stack structure as taught by Ogawa ‘878.
Regarding Claim 7: Allowable subject matter has been indicated because the closest prior art of record, either alone or in combination, fails to teach or fairly suggest the feature: “wherein the top structure further comprises an interconnection layer on the first penetration electrode, and a first conductive line between the first penetration electrode and the interconnection layer” along with the rest of the limitations of said claims.
Closest prior art of record Tang ‘482 teaches a three-dimensional semiconductor memory system with a bottom memory stack structure and a top memory stack structure. Tang ‘482 further teaches that the top memory stack structure has a horizontal offset in a vertical direction from the bottom memory stack structure which enables a first penetration electrode, electrically connected to a cell contact plug to vertically overlap. However, Tang ‘482 fails to disclose an interconnection layer and a first conductive line between the first penetration electrode and the interconnection layer on the second cell array structure. Tang teaches a connection layer between the bottom memory stack structure and a top memory stack structure.
Closest prior art of record Ogawa ‘878 teaches a three-dimensional semiconductor memory system with a bottom memory stack structure and a top memory stack structure. Ogawa ‘878 further teaches an interconnection layer on the second cell array structure. However, Ogawa ‘878 fails to disclose obvious motivation to modify the structure of Tang ‘482 having the connection region between the upper memory stack structure and the bottom memory stack structure with the interconnect region above the upper memory stack structure as taught by Ogawa ‘878.
Regarding Claims 9-11: Allowable subject matter has been indicated because the closest prior art of record, either alone or in combination, fails to teach or fairly suggest the feature: “wherein the redistribution layer comprises a first redistribution pattern electrically connected to the second cell contact plug, and a second redistribution pattern electrically connected to the second penetration electrode” along with the rest of the limitations of said claims.
Closest prior art of record Tang ‘482 teaches a three-dimensional semiconductor memory system with a bottom memory stack structure and a top memory stack structure. Tang ‘482 further teaches that the top memory stack structure has a horizontal offset in a vertical direction from the bottom memory stack structure which enables a first penetration electrode, electrically connected to a cell contact plug to vertically overlap and Tang ‘482 teaches a direction connection of the penetration electrodes and cell contact plugs in the connection layer between the bottom memory stack structure and a top memory stack structure. However, Tang ‘482 fails to disclose a redistribution layer comprises a first redistribution pattern electrically connected to the second cell contact plug, and a second redistribution pattern electrically connected to the second penetration electrode.
Closest prior art of record Ogawa ‘878 teaches a three-dimensional semiconductor memory system with a bottom memory stack structure and a top memory stack structure. Ogawa ‘878 further teaches a redistribution layer between the upper and lower memory cell structures. However, Ogawa ‘878 fails to disclose obvious motivation to modify the direct connection of the penetration electrode and the cell contact plugs in the connection layer structure of Tang ‘482 with the muti-layer redistribution layer structure as taught by Ogawa ‘878.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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