DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following items from the applicant: Information Disclosure Statement (IDS) filed on 11 September 2023 and 27 November 2024. The references cited on the PTOL 1449 form have been considered.
Drawings
The drawings are objected to because:
Fig. 1 shows does not properly depict reference character “100” of the semiconductor device. In the figure, it is shown as “10” on one line and “0” on the next line, which is not clear. It appears that the reference character should read “100” on the same line.
Fig. 2 shows does not properly depict reference character “130” of the semiconductor device. In the figure, it is shown as “13” on one line and “0” on the next line, which is not clear. It appears that the reference character should read “130” on the same line.
Fig. 6 cross-sectional view C incorrectly recites reference character “204” and should read “304” for the identifier line on the left-side active region.
Fig. 6 cross-sectional view C is missing the reference character “306” for the identifier line on the right-side active region.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites “the first electrical connection,” which makes unclear as to which first electrical connection is being referenced as claim 17 requires both the first component to include a first electrical connection and the second component to include a first electrical connection.
Claim 20 also recites “the second electrical connection,” which makes unclear as to which second electrical connection is being referenced as claim 17 requires both the first component to include a second electrical connection and the second component to include a second electrical connection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5-8 and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morrow et al. (U.S. Patent Application Publication 2018/0248012).
Referring to Claim 1, Morrow teaches in Fig. 3 for example, a semiconductor device, comprising: a top side and a bottom side opposite the top side; a central portion including a semiconductor substrate (310; par. 10, 11, 18) disposed between the top side and the bottom side; and a component (318) disposed in the central portion on the semiconductor substrate (310), the component (318) including a first electrical connection (330) from the top side and a second electrical connection (320) from the bottom side.
Referring to Claim 5, Morrow further teaches wherein the component (318) includes an active region (318) and the first electrical connection (330) connects to a top portion (321) of the active region (318) and the second electrical connection (320) connects to a bottom portion (319) of the active region (318) opposite the top portion (321).
Referring to Claim 6, Morrow further teaches wherein the active region (318) includes a source/drain region (par. 34) of a transistor device (322).
Referring to Claim 7, Morrow further teaches wherein the active region (318) includes a source/drain region (318) of a stacked field effect transistor device (par. 1).
Referring to Claim 8, Morrow teaches in Fig. 3 for example, a semiconductor device, comprising: top side wiring including metal lines and contacts (335); bottom side wiring including metal lines and contacts (325) and disposed opposite the top side wiring; a central portion including a semiconductor substrate (310; par. 10, 11 and 18) disposed between the top side wiring and the bottom side wiring; and a component (318) formed on the semiconductor substrate (310) and disposed in the central portion; the component (318) including a first electrical connection (330) from the top side wiring and a second electrical connection (320) from the bottom side wiring.
Referring to Claim 12, Morrow further teaches wherein the component (318) includes an active region (318) and the first electrical connection (330) connects to a top portion (321) of the active region (318) and the second electrical connection (320) connects to a bottom portion (319) of the active region (318) opposite the top portion (321).
Referring to Claim 13, Morrow further teaches wherein the active region (318) includes a source/drain region (par. 34) of a transistor device.
Referring to Claim 14, Morrow further teaches wherein the active region (318) includes a source/drain region (318) of a stacked field effect transistor device (par. 1).
Claims 1, 3-8, 10-17, 20-22 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bernstein et al. (U.S. Patent Application Publication 2007/0267723).
Referring to Claim 1, Bernstein teaches in Fig. 1J or Fig. 2 for example, a semiconductor device, comprising: a top side and a bottom side opposite the top side; a central portion including a semiconductor substrate (105A/105B) disposed between the top side and the bottom side; and a component (135) disposed in the central portion on the semiconductor substrate (105A/105B), the component (135) including a first electrical connection (210) from the top side and a second electrical connection (160; see Fig. 1C) from the bottom side.
Referring to Claim 3, Bernstein further teaches wherein the top side includes symmetrical metal structures (180, 190) relative to the bottom side (in layers 175 and 185).
Referring to Claim 4, Bernstein further teaches, in Fig. 2, wherein the first electrical connection (210) connects to the second electrical connection (160) across the central portion by a through contact (220 – via 160, 170, 180).
Referring to Claim 5, Bernstein further teaches wherein the component (135) includes an active region (135) and the first electrical connection (210) connects to a top portion of the active region (135) and the second electrical connection (160) connects to a bottom portion of the active region (135) opposite the top portion.
Referring to Claim 6, Bernstein further teaches wherein the active region (135) includes a source/drain region of a transistor device (par. 24).
Referring to Claim 7, Bernstein further teaches wherein the active region (135) includes a source/drain region (135) of a stacked field effect transistor device.
Referring to Claim 8, Bernstein teaches in Fig. 1J or 2 for example, a semiconductor device, comprising: top side wiring including metal lines and contacts (upper 180 and 190 in upper layers 175 and 185); bottom side wiring including metal lines and contacts (lower 180 and 190 in lower layers 175 and 185) and disposed opposite the top side wiring; a central portion including a semiconductor substrate (105A/105B) disposed between the top side wiring and the bottom side wiring; and a component (135) formed on the semiconductor substrate (105A/105B) and disposed in the central portion; the component (135) including a first electrical connection (210) from the top side wiring and a second electrical connection (160; see Fig. 1C) from the bottom side wiring.
Referring to Claim 10, Bernstein further teaches wherein the top side wiring and the bottom side wiring include symmetrical metal structures (180, 190) relative to one another.
Referring to Claim 11, Bernstein further teaches wherein the first electrical connection (240) connects to the second electrical connection (160) across the central portion by a through contact (220) that traverses the semiconductor substrate (105A/105B).
Referring to Claim 12, Bernstein further teaches wherein the component (135) includes an active region (135) and the first electrical connection (210) connects to a top portion of the active region (135) and the second electrical connection (160) connects to a bottom portion of the active region (135) opposite the top portion.
Referring to Claim 13, Bernstein further teaches wherein the active region (135) includes a source/drain region of a transistor device (par. 24).
Referring to Claim 14, Bernstein further teaches wherein the active region (135) includes a source/drain region (135) of a stacked field effect transistor device.
Referring to Claim 15, Bernstein further teaches wherein the top side wiring (upper 180 and 190) mirrors the bottom side wiring (lower 180 and 190) relative to the central portion.
Referring to Claim 16, Bernstein further teaches wherein the top side wiring mirrors (upper 180 and 190) the bottom side wiring (lower 180 and 190) in three dimensions.
Referring to Claim 17, Bernstein teaches in Fig. 1J for example, a semiconductor device, comprising: top side wiring including metal lines and contacts (upper 180 and 190); bottom side wiring including metal lines and contacts (lower 180 and 190) and disposed opposite the top side wiring; a central portion including a semiconductor substrate (105A/105B) disposed between the top side wiring and the bottom side wiring; a first component (135) formed on the semiconductor substrate (105A/105B) and disposed in the central portion, the first component (135) including a first electrical connection (210) from the top side wiring and a second electrical connection (160; see Fig. 1C) from the bottom side wiring; a second component (150) formed on the semiconductor substrate (105A/105B) and disposed in the central portion, the second component (150) including a first electrical connection (210; see Fig. 1I) from the top side wiring and a second electrical connection (160; see Fig. 1C) from the bottom side wiring; and a bridge (170) connecting the first electrical connection (210) of the first component (135) to the first electrical connection (210) of the second component (150).
Referring to Claim 20, Bernstein further teaches wherein the second component (150) includes an active region (150; par. 24) and the first electrical connection (210) connects to a top portion of the active region (150) and the second electrical connection (160) connects to a bottom portion of the active region (150) opposite the top portion.
Referring to Claim 21, Bernstein further teaches wherein the top side wiring (upper 180, 190) mirrors the bottom side wiring (lower 180, 190) relative to the central portion.
Referring to Claim 22, Bernstein teaches in Fig. 1J for example, a semiconductor device, comprising: top side wiring including metal lines and contacts (upper 180, 190); bottom side wiring including metal lines and contacts (lower 180, 190) and disposed opposite the top side wiring; a central portion including a semiconductor substrate (105A/105B) disposed between the top side wiring and the bottom side wiring; a first circuit disposed in the top side wiring and the bottom side wiring, the first circuit including a first component (135) including a first electrical connection (210) from the top side wiring and a second electrical connection (160) from the bottom side wiring; a second circuit disposed in the top side wiring and the bottom side wiring, the second circuit including a second component (150) including a first electrical connection (210) from the top side wiring and a second electrical connection (160) from the bottom side wiring; and a bridge (170) connecting the first circuit to the second circuit to form a single circuit across the top side wiring, bottom side wiring and the central portion, wherein the top side wiring (upper 180, 190) mirrors the bottom side wiring (lower 180, 190) relative to the central portion.
Referring to Claim 25, Bernstein further teaches wherein the second component (150) includes an active region (150; par. 24) and the first electrical connection (210) of the second component (150) connects to a top portion of the active region (150) and the second electrical connection (160) of the second component (150) connects to a bottom portion of the active region (150) opposite the top portion.
Claims 1-3, 8-10 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated Li et al. (U.S. Patent Application Publication 2024/0021586).
Referring to Claim 1, Li teaches in Fig. 1 for example, a semiconductor device, comprising: a top side and a bottom side opposite the top side; a central portion including a semiconductor substrate (108) disposed between the top side and the bottom side; and a component (118) disposed in the central portion on the semiconductor substrate, the component (118) including a first electrical connection (8) from the top side and a second electrical connection (5) from the bottom side.
Referring to Claim 2, Li further teaches wherein the component (118) includes a gate structure (118) and the first electrical connection (8) connects to a top portion of the gate structure (118) and the second electrical connection (5) connects to a bottom portion of the gate structure (118) opposite the top portion.
Referring to Claim 3, Li further teaches wherein the top side includes symmetrical metal structures (vias 7/9 and 2/4; or contacts 6/7 and 3/4) relative to the bottom side. The manner in which the claim is written does not define any specificity as to the total quantity of metal structures nor how many should be symmetrical.
Referring to Claim 8, Li teaches in Fig. 1 for example, a semiconductor device, comprising: top side wiring including metal lines and contacts (6 and 7); bottom side wiring including metal lines and contacts (3 and 4) and disposed opposite the top side wiring; a central portion including a semiconductor substrate (108) disposed between the top side wiring and the bottom side wiring; and a component (118) formed on the semiconductor substrate (108) and disposed in the central portion; the component (118) including a first electrical connection (8) from the top side wiring and a second electrical connection (5) from the bottom side wiring.
Referring to Claim 9, Li further teaches wherein the component includes a gate structure (118) and the first electrical connection (8) connects to a top portion of the gate structure (118) and the second electrical connection (5) connects to a bottom portion of the gate structure (118) opposite the top portion.
Referring to Claim 10, Li further teaches wherein the top side wiring and the bottom side wiring include symmetrical metal structures (6 and 3) relative to one another.
Referring to Claim 15, Li further teaches wherein the top side wiring (6 and 7) mirrors the bottom side wiring (3 and 4) relative to the central portion.
Allowable Subject Matter
Claims 18, 19, 23 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 18, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device wherein the first component includes a gate structure and the first electrical connection connects to a top portion of the gate structure and the second electrical connection connects to a bottom portion of the gate structure opposite the top portion in combination with all of the limitations of claims 17 and 18.
Regarding Claim 19, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device wherein the first electrical connection connects to the second electrical connection across the central portion by a respective through contact that traverses the semiconductor substrate in combination with all of the limitations of claims 17 and 19.
Regarding Claim 23, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device wherein the first component includes a gate structure and the first electrical connection of the first component connects to a top portion of the gate structure and the second electrical connection of the first component connects to a bottom portion of the gate structure opposite the top portion in combination with all of the limitations of claims 22 and 23.
Regarding Claim 24, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device wherein the first electrical connection connects to the second electrical connection across the central portion by a respective through contact that traverses the semiconductor substrate in combination with all of the limitations of claims 22 and 24.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896
1. A semiconductor device, comprising:
a top side and a bottom side opposite the top side;
a central portion including a semiconductor substrate disposed between the top side and the bottom side; and
a component disposed in the central portion on the semiconductor substrate, the component including a first electrical connection from the top side and a second electrical connection from the bottom side.
2. The semiconductor device as recited in claim 1, wherein the component includes a gate structure and the first electrical connection connects to a top portion of the gate structure and the second electrical connection connects to a bottom portion of the gate structure opposite the top portion.
3. The semiconductor device as recited in claim 1, wherein the top side includes symmetrical metal structures relative to the bottom side.
4. The semiconductor device as recited in claim 1, wherein the first electrical connection connects to the second electrical connection across the central portion by a through contact.
5. The semiconductor device as recited in claim 1, wherein the component includes an active region and the first electrical connection connects to a top portion of the active region and the second electrical connection connects to a bottom portion of the active region opposite the top portion.
6. The semiconductor device as recited in claim 5, wherein the active region includes a source/drain region of a transistor device.
7. The semiconductor device as recited in claim 5, wherein the active region includes a source/drain region of a stacked field effect transistor device.
8. A semiconductor device, comprising:
top side wiring including metal lines and contacts; bottom side wiring including metal lines and contacts and disposed opposite the top side wiring;
a central portion including a semiconductor substrate disposed between the top side wiring and the bottom side wiring; and a component formed on the semiconductor substrate and disposed in the central portion;
the component including a first electrical connection from the top side wiring and a second electrical connection from the bottom side wiring.
9. The semiconductor device as recited in claim 8, wherein the component includes a gate structure and the first electrical connection connects to a top portion of the gate structure and the second electrical connection connects to a bottom portion of the gate structure opposite the top portion.
10. The semiconductor device as recited in claim 9, wherein the top side wiring and the bottom side wiring include symmetrical metal structures relative to one another.
11. The semiconductor device as recited in claim 8, wherein the first electrical connection connects to the second electrical connection across the central portion by a through contact that traverses the semiconductor substrate.
12. The semiconductor device as recited in claim 8, wherein the component includes an active region and the first electrical connection connects to a top portion of the active region and the second electrical connection connects to a bottom portion of the active region opposite the top portion.
13. The semiconductor device as recited in claim 12, wherein the active region includes a source/drain region of a transistor device.
14. The semiconductor device as recited in claim 12, wherein the active region includes a source/drain region of a stacked field effect transistor device.
15. The semiconductor device as recited in claim 8, wherein the top side wiring mirrors the bottom side wiring relative to the central portion.
16. The semiconductor device as recited in claim 8, wherein the top side wiring mirrors the bottom side wiring in three dimensions.
17. A semiconductor device, comprising:
top side wiring including metal lines and contacts;
bottom side wiring including metal lines and contacts and disposed opposite the top side wiring;
a central portion including a semiconductor substrate disposed between the top side wiring and the bottom side wiring;
a first component formed on the semiconductor substrate and disposed in the central portion, the first component including a first electrical connection from the top side wiring and a second electrical connection from the bottom side wiring;
a second component formed on the semiconductor substrate and disposed in the central portion, the second component including a first electrical connection from the top side wiring and a second electrical connection from the bottom side wiring; and
a bridge connecting the first electrical connection of the first component to the first electrical connection of the second component.
18. The semiconductor device as recited in claim 17, wherein the first component includes a gate structure and the first electrical connection connects to a top portion of the gate structure and the second electrical connection connects to a bottom portion of the gate structure opposite the top portion.
19. The semiconductor device as recited in claim 17, wherein the first electrical connection connects to the second electrical connection across the central portion by a respective through contact that traverses the semiconductor substrate.
20. The semiconductor device as recited in claim 17, wherein the second component includes an active region and the first electrical connection connects to a top portion of the active region and the second electrical connection connects to a bottom portion of the active region opposite the top portion.
21. The semiconductor device as recited in claim 17, wherein the top side wiring mirrors the bottom side wiring relative to the central portion.
22. A semiconductor device, comprising:
top side wiring including metal lines and contacts;
bottom side wiring including metal lines and contacts and disposed opposite the top side wiring;
a central portion including a semiconductor substrate disposed between the top side wiring and the bottom side wiring;
a first circuit disposed in the top side wiring and the bottom side wiring, the first circuit including a first component including a first electrical connection from the top side wiring and a second electrical connection from the bottom side wiring;
a second circuit disposed in the top side wiring and the bottom side wiring, the second circuit including a second component including a first electrical connection from the top side wiring and a second electrical connection from the bottom side wiring; and
a bridge connecting the first circuit to the second circuit to form a single circuit across the top side wiring, bottom side wiring and the central portion, wherein the top side wiring mirrors the bottom side wiring relative to the central portion.
23. The semiconductor device as recited in claim 22, wherein the first component includes a gate structure and the first electrical connection of the first component connects to a top portion of the gate structure and the second electrical connection of the first component connects to a bottom portion of the gate structure opposite the top portion.
24. The semiconductor device as recited in claim 22, wherein the first electrical connection connects to the second electrical connection across the central portion by a respective through contact that traverses the semiconductor substrate.
25. The semiconductor device as recited in claim 22, wherein the second component includes an active region and the first electrical connection of the second component connects to a top portion of the active region and the second electrical connection of the second component connects to a bottom portion of the active region opposite the top portion.