Prosecution Insights
Last updated: May 29, 2026
Application No. 18/464,511

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Non-Final OA §103§112
Filed
Sep 11, 2023
Priority
Nov 29, 2022 — JP 2022-189975
Examiner
LEE, EUGENE
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mitsubishi Electric Corporation
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
737 granted / 900 resolved
+13.9% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
26 currently pending
Career history
935
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
73.4%
+33.4% vs TC avg
§102
10.6%
-29.4% vs TC avg
§112
2.7%
-37.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 900 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I, Species III, FIG. 10 (claims 1, 2, 6, and 7) in the reply filed on 3/18/26 is acknowledged. Claims 3-5, and 8-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/18/26. Drawings The drawings are objected to because it is unclear how FIG. 2 shows the same structure in FIG. 1. According to paragraph [0017] of the specification, FIG. 1 shows a cross section of FIG. 2 along the line A-A; however, it is unclear how the first lead frame 104 can be shown in FIG. 1 when the line A-A in FIG. 2 does not cross the first lead frame 104. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1, 2, 6, and 7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In lines 5-7 of claim 1, the applicant states “a semiconductor element including a first surface … a first electrode disposed on the first surface,”; however, it is unclear how the first electrode is disposed on a first surface of a semiconductor element. See, for example, FIG. 2 wherein the applicant shows the semiconductor element 14 including a first surface 14a, but the first electrode 144 is only on the heat spreader 15, and is not on the semiconductor element 14. Further, it is unknown how the first lead frame 104 can appear in FIG. 1 when FIG. 2 shows the cross-section A-A not including the first lead frame 104. Also see the Drawing Objection above. Appropriate clarification and/or correction are required. The same applies to claim 2, which contains the same limitation. In lines 18-21 of claim 1, the applicant states “the sealant … sealing the first lead frame with the first lead frame being partly exposed opposite to the heat spreader,”; however, it is unclear what direction “opposite” is referring to. For example, in FIG. 24, the applicant shows the first lead frame 104 that is on a heat spreader 15, but it is unclear how the term “opposite” further distinguishes the structure as any structure that is not part of the heat spreader could be widely interpreted as “opposite” to the heat spreader. Appropriate clarification and/or correction are required. The same applies to claim 2, which contains the same limitation. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. In view of 112 rejection, claim(s) 1, 2, 6, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujino et al. US 2019/0189537 A1 in view of JP 2021-111765 A1 (published on 8/2/2021) as disclosed by the applicant’s IDS filed 2/9/26. Fujino discloses (see, for example, FIG. 7) a semiconductor device 200 comprising a heat spreader 11, second solder layer 31, semiconductor element 21, first surface (i.e. bottom surface), second surface (i.e. top surface), first electrode (see, for example, paragraph [0039]), second electrode (see, for example, paragraph [0039]), block 61, sheet 10/13, first portion 13, second portion 10, first lead frame 67, second lead frame 68, and sealant 71. In paragraph [0036], Fujino discloses the heat spreader 11 may include copper or copper alloy. In paragraph [0042], Fujino discloses the block 61 may include copper or copper alloy. In paragraph [0034], Fujino discloses the first portion 13 may include copper, and the second portion 10 may include insulating properties. In paragraph [0054], Fujino discloses the first lead frame 67 includes copper, etc. In paragraph [0101], Fujino discloses the second lead frame 68 may include copper plating. In FIG. 7, Fujino discloses the sealant 71 sealing the sheet 10/13 with at least a part of the first portion 13 being exposed, sealing the first lead frame 67 with the first lead frame 67 being partly exposed opposite to the heat spreader 11, sealing the second lead frame 68 with the second lead frame 68 being partly exposed opposite to the block 61, and sealing the heat spreader 11, the second solder layer 31, the semiconductor element 21, and the block 61. Regarding the limitation “first electrode”, see, for example, paragraph [0039] wherein Fujino discloses the semiconductor element 21 having a bottom surface having a back electrode (i.e. first electrode), and a top surface having a front electrode (i.e. second electrode). Fujino does not disclose a first solder layer. However, JP 2021-111765 A1 discloses (see, for example, figure 1) a semiconductor device 100 comprising a first solder layer 2b connected to a semiconductor element 1b and heat spreader 3. In the applicant’s translation, it is stated in paragraph [0020] that the first solder layer 2b includes a solder bonding material or the like. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a first solder layer in order to improve the adhesion between the semiconductor element and the heat spreader. Fujino does not disclose the first lead frame welded to the heat spreader. However, JP 2021-111765 A discloses a semiconductor device 100 comprising a first lead frame 4a that is welded to a heat spreader 3. In paragraph [0039], the applicant’s translation states using welding to connect the heat spreader 3 and first lead frame 4a. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the first lead frame welded to the heat spreader in order to improve stability of the first lead frame within the semiconductor device, and further improve heat dissipation outside the semiconductor device. Fujino does not specifically disclose the sealant having a linear coefficient of expansion more than or equal to 11 ppm/K and less than or equal to 21 ppm/K. However, JP 2021-111765 A discloses (see, for example, paragraph [0048]) a sealant 9 having a linear coefficient of expansion from 11 ppm to 19 ppm/K. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the sealant having a linear coefficient of expansion more than or equal to 11 ppm/K and less than or equal to 21 ppm/K in order to reduce stress within the semiconductor device, and therefore improve its reliability. Further, it has been held that discovering the optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980). Regarding claims 2, 6, and 7, see the 112 rejections above. Allowable Subject Matter Claims 2, 6, and 7 are rejected because of 112 rejections, but would be allowable if rewritten to overcome the 112 rejections. Regarding claim 2, the prior art is made of record and not relied upon is considered pertinent to applicant's disclosure. Fujino in view of JP 2021-111765 A1 discloses a semiconductor device as disclosed in claim 1, but fails to further disclose a third solder layer having a melting point lower than a first melting point that is a lower one of a melting point of the first solder layer and a melting point of the second solder layer; a fourth solder layer having a melting point lower than the first melting point as disclosed in claim 2. Regarding claims 6, and 7, Fujino in view of JP 2021-111765 A1 fails to further disclose a third lead frame; and a wire connected to the third lead frame, wherein the semiconductor element further includes a third electrode disposed on the second surface and connected to the third lead frame through the wire, and the block includes a surface closer to the third lead frame, the surface having an increasing distance from the third lead frame with distance away from the second surface. INFORMATION ON HOW TO CONTACT THE USPTO Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Eugene Lee March 30, 2026 /EUGENE LEE/Primary Examiner, Art Unit 2815
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Prosecution Timeline

Sep 11, 2023
Application Filed
Apr 06, 2026
Non-Final Rejection mailed — §103, §112
May 27, 2026
Interview Requested

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
87%
With Interview (+5.1%)
2y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 900 resolved cases by this examiner. Grant probability derived from career allowance rate.

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