DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-7, 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Jeng et al. (US 2021/0074600 A1, hereinafter Jeng ‘600) in view of Yu et al. (US 6,100,593, hereinafter Yu ‘593) in view of the following arguments.
With respect to Claim 1 Jeng ‘600 discloses a semiconductor package (Fig 4A-5) comprising:
a semiconductor chip (506, Fig 4F, Para [0067]) including a first area (first area as shown in annotated Fig 4F of Jeng ‘600, hereinafter FA) and a second area (second area as shown in annotated Fig 4F of Jeng ‘600, hereinafter SA) around the first area (FA);
a substrate (110/112, Fig 4F, Para [0030]) including a second surface (112A, Fig 4F, Para [0031]), the second surface (112A) facing (disclosed in Fig 4F) a first surface (bottom of device 506, Fig 4F) of the semiconductor chip (506), a first trench (left 502 as shown in annotated Fig 4F of Jeng ‘600, Para [0063]) defined on the second surface (112A) and the first trench (left 502) at least partially overlapping (as shown in annotated Fig 4F of Jeng ‘600) the second area (SA) of the semiconductor chip (506);
a bump structure (508/509, Fig 4F, Para [0068]) including first bumps (first bumps as shown in annotated Fig 4F of Jeng ‘600, hereinafter FB) on the first area (FA) of the semiconductor chip (506), and second bumps (second bump as shown in annotated Fig 4F of Jeng ‘600, hereinafter SB) on the second area (SA) of the semiconductor chip (506), the bump structure (508/509) between (disclosed in Fig 4F) the substrate (110/112) and the semiconductor chip (506); and
a first passive device (leftmost 504 as shown in annotated Fig 4F of Jeng ‘600, Para [0066] discloses 504 comprising passive device) in the first trench (left 502),
But Jeng ‘600 fails to expressly disclose each of the second bumps including a second upper solder layer on the first surface of the semiconductor chip, wherein the second upper solder layer of each of the second bumps is between a top surface of the first device and the first surface of the semiconductor chip, the second upper solder layer of each of the second bumps being in direct contact with the first surface of the semiconductor chip and the top surface of the first device.
Nevertheless, in a related endeavor (Fig 1-3 of Yu ‘593), Yu ‘593 teaches each of the second bumps (110, Fig 3 of Yu ‘593, Col 3, Lines 21-22) including a second upper solder layer (solder layer of 110, Col 3, Lines 21-22 of Yu ‘593 discloses 110 as a solder ball, hereinafter 2USL) on the first surface (bottom side of 108 as shown in Fig 3 of Yu ‘593) of the semiconductor chip (108, Fig 3 of Yu ‘593, Col 3, Lines 21-22), wherein the second upper solder layer (2USL) of each of the second bumps (110) is between a top surface (top of 104) of the first device (104, Fig 3 of Yu ‘593, Col 3, Lines 21-22) and the first surface (bottom side of 108) of the semiconductor chip (108), the second upper solder layer (2USL) of each of the second bumps (110) being in direct contact (Fig 3 of Yu ‘593 discloses solder layer of 110 in direct contact with bottom of 108 and top of 104) with the first surface (bottom side of 108) of the semiconductor chip (108) and the top surface (top of 104) of the first device (104).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Yu ‘593’s teaching of each of the second bumps including a second upper solder layer on the first surface of the semiconductor chip, wherein the second upper solder layer of each of the second bumps is between a top surface of the first device and the first surface of the semiconductor chip, the second upper solder layer of each of the second bumps being in direct contact with the first surface of the semiconductor chip and the top surface of the first device into Jeng ‘600’s device. Jeng ‘600 discloses a semiconductor package with multiple chips; those chips directly connected to one another. Yu ‘593 also teaches a multi-chip semiconductor package with chips directly connected to one another and further teaches the use of a solder ball in direct contact to the top and bottom of the two chips to be connected. The ordinary artisan would have been motivated to modify Jeng ‘600 in the manner set forth above, at least, because as Yu ‘593 teaches in Col 2, Lines 39-43 the use of solder bumps between chips of a multi-chip package can lead to an increased yield and performance of the device.
As incorporated, the teaching of Yu ‘593 of using a solder bump (110) with a solder layer (solder layer of 110) would be used as the second bump (SB) of Jeng ‘600 such that SB of Jeng ‘600 includes the solder layer of 110 of Yu ‘593 and SB is between top surface of first passive device (504) of Jeng ‘600 and the bottom surface of semiconductor chip (506) of Jeng ‘600, the second upper solder layer (solder layer of 110) of Jeng ‘600 of each of the second bumps (SB) of Jeng ‘600 being in direct contact with the first surface (bottom of 506) of the semiconductor chip (506) and the top surface of the first passive device (504) of Jeng ‘600.
With respect to Claim 6 Jeng ‘600 as modified by Yu ‘593 discloses all limitations of the semiconductor package of claim 1, and Jeng ‘600 further discloses wherein
the substrate (110/112) includes an insulating layer (Para [0063] discloses 112 composition described in Para [0030] which discloses structure of 112 to dielectric layers) and a wiring layer (Para [0063] discloses 112 composition in Para [0030] which discloses structure of 112 to contain metal lines, hereinafter WL of 110/112), the wiring layer (WL of 110/112) electrically connected (Para [0068] discloses 506 electrically connected to 112) to the semiconductor chip (506), and
the first passive device (leftmost 504) and the semiconductor chip (506) are electrically connected (Para [0068 and 0069] discloses 504 electrically connected to 506 and 110/112 through FB and WL of 110/112) through the first bumps (FB) and the wiring layer (WL of 110/112).
With respect to Claim 7 Jeng ‘600 as modified by Yu ‘593 discloses all limitations of the semiconductor package of claim 1, and in a further embodiment (embodiment disclosed in Para [0080] of Jeng ‘600), Jeng ‘600 further discloses wherein the first passive device (leftmost 504) and the semiconductor chip (506) are not electrically connected (Para [0080] discloses an embodiment where the devices 504 are not electrically connected to 506) through the second bumps (SB).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Jeng ‘600’s further teaching of wherein the first passive device and the semiconductor chip are not electrically connected through the second bumps in Jeng ‘600 as modified by Yu ‘593’s earlier device embodiment. The ordinary artisan would have been motivated to further modify Jeng ‘600 in the manner set forth above, at least, because as Jeng ‘600 notes in Para [0080] this connection configuration enables the incorporation of various types of passive devices, which a person of ordinary skill in the art would recognize as providing them flexibility in both the device and manufacturing process.
As incorporated, the further embodiment teaching of Jeng ‘600 of not electrically connecting 504 to 506 would be used in the device of Jeng ‘600 as modified by Yu ‘593.
With respect to Claim 9 Jeng ‘600 as modified by Yu ‘593 discloses all limitations of the semiconductor package of claim 1, and Jeng ‘600 further discloses wherein
the first passive device (leftmost 504) is on the substrate (110/112)(arrangement disclosed in Fig 4F), and
and in a further embodiment (Fig 5 of Jeng ‘600), Jeng ‘600 further teaches the first passive device (leftmost 504) is spaced apart (leftmost 504 spaced apart from 110/112 by pillars 516) from the substrate (110/112) by a lower pillar layer (516A, Fig 5 of Jeng ‘600, Para [0078]) and a lower solder layer (516B, Fig 5 of Jeng ‘600, Para [0078]) between a bottom surface (bottom of leftmost 504) of the first passive device (leftmost 504) and the substrate (110/112).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Jeng ‘600’s further teaching of wherein the first passive device is on the substrate, and the first passive device is spaced apart from the substrate by a lower pillar layer and a lower solder layer between a bottom surface of the first passive device and the substrate into Jeng ‘600 as modified by Yu ‘593’s device. The ordinary artisan would have been motivated to further modify Jeng ‘600 in the manner set forth above, at least, because as Jeng ‘600 notes in Para [0080 and 0081] this connection configuration enables the incorporation of various types of passive devices, which a person of ordinary skill in the art would recognize as providing them flexibility in both the device and manufacturing process.
As incorporated, the further embodiment teaching of Jeng ‘600 the first passive device is spaced apart from the substrate by a lower pillar layer and a lower solder layer between a bottom surface of the first passive device and the substrate of would be used as the arrangement of (leftmost 504) of Jeng ‘600 as modified by Yu ‘593.
With respect to Claim 11 Jeng ‘600 as modified by Yu ‘593 discloses all limitations of the semiconductor package of claim 1, and Jeng ‘600 discloses further comprising:
an underfill material (510, Fig 4F, Para [0070]) between the semiconductor chip (506) and the substrate (110/112), the underfill material (510) filling at least part (Fig 4D and Para [0070] disclose 510 fills trench 502) of the first trench (left 502).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over in view of Jeng ‘600 in view of Yu ‘593 in further view of Elsherbini et al. (US 2020/0219815 A1, hereinafter Elsherbini ‘815) in view of the following arguments.
With respect to Claim 4 Jeng ‘600 as modified by Yu ‘593 discloses all limitations of the semiconductor package of claim 1, and Jeng ‘600 further discloses wherein
the first passive device (leftmost 504) is in the first trench (left 502), the first trench (left 502) having a first depth (first depth shown in annotated Fig 4F of Jeng ‘600, hereinafter FD) from the second surface (112A) of the substrate (110/112), and
Jeng ‘600 discloses in Para [0065], “In some embodiments, each cavity 502 is designed to have an appropriate depth so that the top surface 504A of the respective semiconductor device 504 is substantially flush with the top surface 110B of the interposer substrate 110 after the semiconductor devices 504 are placed in the cavities 502 in some embodiments that the cavity 502”, so Jeng ‘600 is open to an embodiment where the top surface of the device 504 is not at the same level as the top surface of the substrate. But Jeng ‘600 as modified by Yu ‘593 fails to explicitly disclose a top surface of the first passive device protrudes from the second surface of the substrate.
In a related endeavor (Fig 1 of Elsherbini ‘815), Elsherbini ‘815 teaches a top surface (top of 114-1 as shown in Fig 1 of Elsherbini ‘815) of the first passive device (114-1, Fig 1 of Elsherbini ‘815, Para [0058]) protrudes from (shown in Fig 1 of Elsherbini ‘815) the second surface (top of 164) of the substrate (102, Fig 1 of Elsherbini ‘815, Para [0033]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Elsherbini ‘815’s teaching of a top surface of the first passive device protrudes from the second surface of the substrate into Jeng ‘600’s device. As described above Jeng ‘600 as modified by Yu ‘593 is open to passive devices not being the size of the trench and Jeng ‘600 as modified by Yu ‘593 also discloses a plurality of devices in the trench structures. Elsherbini ‘815 teaches a plurality of devices in trenches and further teaches (Para [0058]) that the devices may not all be the same height. The ordinary artisan would have been motivated to modify Jeng ‘600 as modified by Yu ‘593 in the manner set forth above, at least, because Elsherbini ‘815 teaches a single depth for trenches regardless of the height of the components which would simplify the manufacturing process by not having to create a custom trench depth for each device.
As incorporated, the teaching of Elsherbini ‘815 of a top surface of the passive device protruding from the surface of substrate would be used as the arrangement of (leftmost 502) above the surface of (110/112) of Jeng ‘600 as modified by Yu ‘593.
Allowable Subject Matter
Claims 2-3 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claims 2-3: Allowable subject matter has been indicated because the closes prior art of record, either alone or in combination, fails to teach or fairly suggest the feature “wherein each of the first bumps includes a first upper pillar layer on the first surface of the semiconductor chip, and a first upper solder layer, between the first upper pillar layer and the second surface of the substrate” along with the rest of the limitation of said claims.
Closest prior art of record Jeng et al. (US 2021/0074600 A1) teaches “A semiconductor package comprising: a semiconductor chip including a first area and a second area around the first area; a substrate including a second surface, the second surface facing a first surface of the semiconductor chip, a first trench defined on the second surface and the first trench at least partially overlapping the second area of the semiconductor chip; a bump structure including first bumps on the first area of the semiconductor chip, and second bumps on the second area of the semiconductor chip, the bump structure between the substrate and the semiconductor chip; and a first passive device in the first trench, wherein the second bumps are in contact with the first surface of the semiconductor chip and the first passive device and Jeng ‘600 also teaches first and second bumps comprising pillars and solder. However, Jeng ‘600 fails to disclose where some of the bump connectors on the semiconductor die are solder bumps and some comprise a pillar layer along with a solder bump.
Closest prior art of record Yu ‘593 discloses a multi-chip semiconductor package with chips directly connected to one another and further teaches the use of a solder ball in direct contact to the top and bottom of the two chips to be connected and Yu ‘593 also teaches bumps comprising and solder. However, Yu ‘593 fails to disclose that some of the bump connectors on the semiconductor die are solder bumps and some comprise a pillar layer along with a solder bump. Further there is no motivation to modify only some of the solder/pillar connections Jeng ‘600 with the solder ball teachings of Yu ‘593.
Regarding Claim 5: Allowable subject matter has been indicated because the closes prior art of record, either alone or in combination, fails to teach or fairly suggest the feature, “wherein a thickness of the second bumps differs from a thickness of the first bumps” along with the rest of the limitations of said claims.
Closest prior art of record Jeng et al. (US 2021/0074600 A1) teaches “A semiconductor package comprising: a semiconductor chip including a first area and a second area around the first area; a substrate including a second surface, the second surface facing a first surface of the semiconductor chip, a first trench defined on the second surface and the first trench at least partially overlapping the second area of the semiconductor chip; a bump structure including first bumps on the first area of the semiconductor chip, and second bumps on the second area of the semiconductor chip, the bump structure between the substrate and the semiconductor chip; and a first passive device in the first trench, wherein the second bumps are in contact with the first surface of the semiconductor chip and the first passive device. However, Jeng et al fails to disclose wherein a thickness of the second bumps differs from a thickness of the first bumps.
Claims 12-17 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 12: Allowable subject matter has been indicated because the closes prior art of record, either alone or in combination, fails to teach or fairly suggest the feature, “wherein a thickness of the dummy bumps differs from a thickness of the connection bumps, the dummy bumps are in contact with the passive device, and the connection bumps are in contact with the substrate” along with the rest of the limitations of said claim.
Closet prior art of record Jeng ‘600 teaches, “A semiconductor package comprising: a semiconductor chip including a first area and a second area, the second area around the first area in a plan view of the semiconductor chip; a substrate including a top surface, the top surface of the substrate facing a bottom surface of the semiconductor chip, a trench defined in the top surface of the substrate, and the trench at least partially overlapping the second area of the semiconductor chip; a bump structure including connection bumps in the first area of the semiconductor chip, the bump structure between the substrate and the semiconductor chip; and a passive device in the trench, the passive device between the bump structure and the substrate”. However, Jeng et al. fails to teach, “and dummy bumps on the second area of the semiconductor chip” and “wherein a thickness of the dummy bumps differs from a thickness of the connection bumps, the dummy bumps are in contact with the passive device, and the connection bumps are in contact with the substrate”
Closest prior art of record Kim et al. (US2020/273800 A1) teaches “and dummy bumps on the second area of the semiconductor chip”. However Kim et al. fails to teach “a trench defined in the top surface of the substrate, and the trench at least partially overlapping the second area of the semiconductor chip; a bump structure including connection bumps in the first area of the semiconductor chip, the bump structure between the substrate and the semiconductor chip; and a passive device in the trench, the passive device between the bump structure and the substrate” and “wherein a thickness of the dummy bumps differs from a thickness of the connection bumps, the dummy bumps are in contact with the passive device, and the connection bumps are in contact with the substrate”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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