DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 8, 10 and 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Invention II and non-elected species Device Embodiment 2 and 3, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 02/09/2026.
Claim 18 reads on unelected Species Device Embodiment 3, wherein, the first passive device 410 is attached by lower pillar layers 410a and 410b as in Device Embodiment 1, but a third passive device 430 is attached in a third trench TR3 of the third insulating layer 111. That third passive area is not shown in Device Embodiment 1 and Device Embodiment 2. Specifically, Claim 18 states “the semiconductor chip includes a third area on an inside of the first area, and the passive device is in the third area”. Therefore claim 18 is withdrawn from further consideration, as being drawn to a nonelected species. Applicant timely traversed the restriction (election) requirement in the reply filed on 02/09/2026.
Applicant's election with traverse of Invention I and species 1A in the reply filed on 02/09/2026 is acknowledged. The traversal is on the ground(s) that Applicant submits that the search and examination of all claims may be made without serious search burden. This is not found persuasive because as stated in the Restriction/Election Requirement mailed on 12/08/2025, the inventions have acquired a separate status in the art in view of their different classification and the inventions require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
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Claims 1-3, 6 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeng et al. (US 2021/0074600 A1, hereinafter Jeng ‘600).
With respect to Claim 1 Jeng ‘600 discloses a semiconductor package (Fig 4A-5) comprising:
a semiconductor chip (506, Fig 4F, Para [0067]) including a first area (first area as shown in annotated Fig 4F of Jeng ‘600, hereinafter FA) and a second area (second area as shown in annotated Fig 4F of Jeng ‘600, hereinafter SA) around the first area (FA);
a substrate (110/112, Fig 4F, Para [0030]) including a second surface (112A, Fig 4F, Para [0031]), the second surface (112A) facing (disclosed in Fig 4F) a first surface (bottom of device 506, Fig 4F) of the semiconductor chip (506), a first trench (left 502 as shown in annotated Fig 4F of Jeng ‘600, Para [0063]) defined on the second surface (112A) and the first trench (left 502) at least partially overlapping (as shown in annotated Fig 4F of Jeng ‘600) the second area (SA) of the semiconductor chip (506);
a bump structure (508/509, Fig 4F, Para [0068]) including first bumps (first bumps as shown in annotated Fig 4F of Jeng ‘600, hereinafter FB) on the first area (FA) of the semiconductor chip (506), and second bumps (second bump as shown in annotated Fig 4F of Jeng ‘600, hereinafter SB) on the second area (SA) of the semiconductor chip (506), the bump structure (508/509) between (disclosed in Fig 4F) the substrate (110/112) and the semiconductor chip (506); and
a first passive device (leftmost 504 as shown in annotated Fig 4F of Jeng ‘600, Para [0066] discloses 504 comprising passive device) in the first trench (left 502),
wherein the second bumps (SB) are in contact with (disclosed in Fig 4F) the first surface (bottom of device 506) of the semiconductor chip (506) and the first passive device (left 504).
With respect to Claim 2 Jeng ‘600 discloses all limitations of the semiconductor package of claim 1, and Jeng ‘600 further discloses wherein
each of the first bumps (FB) includes a first upper pillar layer (508, Fig 4F, Para [0068]) on the first surface (bottom of device 506) of the semiconductor chip (506), and a first upper solder layer (509B, Fig 4F, Para [0068] discloses bonding as solder bonding), between the first upper pillar layer (508) and the second surface (112A) of the substrate (110/112), and
each of the second bumps (SB) includes a second upper solder layer (508 of SB as shown in annotated Fig 4F of Jeng ‘600) on the first surface (bottom of device 506) of the semiconductor chip (506).
With respect to Claim 3 Jeng ‘600 discloses all limitations of the semiconductor package of claim 2, and Jeng ‘600 further discloses wherein
the second upper solder layer (508 of SB) is between (disclosed in annotated Fig 4F of Jeng ‘600) a top surface (top of leftmost 504 as shown in annotated Fig 4F of Jeng ‘600) of the first passive device (leftmost 504) and the first surface (bottom of device 506) of the semiconductor chip (506), and
the first upper solder layer (509B) is between (disclosed in annotated Fig 4F of Jeng ‘600) the second surface (112A) of the substrate (110/112) and the first surface (bottom of device 506) of the semiconductor chip (506).
With respect to Claim 6 Jeng ‘600 discloses all limitations of the semiconductor package of claim 1, and Jeng ‘600 further discloses wherein
the substrate (110/112) includes an insulating layer (Para [0063] discloses 112 composition described in Para [0030] which discloses structure of 112 to dielectric layers) and a wiring layer (Para [0063] discloses 112 composition in Para [0030] which discloses structure of 112 to contain metal lines, hereinafter WL of 110/112), the wiring layer (WL of 110/112) electrically connected (Para [0068] discloses 506 electrically connected to 112) to the semiconductor chip (506), and
the first passive device (leftmost 504) and the semiconductor chip (506) are electrically connected (Para [0068 and 0069] discloses 504 electrically connected to 506 and 110/112 through FB and WL of 110/112) through the first bumps (FB) and the wiring layer (WL of 110/112).
With respect to Claim 11 Jeng ‘600 discloses all limitations of the semiconductor package of claim 1, and Jeng ‘600 discloses further comprising:
an underfill material (510, Fig 4F, Para [0070]) between the semiconductor chip (506) and the substrate (110/112), the underfill material (510) filling at least part (Fig 4D and Para [0070] disclose 510 fills trench 502) of the first trench (left 502).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over in view of Jeng ‘600 in view of Elsherbini et al. (US 2020/0219815 A1, hereinafter Elsherbini ‘815) in view of the following arguments.
With respect to Claim 4 Jeng ‘600 discloses all limitations of the semiconductor package of claim 1, and Jeng ‘600 further discloses wherein
the first passive device (leftmost 504) is in the first trench (left 502), the first trench (left 502) having a first depth (first depth shown in annotated Fig 4F of Jeng ‘600, hereinafter FD) from the second surface (112A) of the substrate (110/112), and
Jeng ‘600 discloses in Para [0065], “In some embodiments, each cavity 502 is designed to have an appropriate depth so that the top surface 504A of the respective semiconductor device 504 is substantially flush with the top surface 110B of the interposer substrate 110 after the semiconductor devices 504 are placed in the cavities 502 in some embodiments that the cavity 502”, so Jeng ‘600 is open to an embodiment where the top surface of the device 504 is not at the same level as the top surface of the substrate. But Jeng ‘600 fails to explicitly disclose a top surface of the first passive device protrudes from the second surface of the substrate.
In a related endeavor (Fig 1 of Elsherbini ‘815), Elsherbini ‘815 teaches a top surface (top of 114-1 as shown in Fig 1 of Elsherbini ‘815) of the first passive device (114-1, Fig 1 of Elsherbini ‘815, Para [0058]) protrudes from (shown in Fig 1 of Elsherbini ‘815) the second surface (top of 164) of the substrate (102, Fig 1 of Elsherbini ‘815, Para [0033]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Elsherbini ‘815’s teaching of a top surface of the first passive device protrudes from the second surface of the substrate into Jeng ‘600’s device. As described above Jeng ‘600 is open to passive devices not being the size of the trench and Jeng ‘600 also discloses a plurality of devices in the trench structures. Elsherbini ‘815 teaches a plurality of devices in trenches and further teaches (Para [0058]) that the devices may not all be the same height. The ordinary artisan would have been motivated to modify Jeng ‘600 in the manner set forth above, at least, because Elsherbini ‘815 teaches a single depth for trenches regardless of the height of the components which would simplify the manufacturing process by not having to create a custom trench depth for each device.
As incorporated, the teaching of Elsherbini ;815 of a top surface of the passive device protruding from the surface of substrate would be used as the arrangement of (leftmost 502) above the surface of (110/112) of Jeng ‘600.
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Jeng ‘600 in view of the following arguments.
With respect to Claim 7 Jeng ‘600 discloses all limitations of the semiconductor package of claim 1, and in a further embodiment (embodiment disclosed in Para [0080] of Jeng ‘600), Jeng ‘600 further discloses wherein the first passive device (leftmost 504) and the semiconductor chip (506) are not electrically connected (Para [0080] discloses an embodiment where the devices 504 are not electrically connected to 506) through the second bumps (SB).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Jeng ‘600’s further teaching of wherein the first passive device and the semiconductor chip are not electrically connected through the second bumps in Jeng ‘600’s earlier device embodiment. The ordinary artisan would have been motivated to further modify Jeng ‘600 in the manner set forth above, at least, because as Jeng ‘600 notes in Para [0080] this connection configuration enables the incorporation of various types of passive devices, which a person of ordinary skill in the art would recognize as providing them flexibility in both the device and manufacturing process.
As incorporated, the teaching of Jeng ‘600 of not electrically connecting 504 to 506 would be used in the device of Jeng ‘600.
With respect to Claim 9 Jeng ‘600 discloses all limitations of the semiconductor package of claim 1, and Jeng ‘600 further discloses wherein
the first passive device (leftmost 504) is on the substrate (110/112)(arrangement disclosed in Fig 4F), and
and in a further embodiment (Fig 5 of Jeng ‘600), Jeng ‘600 further teaches the first passive device (leftmost 504) is spaced apart (leftmost 504 spaced apart from 110/112 by pillars 516) from the substrate (110/112) by a lower pillar layer (516A, Fig 5 of Jeng ‘600, Para [0078]) and a lower solder layer (516B, Fig 5 of Jeng ‘600, Para [0078]) between a bottom surface (bottom of leftmost 504) of the first passive device (leftmost 504) and the substrate (110/112).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Jeng ‘600’s further teaching of wherein the first passive device is on the substrate, and the first passive device is spaced apart from the substrate by a lower pillar layer and a lower solder layer between a bottom surface of the first passive device and the substrate into Jeng ‘600’s device. The ordinary artisan would have been motivated to further modify Jeng ‘600 in the manner set forth above, at least, because as Jeng ‘600 notes in Para [0080 and 0081] this connection configuration enables the incorporation of various types of passive devices, which a person of ordinary skill in the art would recognize as providing them flexibility in both the device and manufacturing process.
As incorporated, the further teaching of Jeng ‘600 the first passive device is spaced apart from the substrate by a lower pillar layer and a lower solder layer between a bottom surface of the first passive device and the substrate of would be used as the arrangement of (leftmost 504) of Jeng ‘600.
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 5: Allowable subject matter has been indicated because the closes prior art of record, either alone or in combination, fails to teach or fairly suggest the feature, “wherein a thickness of the second bumps differs from a thickness of the first bumps”.
Closest prior art of record Jeng et al. (US 2021/0074600 A1) teaches “A semiconductor package comprising: a semiconductor chip including a first area and a second area around the first area; a substrate including a second surface, the second surface facing a first surface of the semiconductor chip, a first trench defined on the second surface and the first trench at least partially overlapping the second area of the semiconductor chip; a bump structure including first bumps on the first area of the semiconductor chip, and second bumps on the second area of the semiconductor chip, the bump structure between the substrate and the semiconductor chip; and a first passive device in the first trench, wherein the second bumps are in contact with the first surface of the semiconductor chip and the first passive device. However Jeng et al fails to disclose wherein a thickness of the second bumps differs from a thickness of the first bumps.
Claims 12-17 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 12: Allowable subject matter has been indicated because the closes prior art of record, either alone or in combination, fails to teach or fairly suggest the feature, “wherein a thickness of the dummy bumps differs from a thickness of the connection bumps, the dummy bumps are in contact with the passive device, and the connection bumps are in contact with the substrate” along with the rest of the limitations of said claim.
Closet prior art of record Jeng et al. (US 2021/0074600 A1) teaches, “A semiconductor package comprising: a semiconductor chip including a first area and a second area, the second area around the first area in a plan view of the semiconductor chip; a substrate including a top surface, the top surface of the substrate facing a bottom surface of the semiconductor chip, a trench defined in the top surface of the substrate, and the trench at least partially overlapping the second area of the semiconductor chip; a bump structure including connection bumps in the first area of the semiconductor chip, the bump structure between the substrate and the semiconductor chip; and a passive device in the trench, the passive device between the bump structure and the substrate”. However Jeng et al. fails to teach, “and dummy bumps on the second area of the semiconductor chip” and “wherein a thickness of the dummy bumps differs from a thickness of the connection bumps, the dummy bumps are in contact with the passive device, and the connection bumps are in contact with the substrate”
Closest prior art of record Kim et al. (US2020/273800 A1) teaches “and dummy bumps on the second area of the semiconductor chip”. However Kim et al. fails to teach “a trench defined in the top surface of the substrate, and the trench at least partially overlapping the second area of the semiconductor chip; a bump structure including connection bumps in the first area of the semiconductor chip, the bump structure between the substrate and the semiconductor chip; and a passive device in the trench, the passive device between the bump structure and the substrate” and “wherein a thickness of the dummy bumps differs from a thickness of the connection bumps, the dummy bumps are in contact with the passive device, and the connection bumps are in contact with the substrate”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim et al. (US 2020/0273800 A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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