DETAILED ACTION
This non-final action is responsive to communications: application filed on 09/11/2023.
Claims 1-20 are pending. Claims 1, 10, and 20 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
No Priority
4. No priority is in the record, see ADS.
No Information Disclosure Statement
5. No IDS is in the record.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. Such omission is tantamount to omitting essential structural cooperative relationships of elements also. See MPEP § 2172.01. A claim which omits subject matter disclosed to be essential to the invention as described in the specification or in other statements of record may be rejected as failing to claim the subject matter that the inventor or a joint inventor regards as the invention. See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976); In re Venezia, 530 F.2d 956, 189 USPQ 149 (CCPA 1976); and In re Collier, 397 F.2d 1003, 158 USPQ 266 (CCPA 1968). Such essential matter may include missing elements (circuitry components essential for function), steps or necessary structural cooperative relationships of elements described by the applicant(s) as necessary to practice the invention. For example, for In re Mayhew, the Court of Customs and Patent Appeals (CCPA) held that claims were not enabled under 35 U.S.C. § 112 because they omitted a cooling bath and its specific location, which were deemed essential elements based on the specification. The court found that the specification indicated these elements were critical for the invention to function as described, and their omission from the claims rendered them not supported by an enabling disclosure.
Claim 1, lines 7-10 recites: “…second transistor comprises a charge trap layer…configured to be unalterable…be alterable…”: (1)
Claim 10, lines 15-18 recites “…read transistor comprises a charge trap layer…. configured to…be unalterable…be alterable…” (2)
Claim 20, lines 14-18 recites “…threshold voltage of the read transistor remaining unchanged…read transistor is programmed or erased to have a particular threshold voltage…” (3)
For (1)-(3) limitations above, gate level construction and composition details of “read transistor” is missing making the described biasing scheme vague, ambiguous, subject to multiple interpretations. Associated biasing results described can be achieved in multiple ways and the limitations are vague without clear description of the gate level structure of read transistor. In view of para [0084]-para [0086] descriptions, the limitation language is vague. For example, composition of charge trap layer in association with gate electrode or, any other layer can be described in light of para [0084]-para [0086].
All dependent claims inclusive of claims 1-20 are rejected under this category.
See art rejection for the interpretation of the limitations.
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
11. Claims 1-6, 9-11, and 13-16 is/are rejected under 35 U.S.C. 103 as being obvious over KURITA et al. (US 2013/0077397 A1), in view of YOUNG et al. (US 2021/0375344 A1).
Regarding independent claim 1, KURITA teaches a semiconductor circuit (para [0035]: memory, see Fig. 9), comprising:
a first transistor (Fig. 9: M1ij); and
a second transistor (Fig. 9: M2ij),
wherein the first transistor (Fig. 9: M1ij) has a gate terminal (Fig. 9: gate of M1ij) configured to receive a gate voltage (Fig. 9: WWLj voltage) to turn on or off the first transistor,
a first terminal (Fig. 9: left terminal of M1ij coupled to WBLi) configured to receive a write voltage (para [0046]), and
a second terminal (Fig. 9: right terminal of M1ij) coupled to a gate terminal of the second transistor (Fig. 9: gate of M2ij), and
wherein the second transistor (Fig. 9: M2ij) comprises a charge trap layer at the gate terminal of the second transistor (para [0030]: “charge trap film”, Fig. 4: 14),
the charge trap layer being configured to:
be unalterable when a first write voltage (Fig. 9: WBLi voltage) is applied at the first terminal of the first transistor (Fig. 3-Fig. 5 and para [0027], para [0030]: applied lower voltage level below “write voltage” threshold), and
be alterable when a second write voltage is applied at the first terminal of the first transistor to change a threshold voltage of the second transistor (Fig. 3-Fig. 5 and para [0027], para [0030]: applied higher voltage level at or above “write voltage” threshold),
the second write voltage being greater than the first write voltage (applied lower voltage level and higher voltage level).
KURITA is silent with respect to volatile mode when charge trap layer is unaltered and non-volatile mode when charge trap layer is altered.
Young teaches same type cell (fig. 2A) and explains how to operate it in a volatile mode and in a non-volatile mode (paragraph [0163]: "integrated circuit 500 can operate in a non-volatile mode or a volatile mode.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Chang's compute system and function into the apparatus of KURITA such that In-Memory Computing system with training mode and inference mode of operation can be employed in order to improve “energy-efficiency” and improve accuracy of prediction (para [0061], para [0008]).
Regarding claim 2, KURITA and Young teach the semiconductor circuit of claim 1. KURITA teaches wherein the semiconductor circuit is configured to: operate in a first mode where a storage potential of a storage node between the second terminal of the first transistor and the gate terminal of the second transistor is determined based on the first write voltage applied at the first terminal of the first transistor while the first transistor is turned on, the threshold voltage of the second transistor remaining unchanged (Fig. 9 Fig. 3-Fig. 5 and para [0027], para [0030]),
the storage potential of the storage node being repeatedly changeable based on the first write voltage, and operate in a second mode where the second transistor is programmed or erased to have a particular threshold voltage based on the second write voltage applied at the first terminal of the first transistor while the first transistor is turned on, the particular threshold voltage being tunable based on the second write voltage (Fig. 9 Fig. 3-Fig. 5 and para [0027], para [0030]).
Young teaches same type cell (fig. 2A) and explains how to operate it in a volatile mode and in a non-volatile mode (paragraph [0163]: "integrated circuit 500 can operate in a non-volatile mode or a volatile mode.").
Regarding claim 3, KURITA and Young teach the semiconductor circuit of claim 2, wherein the first mode comprises a training mode of an artificial intelligence (AI) model or a dynamic random-access memory (DRAM)-like mode, and the second mode comprises an inference mode of the AI model or a non-volatile memory (NVM)-like mode. (See claims 1, 2 above)
Regarding claim 4, KURITA and Young teach the semiconductor circuit of claim 2. KURITA teaches wherein the storage potential of the storage node corresponds to an adjustable weight in the first mode (para [0046], Fig. 2, Fig. 9: storage node can be 0 or 1), and
the particular threshold voltage of the second transistor corresponds to a fixed weight in the second mode (para [0046], Fig. 2, Fig. 9: M2ij can be programmed with fixed data e.g. 1).
Regarding claim 5, KURITA and Young teach the semiconductor circuit of claim 2. KURITA teaches wherein the particular threshold voltage of the second transistor corresponds to a binary weight “1” or “0” in the second mode (para [0046]).
Regarding claim 6, KURITA and Young teach the semiconductor circuit of claim 2. KURITA teaches wherein the particular threshold voltage of the second transistor corresponds to an analog weight in the second mode (fixed threshold is programmed into cell), and the
particular threshold voltage is tunable between a minimum threshold voltage and a maximum threshold voltage (erased state and programmed state).
Regarding claim 9, KURITA and Young teach the semiconductor circuit of claim 1. KURITA teaches wherein the second transistor comprises a silicon-oxide-nitride-oxide-silicon (SONOS) transistor, and wherein the first transistor comprises a metal-oxide-semiconductor (MOS) transistor or an SONOS transistor (para [0033])
Regarding independent claim 10, KURITA teaches a semiconductor device (para [0035], memory array, see Fig. 9), comprising:
an array of memory cells (para [0035], memory array, see Fig. 9: MC_ij cell);
one or more write word lines (WWLs) (Fig. 9: WWLj);
one or more write bit lines (WBLs) (Fig. 9: WBLi);
one or more read word lines (RBLs) (Fig. 9: RWLj); and
one or more read bit lines (RBLs) (Fig. 9: RBLi),
wherein each memory cell (Fig. 9: MCij) of the array of memory cells comprises:
a write transistor (Fig. 9: M1ij); and
a read transistor (Fig. 9: M2ij),
wherein the write transistor comprises a gate terminal (Fig. 9: gate of M1ij) coupled to a corresponding write word line (Fig. 9: WWLj),
a first terminal (Fig. 9: left terminal of M1ij) coupled to a corresponding write bit line (Fig. 9: WBLi), and a second terminal (Fig. 9: right terminal of M1ij) coupled to a gate terminal of the read transistor (Fig. 9: gate of M2ij), and
wherein the read transistor (Fig. 9: M2ij) comprises a first terminal (Fig. 9: right terminal of M2ij) coupled to a corresponding read bit line (Fig. 9: RBLi) and a second terminal (Fig. 9: left terminal of M2ij) coupled to a corresponding read word line (Fig. 9: RWLj), and
wherein the read transistor (Fig. 9: M2ij) comprises a charge trap layer at the gate terminal of the read transistor (para [0030]: “charge trap film”, Fig. 4: 14),
the charge trap layer being configured to:
be unalterable when a first write voltage through the corresponding write bit line (Fig. 9: WBLi) is applied at the first terminal of the write transistor (Fig. 3-Fig. 5 and para [0027], para [0030]: applied lower voltage level below “write voltage” threshold), and
be alterable when a second write voltage through the corresponding write bit line (Fig. 9: WBLi) is applied at the first terminal of the write transistor (Fig. 9: left terminal of M1ij) to change a threshold voltage of the read transistor (Fig. 3-Fig. 5 and para [0027], para [0030]: applied higher voltage level at or above “write voltage” threshold),
the second write voltage being greater than the first write voltage (applied lower voltage level and higher voltage level).
KURITA is silent with respect to volatile mode when charge trap layer is unaltered and non-volatile mode when charge trap layer is altered.
Young teaches same type cell (fig. 2A) and explains how to operate it in a volatile mode and in a non-volatile mode (paragraph [0163]: "integrated circuit 500 can operate in a non-volatile mode or a volatile mode.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Chang's compute system and function into the apparatus of KURITA such that In-Memory Computing system with training mode and inference mode of operation can be employed in order to improve “energy-efficiency” and improve accuracy of prediction (para [0061], para [0008]).
Regarding claim 11, KURITA and Young teach the semiconductor device of claim 10, wherein the memory cell is configured to: operate in a first mode where a storage potential of a storage node between the second terminal of the write transistor and the gate terminal of the read transistor is determined based on the first write voltage applied at the first terminal of the write transistor while the write transistor is turned on by a gate voltage applied at the gate terminal of the write transistor, the threshold voltage of the read transistor remaining unchanged, the storage potential of the storage node being repeatedly changeable based on the first write voltage, and operate in a second mode where the read transistor is programmed or erased to have a particular threshold voltage based on the second write voltage applied at the first terminal of the write transistor while the write transistor is turned on, the particular threshold voltage being tunable based on the second write voltage. (claims 1-2, 9 rejection analysis)
Regarding claim 13, KURITA and Young teach the semiconductor device of claim 12, wherein the first mode comprises a training mode of an artificial intelligence (AI) model or a dynamic random-access memory (DRAM)-like mode, and the second mode comprises an inference mode of the AI model or a non-volatile memory (NVM)-like mode. (claims 3 rejection analysis)
Regarding claim 14, KURITA and Young teach the semiconductor device of claim 13, wherein the storage potential of the storage node corresponds to an adjustable weight in the training mode, and the particular threshold voltage of the read transistor corresponds to a fixed weight in the inference mode. . (claims 4 rejection analysis)
Regarding claim 15, KURITA and Young teach the semiconductor device of claim 14, wherein the particular threshold voltage of the read transistor corresponds to a binary weight “1” or “0” in the inference mode. (claims 5 rejection analysis)
Regarding claim 16, KURITA and Young teach the semiconductor device of claim 14, wherein the particular threshold voltage of the read transistor corresponds to an analog weight in the inference mode, and the particular threshold voltage is tunable between a minimum threshold voltage and a maximum threshold voltage. (claims 6 rejection analysis)
12. Claim 20 is/are rejected under 35 U.S.C. 103 as being obvious over KURITA et al. (US 2013/0077397 A1), in view of Chang et al (US 2020/0364548 A1).
Regarding independent claim 20, KURITA teaches an operation method of a universal memory for In-Memory Computing (IMC) (method of operation of Fig. 9 device where stored data can be employed for computing), the operation method comprising:
universal memory comprises at least one memory cell having a write transistor (Fig. 9: M1ij) and a read transistor (Fig. 9: M2ij),
wherein the write transistor has a gate terminal (Fig. 9: gate of M1ij) configured to receive a gate voltage to turn on or off the write transistor (Fig. 9: WWLj potential), a first terminal (Fig. 9: left terminal of M1ij) configured to receive a write voltage (Fig. 9: WBLi potential), and a second terminal (Fig. 9: right terminal of M1ij) coupled to a gate terminal of the read transistor (Fig. 9: gate of M2ij), and
wherein, during the training mode (biasing condition of writing with lower than “write voltage” threshold is applicable since training requires multiple writing), a storage potential of a storage node (Fig. 9: applied voltage at gate node of M2ij) between the second terminal of the write transistor and the gate terminal of the read transistor (See Fig. 9) is determined based on a first write voltage applied at the first terminal of the write transistor (Fig. 9: WBLi applied at left terminal of MCij) while the write transistor is turned on by a gate voltage applied at the gate terminal of the write transistor (Fig. 9: while MCij gate is turned on by WWLj voltage),
a threshold voltage of the read transistor remaining unchanged (Fig. 9: with lower than “write threshold voltage, M2ij is not programmed),
the storage potential of the storage node being repeatedly changeable based on the first write voltage (biasing condition of writing with lower than “write voltage” threshold is applicable since training requires multiple writing prior to reaching “write voltage” threshold).
KURITA is silent with respect to the details of operation method of In-Memory Computing utilizing training mode inference mode of operation.
Chang teaches -
An operation method of a universal memory for In-Memory Computing (IMC) (method of operation of Fig. 1 device. See also para [0090]), the operation method comprising:
performing a training mode of an artificial intelligence (AI) model in the universal memory (para [0044]: training),
wherein the universal memory comprises at least one memory cell having a write transistor (transistor in pulse gen 30a) and a read transistor (Fig. 1: NR 1, N),
performing an inference mode of the AI model in the universal memory (para [0047]),
wherein, in the inference mode, the read transistor is programmed or erased to have a particular threshold voltage based on a second write voltage (Fig. 1: pulse potential that programs weight in CTT) applied at the first terminal of the write transistor while the write transistor is turned on (para [0047]: “inference mode” requires stable weight values once they are programmed from the pre-trained model. See also para [0123]),
the particular threshold voltage being tunable based on the second write voltage (Fig. 1: CTT can be programmed at different threshold levels).
KURITA and Chang are in the same field of endeavor of operational method (programming and analog compute) of memory circuit and they are in the analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Chang's compute system and function into the apparatus of KURITA such that In-Memory Computing system with training mode and inference mode of operation can be employed in order to improve “energy-efficiency” and improve accuracy of prediction (para [0061], para [0008]).
Allowable Subject Matter
Claims 7, 8, 12, and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims above, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims of the claims. In addition, any associated 112b rejections must be over-come.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
TSENG (US 2024/0221822 A1): Fig. 1A-Fig. 8C disclosure applicable. Gokmen (US 2018/0053089 A1): Fig. 1-Fig. 10 disclosure applicable for all claims.
Lee et al. (US 2023/0370082 A1) teaches a processing-in-memory device based on a resistive memory (Fig. 2: 200 “in-memory computing Macro” for performing “Charge-domain in-memory computing”, see e.g., para [0040], para [0004], para [0048]), the processing-in-memory device comprising: at least one local array (“IMC Column”, see Fig. 2, Fig. 5); and an input operation unit (para [0040]: combined “periphery for providing…input-vector elements” and “column reset mechanisms”) configured to re-set an input value based on a predicted value (para [0041]: “…MVM operations are typically performed by applying input-vector element corresponding to neural-network input activations…”. Thus digital 5-bit inputs are restarted corresponding to operation requirements. Additionally, see column reset) with respect to an operation of the local array (para [0041]) and to apply the re-set input value to the local array (para [0041]: restarted 5-bit inputs corresponding to operation requirements is used), and wherein the local array (“IMC Column”, see Fig. 2, Fig. 5) includes: at least one weight cell (Fig. 3: SRAM latch portion of 10T cell) configured to store a plurality of weights (par [0046], para [0007]); and a charge domain cell (Fig. 3: C, SW1, SW2 circuitry portion of 10T cell; see para [0041], para [0045]) configured to convert the stored weights into voltage values based on the re-set input value (para [0041]: “…DRD-DAC 2201, in response to a respective 5-bit input vector element X…generates …output signal (IA/ IAb) which is subjected to a 1-bit multiplication with the stored weights (W, /Wb,) … and accumulation through charge-redistribution across M-BC capacitors on the compute line…”. See also para [0047]).
It is suggested that applicant consider all prior arts made of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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