DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in Japanese Patent Application No. 2023-044514, filed on 3/20/2023.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/11/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restriction
It has been acknowledged that the applicant has elected without traverse Invention (device embodiment 1) by cancelling claims 3-5, 7-8, and 12-15 (device embodiments 2-8) per the response dated on 1/13/2026. Currently claims 1-2, 6, and 9-11 are present for examination.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The title of the invention has been suggested as, “SEMICONDUCTOR DEVICE COMPRISING A DIE PAD CARRYING A SEMICONDUCTOR CHIP CONNECTED WITH TWO CONNECTORS”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Ashida (US 2006/0043618 A1) in view of Akagi (US 2014/0151785 A1).
Regarding claim 1, Ashida teaches a semiconductor device (semiconductor device, Fig. 8, [0057]) comprising:
a die pad (comprising the layer of first part 7a, [0042], Illustrative Fig. 1, which is a modified and annotated version of Fig. 2 (in Fig. 2 the bottom surface of the semiconductor chip 1 is upside down (see Fig. 9 and [0028]), therefore, upward direction and downward directions are defined as shown in Illustrative Fig. 1) including an upper surface (upper surface, Illustrative Fig. 1);
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a semiconductor chip (semiconductor chip 1, Illustrative Fig. 1, [0035]) provided on the upper surface (upper surface, Illustrative Fig. 1), the semiconductor chip (semiconductor chip 1, Illustrative Fig. 1) including a rectangular shape (see top and bottom views of the semiconductor chip 1 in Figs. 4a and 4b, respectively, [0035]);
a first electrode (electrode for source 105, Fig. 9a, [0058]) provided on the semiconductor chip (semiconductor chip 1, Fig. 9a);
a second electrode (electrode for gate 104, Fig. 9a, [0058]) provided on the semiconductor chip (semiconductor chip 1, Fig. 9a);
a first connector (header for source 5, Illustrative Fig. 1 and Fig. 8, [0043]) provided, the first connector (header for source 5, Illustrative Fig. 1 and Fig. 8) including a portion (see portion 1 as labeled in Illustrative Fig. 2, which is an annotated version of Fig. 8) covering each of the four sides of the rectangular shape (portion 1 covers each of the four sides of the semiconductor chip 15, Illustrative Fig. 2) when viewed from above (Illustrative Fig. 2), and the first connector (header for source 5, Illustrative Fig. 1 and Illustrative Fig. 2) being electrically connected to the first electrode (electrode for source 105, Illustrative Fig. 1, [0027]: “The header for source 5 is arranged, as shown in FIG. 2, below the main surface of the semiconductor chip 1, joined electrically and mechanically with the electrode for source 105 (make reference to FIG. 4) of the semiconductor chip 1”); and
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a sealing resin (resin sealing member 8, Illustrative Fig. 1, [0039]) sealing a periphery of the semiconductor chip (semiconductor chip 1, Illustrative Fig. 1) and the first connector header for source 5, Illustrative Fig. 1).
Ashida, however, does not teach that
the semiconductor chip includes
an element region, and
a termination region (peripheral region 2, Figs 1 and 2, [0042]) surrounding the element region (cell region 1, Figs. 1 and 2); and
the first connector is provided above the termination region.
Akagi, on the other hand, teaches a semiconductor chip (semiconductor device as a vertical metal-oxide semiconductor field effect transistor (MOSFET), Figs. 1 and 2, [0015]-[0016]), which can provides improved breakdown voltage yield and low ON resistance ([0003] and [0009]), wherein
the semiconductor chip (semiconductor device, Figs. 1-2) includes
an element region (cell region 1, Figs. 1 and 2, [0042]), and
a termination region (peripheral region 2, Figs 1 and 2, [0042]) surrounding the element region (cell region 1, Figs. 1 and 2).
A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the semiconductor chip of Akagi is analogous to semiconductor chip in the semiconductor device of Ashida in that the drain electrode (drain electrode 8, Fig. 2, [0045]) is at the bottom, the source electrode (source electrode 12, Fig. 2, [0050]) is large and at the central region (cell region 1, Fig. 2) and the gate electrode (gate electrode 17, Fig. 2, [0050]) is at the edge region (peripheral region 2, Fig. 2), and the semiconductor chip of Ashida can be replaced by the semiconductor chip of Akagi. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the semiconductor chip in the semiconductor device of Ashida with the semiconductor chip of Akagi which would provide the benefit of improved breakdown voltage yield and low ON resistance (Akagi, [0003] and [0009]). Thus, the combination of Ashida and Akagi meets all the limitations of claim 1 including that the first connector is provided above the termination region.
Regarding claim 2, Ashida in view of Akagi teaches the semiconductor device according to claim 1, wherein
Ashida further teaches that
the first connector (header for source 5, Fig. 8) completely covers at least three sides (left, right and lower sides of semiconductor chip 1, Fig. 8) of the rectangular shape (the shape of the semiconductor chip 1, Fig. 8) when viewed from above (Fig. 8 is top view).
Regarding claim 10, Ashida in view of Akagi teaches the semiconductor device according to claim 1, wherein
Ashida further teaches that
when viewed from above (Fig. 9a), a size of the second electrode (electrode for gate 104, Fig. 9a, [0058]) is smaller than a size of the first electrode (electrode for source 105, Fig. 9a, [0058]).
Regarding claim 11, Ashida in view of teaches the semiconductor device according to claim 1, wherein
Ashida further teaches that the semiconductor device comprises
an insulating film (insulating protect layer 103, Fig. 9a, [0058]) provided on the semiconductor chip (semiconductor chip 1, Fig. 9a), the insulating film (insulating protect layer 103, Fig. 9a) being in contact with the first connector (header for source 5, Figs. 2 and 8: even though the semiconductor chip of Ashida is replaced by semiconductor chip of Akagi, the insulating protect layer would be still on the semiconductor chip contacting the first connector becasue “protect layer 103 is for preventing an electrical short through a side surface of the semiconductor chip 1 between after-mentioned joint member for drain 6 and joint member for source 4 when joining the semiconductor chip 1 and electrically conductive members (lead, header) with each other.” ([0035]) and “the protect layer 103 is arranged between the peripheral edge of the semiconductor chip 1 and each of the electrode for gate 104 and electrode for source 105 and between the electrode for gate 104 and electrode for source 105.” ([0035]).
Claim 6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Ashida (US 2006/0043618 A1) in view of Akagi (US 2014/0151785 A1) as applied to claims 1-2 and 10-11 above, and further in view of Noda (US 2021/0398962 A1).
Regarding claim 6, Ashida and Akagi teaches the semiconductor device according to claim 1, wherein,
Ashida further teaches that the semiconductor device comprises
a second connector (lead for gate 3, Fig. 8, [0059]).
Ashida and Akagi, however, do not teach that
a second post is provided separately from the die pad; and
second connector is electrically connected to the second post, the second connector including
a first portion electrically connected to the second electrode, and
a second portion connected to the first portion, a distance between the second portion and the upper surface is longer than a distance between the first portion and the upper surface.
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Noda, on the other hand, teaches a semiconductor device (semiconductor device 1, Fig. 1A-B, [0015]) comprising multiple switching elements (switching elements 10, and 20, Fig. 1A-B, each switching element is analogous to the semiconductor device of Ashida in view of Akagi, [0015]-[0016]) on a lead frame comprising leads 30, 40, 60, and 70, Fig. 1A-B, [0016]), wherein the leads (source terminal 13S connected to lead 60 and gate terminal (not shown in figures) connected to control lead 70, Fig. 1A, [0015]) of the switching element (including the semiconductor chip 15, Illustrative Fig. 3) are connected to lead frame by bending the terminals towards the lead frame (see Illustrative Fig. 3, which is an annotated version of Fig. 1 A). Therefore, Noda teaches that the semiconductor device (semiconductor device 1, Fig. 1A-B, [0015]) comprises
a second post (control lead 70, Illustrative Fig. 3) provided separately from the die pad (lead 11 (analogous to the die pad of Ashida in view of Akagi shown in Illustrative Fig. 1), Illustrative Fig. 3, [0018]); and
a second connector (analogous to the lead for gate 3 of Ashida in view of Akagi shown in Illustrative Fig. 1), see Illustrative Fig. 3 illustrating how the second connector should look like) is electrically connected to the second post (control lead 70, [0028]: “The control lead 70 is electrically connected to the gate of the semiconductor chip 15”), the second connector (see Illustrative Fig. 3) including
a first portion (first portion, Illustrative Fig. 3) electrically connected to the second electrode (gate electrode (not shown in figures, but similar to the source electrode connection, Illustrative Fig. 3), and
a second portion (second portion, Illustrative Fig. 3) connected to the first portion (first portion, Illustrative Fig. 3), a distance between the second portion (second portion, Illustrative Fig. 3) and the upper surface (upper surface, Illustrative Fig. 3) is longer than a distance between the first portion (first portion, Illustrative Fig. 3) and the upper surface (upper surface, Illustrative Fig. 3: first portion is on the same horizontal plane as the upper surface, whereas the second portion is below the upper surface).
Therefore, a person of ordinary skill in the art before effective filing date of the claimed invention, who is aiming to mount the semiconductor device of Ashida in view of Akagi on a lead frame to form a device with multiple switching elements, would be motivated to pursue the teachings of Noda to include a second post separately from the die pad and electrically connect the second electrode and the second post with the second connector by bending the connector towards the second post to form a first portion and second portion as taught by Noda. Thus, the combination of Ashida, Akagi and Noda teach all the limitations of claim 6.
Regarding claim 9, Ashida in view of Akagi teaches the semiconductor device according to claim 1, wherein
Ashida further teaches that the semiconductor device comprises
a second connector (lead for gate 3, Fig. 8, [0059]) provided in a slot (notch 36, Fig. 8, [0059]) of the first connector (header for source 5, Fig. 8, [0059]).
Ashida and Akagi, however, do not teach that
a second post provided separately from the die pad; and
the second connector electrically connecting the second electrode and the second post.
Noda, on the other hand, teaches a semiconductor device (semiconductor device 1, Fig. 1A-B, [0015]) comprising multiple switching elements (switching elements 10, and 20, Fig. 1A-B, each switching element is analogous to the semiconductor device of Ashida in view of Akagi, [0015]-[0016]) on a lead frame comprising leads 30, 40, 60, and 70, Fig. 1A-B, [0016]), wherein the leads (source terminal 13S connected to lead 60 and gate terminal (not shown in figures) connected to control lead 70, Fig. 1A, [0015]) of the switching element (including the semiconductor chip 15, Illustrative Fig. 3) are connected to lead frame by bending the terminals towards the lead frame (see Illustrative Fig. 3, which is an annotated version of Fig. 1 A). Therefore, Noda teaches that the semiconductor device (semiconductor device 1, Fig. 1A-B, [0015]) comprises
a second post (control lead 70, Illustrative Fig. 3) provided separately from the die pad (lead 11 (analogous to the die pad of Ashida in view of Akagi shown in Illustrative Fig. 1), Illustrative Fig. 3, [0018]); and
the second connector (while not shown in figure, gate lead (analogous to the lead for gate 3 of Ashida in view of Akagi, Illustrative Fig. 1), see Illustrative Fig. 3 illustrating how the second connector should look like) electrically connecting the second electrode (gate electrode) and the second post (control lead 70, [0028]: “The control lead 70 is electrically connected to the gate of the semiconductor chip 15”).
Therefore, a person of ordinary skill in the art before effective filing date of the claimed invention, who is aiming to mount the semiconductor device of Ashida in view of Akagi on a lead frame to form a device with multiple switching elements, would be motivated to pursue the teachings of Noda to include a second post separately from the die pad and electrically connect the second electrode and the second post with the second connector by bending the connector towards the second post. Thus, the combination of Ashida, Akagi and Noda teach all the limitations of claim 9.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Miyakawa (US 2018/0090422 A1) teaches a semiconductor device comprising a die pad, a semiconductor chip and two connectors encapsulated in a sealant, which is relevant to all claims.
Inoue (US 2019/0295933 A1) teaches a semiconductor device comprising a die pad, a semiconductor chip and two connectors encapsulated in a sealant, which is relevant to all claims.
Murakami (US 2005/0012112 A1) teaches a semiconductor device comprising a die pad, a semiconductor chip and two connectors encapsulated in a sealant, which is relevant to all claims.
Fukui (US 2015/0221580 A1) teaches a semiconductor device comprising a die pad, a semiconductor chip and two connectors encapsulated in a sealant, which is relevant to all claims.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812