DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim language in the following claim is not clearly understood:
As per claim 10, it is unclear whether “at least two kernels”, “different compute circuits”, and “a single buffer” are referring to one of the “plurality of kernels”, “plurality of compute circuits” and “a set of buffers” in claim 1 (i.e. consistent term should be used with “the” or “said” if they are the same)
As per claim 11, it is unclear whether “first kernel”, “a device buffer” and “second kernel” referring to one of “the set of buffers” and “plurality of kernels” in claim 1 (i.e. consistent term should be used with “the” or “said” if they are the same)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 8, 10-16, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kinsner et al. US Pub 2022/0197613 (hereafter Kinsner) in view of Goel et al. US Pub 2024/0248853 (hereafter Goel).
As per claim 1, Kinsner teaches the invention substantially as claimed including a method, comprising: receiving, by a hardware processor, a plurality of kernels and a graph including a plurality of nodes corresponding to the plurality of kernels, wherein the graph defines a control flow and a data flow for the plurality of kernels (para[0084, 0111-0112, 0117-0119], FIG. 10, a task graph is originated from code with kernels, that uses data and control dependencies to define how kernels are invoked and when data should be moved between the accelerator devices, thus the graph defines control and data flow for the kernels);
implementing, by the hardware processor, the plurality of kernels within different ones of a plurality of compute circuits coupled to the hardware processor (para[0097-0098, 0111-0112, 0117-0120, 0129], the accelerators 870 represents different types of hardware accelerators where the tasks are executed, and program the bitstream (kernels) to accelerator devices according to the graph);
and invoking, by the hardware processor, different ones of the plurality of kernels as implemented in the plurality of compute circuits based on the control flow defined by the graph (para[0084, 0118, 0129-0130], kernels of the code are executed (invoked) using the accelerator devices using the information about how quickly kernels should complete based on downstream data and control dependencies of the task graph).
Kinsner does not explicitly teach allocating a set of buffers for performing a job for the graph, wherein the allocating is based, at least in part, on the data flow specified by the graph.
However, Goel teaches allocating a set of buffers for performing a job for the graph, wherein the allocating is based, at least in part, on the data flow specified by the graph (para[0107, 0110-0112], FIG. 8, the graph is implemented by inserting buffers (between nodes and between stages in the graph) based on the dataflow information of the graph).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Goel’s teaching to Kinsner’s invention in order to provide a technology implementing efficient distributed computing by allowing an array of accelerators attached to separate hosts to directly communicate with each other via buffers, and dynamically select the most efficient data passing method for a given set of source and target devices in an application defined pipeline based on the latency and bandwidth requirement of the operating device stages (para[0130, 0132]).
As per claim 2, Kinsner and Goel teach the method of claim 1, Goel teaches wherein the different ones of the plurality of kernels share data during execution via the set of buffers as allocated (para[0110-0112, 0130-0132], kernels of the different accelerators communicate with each other via buffers).
As per claim 3, Goel teaches wherein the graph specifies the data flow by defining one or more input buffers and one or more output buffers for each kernel (para[0110-0112, 0130-0132], there are input buffers to the node (kernel) and output buffers from the node in the graph).
As per claim 4, Kinsner teaches wherein the graph specifies the control flow by, for each kernel, specifying a next node to be executed, a plurality of next nodes to be executed in parallel, or that no further node is executed (para[0112, 0114-0115], FIG. 10, graph represents the control flow for each kernel, relationship and dependencies between the kernels, and specifying the next node (kernel 2) to be executed after kernel 1).
As per claim 5, Kinsner wherein the plurality of kernels are specified in a file of high-level programming language source code that includes buffer metadata defining requirements of each buffer (para[0110, 0112, 0153], application source code written in high level program source code specifies kernels).
In addition, Goel teaches source code that includes buffer metadata defining requirements of each buffer; and wherein the set of buffers is determined based on the requirements of each buffer determined by the hardware processor by querying the file including the buffer metadata (para[0048-0050, 0107, 0110-0115, 0123, 0198], compiler converts the high level program with user algorithms and functions to the dataflow graphs, where the user-defined metadata of data passing includes number of configured multiple buffers and memory allocations are specified in the configuration file).
As per claim 8, Kinsner teaches further comprising: at runtime, executing graph generation program code that is executable to generate the graph at runtime (para[0111-0113, 0118], task graph generator generates task graph at runtime).
As per claim 10, Goel teaches further comprising: in response to at least two kernels executing in different compute circuits of the plurality of compute circuits disposed in a same device, sharing a single buffer among the at least two kernels (para[0110-0113, 0145-0148], FIG. 8, a buffer between the two nodes is a single buffer accessed/shared among the kernels of the nodes).
As per claim 11, Goel teaches wherein the invoking different ones of the plurality of kernels comprises: writing, by a first kernel, to a device buffer as allocated; passing, by the first kernel, a handle to the device buffer to a second kernel; and accessing, by the second kernel, the device buffer (para[0110-0113, 0145-0148], FIG. 8, data transfer from one node (write to the buffer) to the next node (read from the buffer) via buffer).
As per claim 12, it is a system claim of claim 1 above, thus it is rejected for the same rationale.
As per claim 13, it is a system claim of claim 2 above, thus it is rejected for the same rationale.
As per claim 14, it is a system claim of claim 3 above, thus it is rejected for the same rationale.
As per claim 15, it is a system claim of claim 4 above, thus it is rejected for the same rationale.
As per claim 16, it is a system claim of claim 5 above, thus it is rejected for the same rationale.
As per claim 19, it is a system claim of claim 8 above, thus it is rejected for the same rationale.
Claim(s) 6-7, 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kinsner in view of Goel as applied to claim 1 above, and further in view of Sood et al. US Pub 2025/0044983 (hereafter Sood).
As per claim 6, Kinsner and Goel teach the method of claim 1, but they do not explicitly teach wherein the allocating further comprises: at runtime, generating a graph buffer pool that creates the set of buffers for performing the job for the graph; and maintaining a buffer pool stack for the graph, wherein the buffer pool stack is configured to store graph buffer pools for the graph while not in use.
However, Sood teaches at runtime, generating a graph buffer pool that creates the set of buffers for performing the job for the graph(para[0085-0086, 0121], FIG. 3 and 5, each consumer node is assigned data buffers, thus a pool of buffers for each node is generated to perform operations);
and maintaining a buffer pool stack for the graph, wherein the buffer pool stack is configured to store graph buffer pools for the graph while not in use (para[0085-0092], FIG. 3, maintain the data buffer pool to store buffer A, B and C, and the states of the buffers are indicated as free, full, empty or active, thus buffers are stored while not in use (free/empty)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Sood’s teaching to Kinsner and Goel’s invention in order to provide a technique which enables fast and efficient transfer of high bandwidth data and critical control signals to maximize the throughput of heavy workloads on the system, where the data buffers for each node are shared to eliminate unnecessary data copies and improve the performance significantly (para[0017, 0021]).
As per claim 7, Kinsner, Goel and Sood teach the method of claim 6, and Kinsner teaches in response to a new job being queued for the graph (para[0115], a new work is enqueued for the graph);
In addition, Goel teaches no graph buffer pool being available in the buffer pool stack for the graph, creating a new graph buffer pool for the new job for the graph (para[0124, 0146, 0153-0154], FIG. 13, allocate a new buffer space (multiple buffers) for the new operations performed by the nodes).
As per claim 17, it is a system claim of claim 6 above, thus it is rejected for the same rationale.
As per claim 18, it is a system claim of claim 7 above, thus it is rejected for the same rationale.
Claim(s) 9 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kinsner in view of Goel as applied to claim 1 above, and further in view of Burger et al. US Pub 2017/0083320 (hereafter Burger).
As per claim 9, Kinsner and Goel teach the method of claim 1, but they do not explicitly teach wherein the graph includes logic that, upon execution, selects one of a plurality of conditional branches within the graph based on a value returned by a selected kernel of the plurality of kernels.
However, Burger teaches the graph includes logic that, upon execution, selects one of a plurality of conditional branches within the graph based on a value returned by a selected kernel of the plurality of kernels (para[0121, 0126, 0130], FIG. 12, conditional path (1212, 1214) for source code is selected based on the value of the node 1210, in the data flow graph 1200).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Burger’s teaching to Kinsner and Goel’s invention in order to provide a compilation method of generating a control data flow graph of the program from a source code having conditional paths in the graph, where the conditional paths are analyzed and rearranged to allow improved computational efficiency in terms of speed, memory and power during the execution of the instruction block (para[0005, 0042, 0130)).
As per claim 20, it is a system claim of claim 9 above, thus it is rejected for the same rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Poornachandran et al. US Pub 2022/0327267 teaches an apparatus for generating logic to be performed by computing circuitry of a computing architecture. The apparatus is configured to determine a performance-critical compute path of a compute kernel to be executed on a plurality of units of computing circuitry of a computing architecture, the compute kernel comprising a plurality of interdependent groups of computational instructions, with the performance-critical compute path being based on a subset of the interdependent groups of computational instructions.
Sastry et al. US Patent No. 11,138,019 teaches a method for determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, building a routing graph of all possible routing choices in the DPE array for communicate channels between DPEs and circuitry of the application configured in programmable logic of the SOC.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAMMY EUNHYE LEE whose telephone number is (571)270-7773. The examiner can normally be reached Mon, Tues, Thur 9PM-4PM.
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/TAMMY E LEE/Primary Examiner, Art Unit 2195
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