DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 7 and 10-33 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II and/or Device Embodiments 2-6, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/21/2026.
Applicant’s election without traverse of Invention I, Device Embodiment 1 in the reply filed on 01/21/2026 is acknowledged.
Claim Objections
Claim 8 is objected to because of the following informalities: the last line of claim 8 recites the limitation “and a connection region connection the first region and second region” Examiner interprets the second recitation of “connection” as a typo and for purposes of examination has interpreted the limitation as “and a connection region connecting the first region and second region”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4 and 7-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hinoue et al. (US 10,950,627 B1, hereinafter Hinoue ‘627).
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With respect to Claim 1 Hinoue ‘627 discloses a semiconductor memory device (Fig 1-13C) comprising:
a gate stack (32/46, Fig 12F, Col 24, Lines 58-65) including a first concave portion (first concave portion of gate stack shown in annotated Fig 12E of Hinoue ‘627, hereinafter FCP-GS) and a second concave portion (second concave portion of gate stack shown in annotated Fig 12E of Hinoue ‘627, hereinafter SCP-GS), the first (FCP-GS) and second concave portions (SCP-GS) facing opposite directions based on a straight line (line in hd2 direction) on a geometric plane (annotated Fig 12E of Hinoue ‘627 discloses FCP-GS and SCP-GS facing opposite directions of hd2 on the plane of layer 46);
an insulating pillar (62, Fig 12E, Col 25, Lines 62-64) having a first convex portion (first convex portion of insulating pillar shown in annotated Fig 12E of Hinoue ‘627, hereinafter FCP-IP) facing (disclosed in annotated Fig 12E of Hinoue ‘627) the first concave portion of the gate stack (FCP-GS) and a second convex portion (second convex portion of insulating pillar shown in annotated Fig 12E of Hinoue ‘627, hereinafter SCP-IP) facing (disclosed in annotated Fig 12E of Hinoue ‘627) the second concave portion of the gate stack (SCP-GS);
a first channel segment (60B, Fig 12E, Col 25, Lines 66-67 and Col 26, Line 1) extending along (disclosed in annotated Fig 12E of Hinoue ‘627) the first convex portion of the insulating pillar (FCP-IP);
a second channel segment (60A, Fig 12A, Col 25, Lines 64-66) extending along (disclosed in annotated Fig 12E of Hinoue ‘627) the second convex portion of the insulating pillar (SCP-IP);
a channel separation structure (region of 148B between end of etch stop liner 142 and planar wall 133 of insulating pillar 62 as denoted by the circle in annotated Fig 12E of Hinoue ‘627, Col 27, Lines 21-30, here in after CSS) extending from (disclosed in annotated Fig 12E of Hinoue ‘627) the insulating pillar (62) to between an end (top end of 60B as shown in annotated Fig 12E of Hinoue ‘627) of the first channel segment (60B) and an end (top end of 60A as shown in annotated Fig 12E of Hinoue ‘627) of the second channel segment (60A);
a first data storage segment (50B, Fig 12E, Col 26, Lines 4-5) located between (disclosed in annotated Fig 12E of Hinoue ‘627) the first channel segment (60B) and the first concave portion of the gate stack (FCP-GS); and
a second data storage segment (50A, Fig 12E, Col 26, Lines 2-3) located between (disclosed in annotated Fig 12E of Hinoue ‘627) the second channel (60A) segment and the second concave portion of the gate stack (SCP-GS),
wherein a width of each of the first data storage segment (50B) and the second data storage segment (50A) becomes narrower as each of the first data storage segment (50B) and the second data storage segment (50A) is close the channel separation structure (CSS)(annotated Fig 12E of Hinoue ‘627 discloses that the ends of 50A and 50B become narrower (note pointed shape at ends) as they become close to CSS).
With respect to Claim 3 Hinoue ‘627 discloses all limitations of the semiconductor memory device of claim 1, and Hinoue ‘627 further discloses wherein each of the first channel segment (60B) and the second channel segment (60A) comprises:
an inner concave portion (inner concave portion of 60B and 60A as shown in annotated Fig 12E of Hinoue ‘627) facing (disclosed in annotated Fig 12E of Hinoue ‘627) the insulating pillar (62); and
an outer convex portion (outer convex portion of 60B and 60A as shown in annotated Fig 12E of Hinoue ‘627) facing (disclosed in annotated Fig 12E of Hinoue ‘627) the gate stack (32/46), and
wherein a curvature of the outer convex portion (curvature of outer convex portion of 60B and 60A as shown in annotated Fig 12E of Hinoue ‘627) is substantially the same as a curvature of the inner concave portion (curvature of inner concave portion of 60B and 60A as shown in annotated Fig 12E of Hinoue ‘627) (annotated Fig 12E discloses the curvatures of the outer convex portion of 60B and 60A substantially the same as the curvature of inner concave portion of 60B and 60A).
With respect to Claim 4 Hinoue ‘627 discloses all limitations of the semiconductor memory device of claim 1, and Hinoue ‘627 discloses further comprising:
a blocking insulating layer (52, Fig 12E, Col 21, Line 50) located between outside surfaces of the first (50B) and second data storage segments (50A) and the gate stack (32/46) (Fig 12E discloses layer 52 between outsides of 50B and 50A and the gate stack 32/46); and
a tunnel insulating layer (56, Fig 12E, Col 21, Line 51) extending along outer convex-shaped surfaces of the first (60B) and second channel segments (60A), the outer convex-shaped surfaces facing the gate stack (32/46)(annotated Fig 12E of Hinoue ‘742 discloses 56 extending along outer convex surfaces of 60B and 60A which are facing the gate stack 32/46).
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With respect to Claim 8 Hinoue ‘627 discloses all limitations of the semiconductor memory device of claim 1, and Hinoue ‘627 further discloses wherein the gate stack (32/46) includes a plurality of conductive layers (46, Fig 11A, Col 24, Lines 58-65) spaced apart from each other (disclosed in Fig 11A and Col 24, Lines 64-65) and stacked along a direction (vertical direction as shown in Fig 11A), which is orthogonal to the straight line (line in hd2 direction as shown in Fig 12E which is into the plane of the image of 11A), and
each conductive layer (46) comprises:
a first region (first region of 46 as shown in annotated Fig 12B of Hinoue ‘627) surrounding a first outer portion (first outer portion of 50B as shown in annotated Fig 12B of Hinoue ‘627) of the first data storage segment (50B);
a second region (second region of 46 as shown in annotated Fig 12B of Hinoue ‘627) surrounding a second outer portion (second outer portion of 50A as shown in annotated Fig 12B of Hinoue ‘627) of the second data storage segment (50A);
and a connection region (connection region between first and second region of 46 shown in annotated Fig 12B of Hinoue ‘742) connection (see Examiner’s interpretation of “connection” as “connecting” the first region (first region of 46 as shown in annotated Fig 12B of Hinoue ‘627) and the second region (second region of 46 as shown in annotated Fig 12B of Hinoue ‘627).
With respect to Claim 9 Hinoue ‘627 discloses all limitations of the semiconductor memory device of claim 1, and Hinoue ‘627 further discloses wherein the channel separation structure (CSS) includes a semiconductor oxide (Col 19, Lines 35-36 discloses 62L as silicon oxide and Col 21, Lines 51-52 disclose 62 comprises the layers 62L).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Hinoue ‘627 in view of Gao et al. (US 2022/0123012 A1, hereinafter Gao ‘012), in view of the following arguments.
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With respect to Claim 2 Hinoue ‘627 discloses all limitations of the semiconductor memory device of claim 1, and Hinoue ‘627 further discloses wherein an outer convex portion (outer convex portion of 50B as shown in Fig 12E) of the first data storage segment (50B) faces a first portion of the gate stack (left portion of 32/46 as shown on Fig 12) (annotated Fig 12E of Hinoue ‘627 shown an outer convex portion of 50B facing a portion of the gate stack 32/46),
wherein an outer convex portion (outer convex portion of 50A as shown in Fig 12E) of the second data storage segment (50A) also faces a second portion of the gate stack (right portion of 32/46 as shown on Fig 12) (annotated Fig 12E of Hinoue ‘627 shown an outer convex portion of 50A facing a portion of the gate stack 32/46), and
wherein the outer convex portions (outer convex portion of 50A and 50B as shown in Fig 12E) of the first (50B) and second data storage segments (50A) contact an inner concave portion (inner concave portion of 46, annotated Fig 12E discloses outer convex portions of 50A and 50B contacts inner concave portions of 46)
But Hinoue fails to explicitly disclose an elliptically-shaped ring.
Nevertheless, in a related endeavor (Fig 1-2A of Gao ‘012), Gao ‘012 teaches an elliptically shaped (Fig 2A of Gao ‘012 shows a memory device 18a with an elliptical shape) ring (212, Fig 2A, Para [0049]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Gao ‘012’s teaching of an elliptically shaped memory device into Hinoue ‘742’s device. Hinoue ‘742 teaches a memory structure with a memory channel opening as oval but Hinoue ‘742 is open to other shapes for the memory channel opening as Hinoue ‘742 teaches in Col 15, Lines 49-51 can be “any other suitable shape”. Gao ‘012 also teaches a memory structure and further teaches that the memory channel can have various shapes. Therefore the ordinary artisan would have been motivated to modify Hinoue ‘742 in the manner set forth above, at least, because, as Gao ‘012 teaches in Para [0038] using an elliptical shape for the memory channel can help to improve the bit density of the device. Further, the person of ordinary skill in the art would be motivated to use the elliptically shaped ring 212 of Gao ‘012 as this structure would provide an additional layer of dielectric protection to the memory channel thereby reducing the possibility of charge leakage from the channel.
As incorporated, the elliptical shape of the memory channel structure taught by Gao ‘012 would be used as the shape of the memory channel structure shown in Fig 12E of Hinoue ‘742 (the shape would be an ellipse instead of an oval) and the ring (212 of Gao ‘012) would be incorporated as the shape of layer 52 of Hinoue ‘742. Therefore, the outer convex portions of the first (50B of Hinoue ‘742) and second data storage segment (50B of Hinoue ‘742) contact an inner concave portion of an elliptically (elliptical shape of memory channel structure taught by Gao ‘012) shaped ring (dielectric layer 52 plus outer layer of CSS (both are silicon oxide) would form an elliptical shaped ring) as incorporated in Hinoue ‘742).
With respect to Claim 5 Hinoue ‘627 discloses all limitations of the semiconductor memory device of claim 4, but Hinoue ‘627 fails to explicitly disclose wherein the shape of at least one of the blocking insulating layer and the tunnel insulating layer is an elliptically-shaped ring.
Nevertheless, in a related endeavor (Fig 1-2A of Gao ‘012), Gao ‘012 teaches wherein the shape of at least one of the blocking insulating layer (212, Fig 2A, Para [0049]) and the tunnel insulating layer (208, Fig 2A of Gao ‘012, Para [0049]) is an elliptically-shaped ring (Fig 2A of Gao ‘012 shows a memory device 18a with an elliptical shape).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Gao ‘012’s teaching of wherein the shape of at least one of the blocking insulating layer and the tunnel insulating layer is an elliptically-shaped ring into Hinoue ‘742’s device. Hinoue ‘742 teaches a memory structure with a memory channel opening as oval but Hinoue ‘742 is open to other shapes for the memory channel opening as Hinoue ‘742 teaches in Col 15, Lines 49-51 can be “any other suitable shape”. Gao ‘012 also teaches a memory structure and further teaches that the memory channel can have various shapes. Therefore the ordinary artisan would have been motivated to modify Hinoue ‘742 in the manner set forth above, at least, because, as Gao ‘012 teaches in Para [0038] using an elliptical shape for the memory channel can help to improve the bit density of the device. Further, the person of ordinary skill in the art would be motivated to use the elliptically shaped tunnel insulating layer 208 and blocking insulating layer 212 of Gao ‘012 as this structure would provide an additional layers of dielectric protection to the memory channel thereby reducing the possibility of charge leakage from the channel.
As incorporated, the shape of at least one of the blocking insulating layer (208) and the tunnel insulating layer (212) is an elliptically-shaped ring taught by Gao ‘012 would be used as the shape insulating layer 52 (dielectric layer 52 plus outer layer of CSS (both are silicon oxide) would form an elliptical shaped ring) of Hinoue ‘742 and the tunnel insulating layer 56 of Hinoue ‘742 (dielectric layer 56 plus layer of CSS (both are silicon oxide) would form an elliptical shaped ring).
With respect to Claim 6 Hinoue ‘627 as modified by Gao ‘012 discloses all limitations of the semiconductor memory device of claim 5, and Hinoue ‘627 as modified by Gao ‘012 further discloses wherein the channel separation structure (CSS of Hinoue ‘627) and the insulating pillar (62 of Hinoue ‘627)
And Gao ‘012 further teaches are located inside the elliptically shaped ring (Fig 2A of Gao ‘012 shows a memory device 18a with an elliptical shape).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Gao ‘012’s teaching of an elliptically shaped memory device into Hinoue ‘742 as modified by Gao ‘012’s device. Hinoue ‘742 as modified by Gao ‘012 teaches a memory structure with a memory channel opening as oval but Hinoue ‘742 as modified by Gao ‘012 is open to other shapes for the memory channel opening as Hinoue ‘742 teaches in Col 15, Lines 49-51 can be “any other suitable shape”. Gao ‘012 also teaches a memory structure and further teaches that the memory channel can have various shapes. Therefore the ordinary artisan would have been motivated to further modify Hinoue ‘742 as modified by Gao ‘012 in the manner set forth above, at least, because, as Gao ‘012 teaches in Para [0038] using an elliptical shape for the memory channel can help to improve the bit density of the device.
As incorporated, the elliptical shape of the memory channel structure taught by Gao ‘012 would be used as the shape of the memory channel structure shown in Fig 12E of Hinoue ‘742 (the shape would be an ellipse instead of an oval) Therefore, the outer convex portions of the first (50B of Hinoue ‘742) and second data storage segment contact (50B of Hinoue ‘742) an inner concave portion of an elliptically shaped ring (shape taught by Gao ‘012).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898