DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Response to Amendment
This Office Action is in response to the amendments filed on 02/19/2026.
Applicant’s amendments filed 02/19/2026 have been fully considered and reviewed by the examiner. The examiner notes the amendment of claim 6.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Regarding claim 6, the limitation "like PN diode power devices" renders the claim indefinite because the claim 6 includes elements not actually disclosed (those encompassed by "like"), thereby rendering the scope of the claim(s) unascertainable. See MPEP § 2173.05(d).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claims 1 and 2 are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by US 2010/0187577 to Lin et al. (hereinafter Lin).
With respect to Claim 1, Lin discloses a method of forming a semiconductor structure comprising at least one PN diode power device (e.g., a method of forming a diode device 20 comprising at least one PN junction formed between the buried region and the active region) (Lin, Fig. 1, ¶0012-¶0026), the method comprising:
forming an active region (e.g., N-type layer 26/48 on the P-type substrate 21) (Lin, Fig. 1, ¶0013, ¶0026);
forming a buried well (e.g., P-type buried region 38) (Lin, Fig. 1, ¶0013, ¶0026) in the active region (26/48), the buried well (38) having a first conductivity type (e.g., P-type);
forming an anode region (e.g., P+ type region 42 connected to the P-type buried region 38 with the P-type region 36) (Lin, Fig. 1, ¶0013, ¶0026), having the first conductivity type (e.g., P-type), in the active region (26) through (e.g., implantation, as known in the prior art, is performed on the upper surface 22 of the substrate 21 to form doped region 42) (Lin, Fig. 1, ¶0020, ¶0026) an upper surface (22) of the active region (26/48), the anode region (42) being electrically connected to the buried well (38);
forming a cathode region (e.g., N-type region 28 in the N-type regions 26/29) (Lin, Fig. 1, ¶0013, ¶0026), having a second conductivity type (e.g., N-type), in the active region (26/48) through (e.g., implantation, as known in the prior art, is performed on the upper surface 22 of the substrate 21 to form doped region 28) (Lin, Fig. 1, ¶0020, ¶0026) the upper surface (22) of the active region (26/48) and disposed laterally from the anode region (42);
forming a cathode terminal (244/301/311) (Lin, Fig. 1, ¶0013-¶0014, ¶0026) electrically connected to the cathode region (28); and
forming an anode terminal (241-243/302/312) (Lin, Fig. 1, ¶0013-¶0014, ¶0026) electrically connected to the anode region (42);
wherein:
the buried well (38) is configured, in conjunction with the cathode region (28), to form a clamping diode (e.g., electrical potential near junction 50 formed by conductor portions 242 on the upper surface 22 of the active region 26 is clamped between the cathode region 28 and the anode region 42, to clamp leakage current and to obtain higher breakdown voltage) (Lin, Fig. 1, ¶0017-¶0018) operative to position a breakdown avalanche region (e.g., a lateral location 381/382/383/384 of the buried region 38 is placed to control the breakdown voltage, generally less than the breakdown voltage of the junction 58) between the buried well (38) and the cathode terminal (244/301/311), a breakdown voltage of the at least one PN diode power device being a function of one or more characteristics of the buried well (e.g., a lateral location 381/382/383/384 of the buried region 38);
the buried well (38) is formed proximate a lower surface of the active region (26/48) and extends from the anode region (42) to a location (e.g., a lateral location 381/382/383/384) proximate the cathode region (28); and
the anode region (42) (Lin, Fig. 1, ¶0015-¶0018) is formed on at least a portion of the buried well (38) and extends along the upper surface (22) of the active region (26) 1) to the anode terminal (e.g., 241-243/302/312) to make electrical contact to the anode terminal (e.g., 241-243/ 302/312) and 2) to the cathode region (28) to form a PN junction (e.g., the end of the P-type buried region 38 at the location 381/382/383/384 form a PN junction with the N -type active region 26/29 at the cathode region 28) of the at least one PN diode power device with the cathode region (28).
Regarding claim 2, Lin discloses the method of claim 1. Further, Lin discloses the method, further comprising: forming a gate structure (e.g., P-type region 40 of the JEFT 56) (Lin, Fig. 1, ¶0017-¶0018) above the active region (26) proximate the upper surface (22) of the active region, at least partially between the cathode region (28) and the anode region (42), and electrically connected to the anode terminal (243/302/312); wherein: the gate structure (40) overlaps the PN junction (e.g., the end of the P-type buried region 38 at the location 382 form a PN junction with the N -type active region 26); and the gate structure (40) is configured to control an electric field distribution (e.g., electrical potential near junction 50 formed by conductor portions 242 on the upper surface 22 of the active region 26 is clamped) proximate the PN junction.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over US 2010/0187577 to Lin in view of Kocon et al. (US 2011/0303976, hereinafter Kocon).
Regarding claim 3, Lin discloses the method of claim 2. Further, Lin does not specifically disclose the method, further comprising: forming a shielding structure proximate the upper surface of the active region between the gate structure and the cathode terminal, wherein the shielding structure comprises a field plate configured to control an electric field distribution along a top oxide interface away from an edge of the gate structure nearest the cathode terminal.
However, Kocon teaches forming a diode structure (Kocon, Fig. 7, ¶0006, ¶0021) comprising a shielding structure (7018) proximate the upper surface of the active region (7006) between the gate structure (7008) and the cathode terminal (7012), wherein the shielding structure (7018) comprises a field plate (e.g., above the drift region7014) configured to control an electric field distribution along a top oxide interface away from an edge of the gate structure (7008) nearest the cathode terminal (7012), to control an electric field across the drift region underlying the shielding structure to reduce operating power for high frequency and high voltage applications (Kocon, ¶0021).
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the method of Lin by forming a shielding structure overlying a portion of the drift region between the gate and the cathode as taught by Kocon to have the method, further comprising: forming a shielding structure proximate the upper surface of the active region between the gate structure and the cathode terminal, wherein the shielding structure comprises a field plate configured to control an electric field distribution along a top oxide interface away from an edge of the gate structure nearest the cathode terminal, in order to control an electric field across the drift region underlying the shielding structure to reduce operating power for high frequency and high voltage applications (Kocon, ¶0006, ¶0021).
Claim 4 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over US 2010/0187577 to Lin in view of Coe (US Patent No. 4,754,310).
Regarding claim 4, Lin discloses the method of claim 2. Further, Lin discloses the method, wherein the anode electrode (302/312) is electrically connected to the buried well (38) and the anode region (36/42) by a conductive layer (e.g., silicide layer 241) (Lin, Fig. 1, ¶0013-¶0014, and the anode electrode (302/312) is electrically connected to the gate structure (40) by a lateral extension (242/243) of the conductive layer (241) outside of the anode region (36/42), to provide low resistance path between the anode and the cathode.
Further, Lin does not specifically disclose the method, further comprising: forming an anode trench in the active region, wherein the anode terminal is disposed at least in part in the anode trench, the anode terminal is electrically connected to the buried well and the anode region in the anode trench by a conductive layer, and the anode terminal is electrically connected to the gate structure by a lateral extension of the conductive layer outside of the anode trench.
However, Coe teaches forming a PN diode device (Coe, Fig. 1, Col. 2, lines 21-61; Col. 7, lines 27-67; Col. 8, lines 148; Col. 11, lines 31-67; Col. 12, lines 1-8) comprising a P -type anode region (14) in an anode trench (22), wherein the anode terminal (24) is disposed at least in part in the anode trench (22) and electrically connected to the buried well (e.g., bottom P-type layer 12) and the anode region (14) in the anode trench (22), wherein the P- type anode region (14) forms PN junction (5) with the body region (3) including N-type regions (11), to provide a diode device with controlled breakdown voltage to increase voltage and current handling capabilities of the device.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the method of Lin by forming an anode trench including P-type anode region and the anode electrode in the anode trench connected to the buried layer as taught by Coe, wherein a conductive layer including silicide or other high work function conductors is formed between the anode electrode and the anode region as taught by Lin to have the method, further comprising: forming an anode trench in the active region, wherein the anode terminal is disposed at least in part in the anode trench, the anode terminal is electrically connected to the buried well and the anode region in the anode trench by a conductive layer, and the anode terminal is electrically connected to the gate structure by a lateral extension of the conductive layer outside of the anode trench, in order to provide a diode device with controlled breakdown voltage to increase voltage and current handling capabilities of the diode device; and to provide silicide layer to form low resistance path between the anode and the cathode (Coe, Col. 2, lines 21-61; Col. 7, lines 27-61; Col. 11, lines 31-40; Col. 12, lines 3-8; Lin, ¶0013-¶0014).
Claim 5 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over US 2010/0187577 to Lin in view of Coe (US Patent No. 4,754,310) and Alter (US 2004/0245631).
Regarding claim 5, Lin discloses the method of claim 1. Further, Lin does not specifically disclose the method, further comprising: forming a macro-cell that includes a plurality of the at least one PN diode power devices; and forming a plurality of the macro-cells for the semiconductor structure connected together to operate as a single PN diode power device.
However, Coe teaches forming a PN diode device (Coe, Figs. 1-2, Col. 2, lines 21-61; Col. 7, lines 27-67; Col. 8, lines 148; Col. 11, lines 31-67; Col. 12, lines 1-8) comprising a plurality of diode elements each including the anode groove (22) having the anode region (14) and the anode electrode (24) and the cathode groove (21) having the cathode region (13) and the cathode electrode (23), wherein the anode and cathodes grooves (21 and 22), and the anode electrode (24) and the cathode electrode (23) are interdigitated (Coe, Figs. 1-2, Col. 12, lines 3-19), to increase voltage and current handling capabilities.
Further, Alter teaches forming an array of power devices (Alter, Figs. 2A-2B, ¶0005 ¶0012-¶0016, ¶0024-¶0031) including anode/cathode pairs of the diodes to form an integrated circuit including chip-scale packaging (CSP), wherein at least one conductive material bus electrically interconnects a plurality of active elements, to provide CSP package with improved power interconnect efficiency (PIE) characteristic by reducing ON resistance (Ron) (Alter, Figs. 2A-2B, ¶0024-¶0025), and to reduce the footprint of package for a given PIE value.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the method of Lin by forming a PN power diode device as a macro-cell comprising a plurality of interdigitated anode trenches and cathode trenches as taught by Coe, wherein a plurality of PN power diode devices as a plurality of macro-cells are integrated using chip-scale packaging technology as taught by Alter to have the method, further comprising: forming a macro-cell that includes a plurality of the at least one PN diode power devices; and forming a plurality of the macro-cells for the semiconductor structure connected together to operate as a single PN diode power device, in order to provide a power diode device with increased voltage and current handling capabilities; and to provide CSP package with improved power interconnect efficiency (PIE) characteristic by reducing ON resistance (Ron), and to reduce the footprint of package for a given PIE value (Coe, Col. 2, lines 21-61; Col. 12, lines 3-19; Alter, ¶0005, ¶0012, ¶0024-¶0025).
Claim 6 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over US 2010/0187577 to Lin in view of Alter (US 2004/0245631).
Regarding claim 6, Lin discloses the method of claim 1. Further, Lin does not specifically disclose the method, further comprising: forming a plurality of like PN diode power devices for the at least one PN diode power device; wherein: the plurality of like PN diode power devices are connected together through a bus structure to operate as a single PN diode power device; the method is part of a chip-scale assembly; and the chip-scale assembly comprises a redistribution layer coupling the bus structure to anode and cathode external contacts.
However, Alter teaches forming an array of power devices (Alter, Figs. 2A-2B, ¶0005 ¶0012-¶0016, ¶0024-¶0031) including anode/cathode pairs of the diodes to form an integrated circuit including chip-scale packaging (CSP), wherein: the plurality of power devices (203) are connected together through a bus structure (e.g., metal trace 212S/212D) (Alter, Figs. 2A-2B, ¶0026) to operate as a single power device; the method is part of a chip-scale assembly (e.g., CSP packaging); and the chip-scale assembly (CSP) comprises a redistribution layer (e.g., meal beam 109 for pad to bump redistribution) (Alter, Figs. 2A-2B, ¶0027) coupling the bus structure (e.g., metal trace 212S/212D) to external contacts (e.g., bump 107 for external connection), to provide CSP package with improved power interconnect efficiency (PIE) characteristic by reducing ON resistance (Ron) (Alter, Figs. 2A-2B, ¶0024-¶0025), and to reduce the footprint of package for a given PIE value.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the method of Lin by forming an array of power devices comprising a plurality of anode/cathode pairs as a plurality of like PN diode devices as taught by Alter, wherein a plurality of like PN power diode devices are integrated using chip-scale packaging technology as taught by Alter to have the method, forming a plurality of like PN diode power devices for the at least one PN diode power device; wherein: the plurality of like PN diode power devices are connected together through a bus structure to operate as a single PN diode power device; the method is part of a chip-scale assembly; and the chip-scale assembly comprises a redistribution layer coupling the bus structure to anode and cathode external contacts, in order to provide CSP package with improved power interconnect efficiency (PIE) characteristic by reducing ON resistance (Ron), and to reduce the footprint of package for a given PIE value (Alter, ¶0005, ¶0012, ¶0024-¶0025).
Claims 7-8 and 11 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over US 2010/0187577 to Lin in view of Weyers et al. (US 2013/0153916, hereinafter Weyers).
With respect to Claim 7, Lin discloses a method of forming a PN diode power device (e.g., a method of forming a diode device 20 comprising at least one PN junction formed between the buried region and the active region) (Lin, Fig. 1, ¶0012-¶0026), comprising:
forming an active region (e.g., N-type layer 26/48 on the P-type substrate 21) (Lin, Fig. 1, ¶0013, ¶0026);
forming a buried well (e.g., P-type buried region 38) (Lin, Fig. 1, ¶0013, ¶0026) in the active region (26/48), the buried well (38) having a first conductivity type (e.g., P-type);
forming an anode terminal (241-243/302/312) (Lin, Fig. 1, ¶0013-¶0014, ¶0026), the anode terminal making electrical contact (e.g., through the P-type anode region 42 and the P-type region 36) with the buried well (38);
forming a cathode region (e.g., N-type region 29/26 connected to the cathode terminal 244 through the N+ type cathode contact region 28) (Lin, Fig. 1, ¶0013, ¶0026) in the active region (26/48) proximate an upper surface (22) of the active region (26/48), the cathode region (29/26) having a second conductivity type (e.g., N-type);
forming a cathode terminal (244/301/311) (Lin, Fig. 1, ¶0013-¶0014, ¶0026) electrically connected (e.g., through the N+ type cathode contact region 28) to the cathode region (29/28/26); and
forming an anode region (e.g., P-type region 36 over the P-type buried region 38 and connected to the anode terminal 241 through the anode contact region P+ type region 42) (Lin, Fig. 1, ¶0013, ¶0026) in the active region (26) proximate the upper surface (22) of the active region (26/48), wherein the anode region (36/42) has the first conductivity type (e.g., P-type), the anode region (36/42) is formed over the buried well (38) under the anode terminal (241-243/302/312), and the anode terminal is electrically connected to the anode region (36/42);
wherein:
the buried well (38) has a first end (e.g., under the P-type region 42) below the anode terminal (241) and a second end (e.g., 382/383/384) that extends partially below the cathode region (e.g., N-type regions 29/28/26), the second end being laterally spaced from the cathode terminal (244/301/311);
the anode region (36/42) forms a PN junction of the PN diode power device with the cathode region (26); and
the buried well (38) is configured, in conjunction with the cathode region (29/28/26), to form a clamping diode (e.g., electrical potential near junction 50 formed by conductor portions 242 on the upper surface 22 of the active region 26 is clamped between the cathode region 29/28 and the anode region 36/42, to clamp leakage current and to obtain higher breakdown voltage) (Lin, Fig. 1, ¶0017-¶0018) operative to position a breakdown avalanche region (e.g., a lateral location 382/383/384 of the buried region 38 is placed to control the breakdown voltage, generally less than the breakdown voltage of the junction 58) between the buried well (38) and the cathode terminal (244/301/311), a breakdown voltage of the PN diode power device being a function of one or more characteristics of the buried well (e.g., a lateral location 382/383/384 of the buried region 38).
Further, Lin does not specifically disclose that the anode region is formed between the anode terminal and the cathode region.
However, Weyers teaches forming a PN diode device (Weyers, Fig. 6, ¶0002-¶0003, ¶0028, ¶0034, ¶0047, ¶0065-¶0067) comprising an anode region (606) in a trench (604) having a specific shape such that the anode region (606a) is formed between the anode terminal (608) and the cathode region (602), to increase current- carrying area and to improve current capability and voltage clamping capability of the diode.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the method of Lin by forming the anode in the trench having a specific shape as taught by Weyers to have the method, wherein the anode region is formed between the anode terminal and the cathode region, in order to provide improved PN diode with increased current- carrying area, and improved current capability and voltage clamping capability (Weyers, ¶0002-¶0003, ¶0028, ¶0034, ¶0047, ¶0067).
Regarding claim 8, Lin in view of Weyers discloses the method of claim 7. Further, Lin discloses the method, further comprising: forming a gate structure (e.g., P-type region 40 of the JEFT 56) (Lin, Fig. 1, ¶0017-¶0018) above the active region (26) proximate the upper surface (22) of the active region; and electrically connecting the gate structure (40) to the anode terminal (241-243/302/312); wherein: the gate structure (40) overlaps the PN junction (e.g., the end of the P-type buried region 38 at the location 382 form a PN junction with the N -type active region 26); and the gate structure (40) is configured to control an electric field distribution (e.g., electrical potential near junction 50 formed by conductor portions 242 on the upper surface 22 of the active region 26 is clamped) proximate the PN junction.
Regarding claim 11, Lin in view of Weyers discloses the method of claim 7. Further, Lin discloses the method, further comprising: forming a highly doped implant region (e.g., N+ type contact region 28) (Lin, Fig. 1, ¶0014, ¶0026) of the second conductivity type in the cathode region (e.g., N-type region 29/26); wherein: the highly doped implant region (28) makes electrical contact with the cathode terminal (244/301/311); and the highly doped implant region (28) is laterally spaced from the PN junction (e.g., a junction between the end 382 of the buried region 38 and the N-type region 26).
Claims 9 and 10 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over US 2010/0187577 to Lin in view of Weyers (US 2013/0153916) as applied to claim 8, and further in view of Kocon (US 2011/0303976).
Regarding claim 9, Lin in view of Weyers discloses the method of claim 8. Further, Lin does not specifically disclose the method, wherein: the gate structure is disposed over a portion of the anode region; the anode terminal is laterally spaced from the gate structure; and the anode region has a first end disposed proximate the anode terminal and a second end disposed underneath the gate structure at the PN junction.
However, Kocon teaches forming a diode structure (Kocon, Fig. 7, ¶0006, ¶0021), wherein: the gate structure (7008) is disposed over a portion of the anode region (7002); the anode terminal (7028) is laterally spaced from the gate structure (7008); and the anode region (7002) has a first end disposed proximate the anode terminal (7028) and a second end disposed underneath the gate structure (7008), to provide power diode with reduced operating power for high frequency and high voltage applications (Kocon, ¶0021).
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the method of Lin/Weyers by forming a gate structure overlying a portion of the anode region as taught by Kocon, wherein the PN junction is formed between the anode region and the cathode region to have the method, wherein: the gate structure is disposed over a portion of the anode region; the anode terminal is laterally spaced from the gate structure; and the anode region has a first end disposed proximate the anode terminal and a second end disposed underneath the gate structure at the PN junction, in order to provide power diode with reduced operating power for high frequency and high voltage applications (Kocon, ¶0006, ¶0021).
Regarding claim 10, Lin in view of Weyers discloses the method of claim 8. Further, Lin does not specifically disclose the method, further comprising: forming a shielding structure proximate the upper surface of the active region between the gate structure and the cathode terminal, wherein the shielding structure comprises a field plate configured to control an electric field distribution along a top oxide interface away from an edge of the gate structure nearest the cathode terminal.
However, Kocon teaches forming a diode structure (Kocon, Fig. 7, ¶0006, ¶0021) comprising a shielding structure (7018) proximate the upper surface of the active region (7006) between the gate structure (7008) and the cathode terminal (7012), wherein the shielding structure (7018) comprises a field plate (e.g., above the drift region7014) configured to control an electric field distribution along a top oxide interface away from an edge of the gate structure (7008) nearest the cathode terminal (7012), to control an electric field across the drift region underlying the shielding structure to reduce operating power for high frequency and high voltage applications (Kocon, ¶0021).
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the method of Lin/Weyers by forming a shielding structure overlying a portion of the drift region between the gate and the cathode as taught by Kocon to have the method, further comprising: forming a shielding structure proximate the upper surface of the active region between the gate structure and the cathode terminal, wherein the shielding structure comprises a field plate configured to control an electric field distribution along a top oxide interface away from an edge of the gate structure nearest the cathode terminal, in order to control an electric field across the drift region underlying the shielding structure to reduce operating power for high frequency and high voltage applications (Kocon, ¶0006, ¶0021).
Claims 12 and 13 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over US 2010/0187577 to Lin in view of Weyers (US 2013/0153916) as applied to claim 7, and further in view of Coe (US Patent No. 4,754,310).
Regarding claim 12, Lin in view of Weyers discloses the method of claim 7. Further, Lin does not specifically disclose the method, further comprising: forming an anode trench in the active region, wherein the anode terminal is disposed at least in part in the anode trench and electrically connected to the buried well and the anode region in the anode trench.
However, Coe teaches forming a PN diode device (Coe, Fig. 1, Col. 2, lines 21-61; Col. 7, lines 27-67; Col. 8, lines 148; Col. 11, lines 31-67; Col. 12, lines 1-8) comprising a P -type anode region (14) in an anode trench (22), wherein the anode terminal (24) is disposed at least in part in the anode trench (22) and electrically connected to the buried well (e.g., bottom P-type layer 12) and the anode region (14) in the anode trench (22), wherein the P- type anode region (14) forms PN junction (5) with the body region (3) including N-type regions (11), to provide a diode device with controlled breakdown voltage to increase voltage and current handling capabilities of the device.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the method of Lin/Weyers by forming an anode trench including P-type anode region and the anode electrode in the anode trench as taught by Coe, wherein the anode terminal in the anode trench electrically connected to the buried P-type well to have the method, further comprising: forming an anode trench in the active region, wherein the anode terminal is disposed at least in part in the anode trench and electrically connected to the buried well and the anode region in the anode trench, in order to provide a diode device with controlled breakdown voltage to increase voltage and current handling capabilities of the device (Coe, Col. 2, lines 21-61; Col. 7, lines 27-61; Col. 11, lines 31-40; Col. 12, lines 3-8).
Regarding claim 13, Lin in view of Weyers and Coe discloses the method of claim 12. Further, Lin discloses the method, further comprising: electrically connecting the anode electrode (312/302) to the buried well (38) and the anode region (36/42) with a conductive layer (241-243) (Lin, Fig. 1, ¶0013-¶0014) including silicide or other high work function conductors to form Schottky contacts and ohmic contacts to provide low resistance path between the anode and the cathode, but does not specifically disclose the method, further comprising: electrically connecting the anode trench to the buried well and the anode region with a conductive layer disposed along the anode trench.
Further, Coe teaches forming the electrode layer (24) in the anode trench (22), and electrically connecting the anode trench (22) to the buried well (12) and the anode region (14) with the electrode layer (24) disposed along the anode trench (22), to provide a diode device with controlled breakdown voltage to increase voltage and current handling capabilities of the device.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the method of Lin/Weyers/Coe by forming the electrode layer in the anode trench as taught by Coe, wherein a conductive layer including silicide or other high work function conductors is formed between the anode electrode and the anode region as taught by Lin to have the method, further comprising: electrically connecting the anode trench to the buried well and the anode region with a conductive layer disposed along the anode trench, in order to provide a diode device with controlled breakdown voltage to increase voltage and current handling capabilities of the device; and to provide silicide layer to form low resistance path between the anode and the cathode (Coe, Col. 2, lines 21-61; Col. 7, lines 27-61; Col. 11, lines 31-40; Col. 12, lines 3-8; Lin, ¶0013-¶0014).
Claim 14 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over US 2010/0187577 to Lin in view of Weyers (US 2013/0153916) as applied to claim 7, and further in view of Terashima (US 2006/0043417).
Regarding claim 14, Lin in view of Weyers discloses the method of claim 7. Further, Lin does not specifically disclose the method, wherein: the buried well has a higher doping concentration than that of the anode region.
However, Terashima teaches forming a diode device (Terashima, Fig. 1, ¶0006-¶0007, ¶0025-¶0035) comprising a P+ type buried well (4) (Terashima, Fig. 1, ¶0025) having a higher doping concentration than that of the P- type anode region (5) (Terashima, Fig. 1, ¶0028) connected to the P+ type buried well (4) and the anode electrode (8), to relieve the electric field concentration near the upper surface of the active semiconductor layer, and to provide a semiconductor diode device with increased breakdown voltage (Terashima, ¶0006, ¶0025, ¶0035).
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the method of Lin/Weyers by forming the buried well of P+ type as taught by Terashima to have the method, wherein: the buried well has a higher doping concentration than that of the anode region, in order to relieve the electric field concentration near the upper surface of the active semiconductor layer, and to provide a semiconductor diode device with increased breakdown voltage (Terashima, ¶0006, ¶0025, ¶0035).
Response to Arguments
Applicant's arguments filed 02/19/2026 have been fully considered but they are not persuasive.
In response to Applicant’s argument regarding 112(b) rejection of claim 6 that “[p]resent disclosure (paragraph 0178) discloses (emphasis added): individual source, drain and gate busses can be connected to multiple source, drain and gate terminals, of multiple like or identical devices, thereby allowing those multiple devices to operate as a single macro-cell device. Multiple macro-cell devices can then be connected together to operate as one power device. This portion of the present disclosure provides the support for the elements in question in claim 6”, the examiner submits that the above assertion does not provide a clear definition for the limitations “a plurality of like PN diode power devices”. The specification does not resolve ambiguity of the claim, and that renders the claim indefinite. Thus, the above Applicant’s argument is not persuasive, and the rejection of claim 6 under 35 USC 112(b) is maintained.
In response to Applicant’s argument that “[t]he "lower surface" of the active region (26/48) in Fig. 1 is the interface or line between the bottom of the N type buried layer region 48 and the top of the semiconductor (SC) substrate 21. The buried well 38, on the other hand, is not proximate this surface but is separated by a substantial portion (thickness 49) of the N type buried layer region 48 from this surface. Therefore, Lin does not disclose "[a] buried well [that] is formed proximate a lower surface of [an] active region"”, the examiner submits that the term “proximate” is interpreted as “close to”, and it does not require a direct contact between “a lower surface of the active region” and “the buried well”. Thus, the above Applicant’s argument is not persuasive, and the limitations “the buried well is formed proximate a lower surface of the active region” are disclosed by Lin.
In response to Applicant’s argument that “[L]in does not disclose "[a] buried well [that] ... extends ... to a location proximate [a] cathode region", the examiner submits that the term “proximate” is interpreted as “close to”. In Lin, the buried well has a lateral location (e.g., 383/384) that is close to the cathode region (e.g., 28/29). Thus, the above Applicant’s argument is not persuasive, and the limitations “the buried well… extends…to a location proximate the cathode region” are disclosed by Lin.
In response to Applicant’s argument that “[t]he device of Lin is a Schottky diode 20. A Schottky diode operates with a metal-semiconductor junction rather than a PN junction… Lin does not disclose "[an] anode region [that] ... extends along [an] upper surface of [an] active region ... to [a] cathode region to form a PN junction of [a] PN diode power device with the cathode region”, the examiner submits that the Schottky diode of Lin comprises a PN junction formed between the end of the P-type buried region 38 at the location (e.g., 383/384) and the N -type active region 26/29 at the cathode region. Further, the original specification discloses (e.g., paragraph [0086]) that the Schottky diode is a modification of PN diode, wherein the P-type body is excluded. However, claim language does not exclude forming PN diode power device as a Schottky diode having the anode region connected to the buried well.
Further, claim 1 does not recite a distinct feature including a gate structure formed above the upper surface of the semiconductor structure, electrically isolated from the active region, and electrically connected with the buried well, to overcome the prior art by Lin including a Schottky diode.
Thus, the above Applicant’s arguments are not persuasive, and the rejection of claim 1 under 35 USC 102 to Lin is maintained.
In response to Applicant’s argument regarding claim 7 that in Lin “[o]nly the cathode contact (28) is disclosed as the cathode, whereas the N type regions 26 and 29 are not disclosed as part of the cathode”, the examiner submits that Lin discloses (paragraph [0014]) that “N type regions 29 of slightly higher doping than N type regions 26 may be provided below N+ regions 28 to reduce the ON-resistance”. Thus, the region (29) under region (28) is interpreted as a cathode region.
Thus, the above Applicant’s argument is not persuasive, and the rejection of claim 7 under 35 USC 103 over Lin is maintained.
Regarding dependent claims 2-6 and 8-14 which depend on the independent claims 1 and 7, the examiner respectfully submits that the applicant’s arguments with respect to dependent claims are not persuasive for the above reasons, thus, the rejections of the dependent claims are sustained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891