DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, including claims 1-18 in the reply filed on 02/09/2026 is acknowledged.
Claim 20 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/09/2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation of “the substrate feature is an interconnect’ must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Allowable Subject Matter
Claims 2, 3, 4, 7, 9, 10, and 16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and the above claim objection overcomes.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein at least a portion of the plurality of crystals is at a distance of less than or equal to about 100 micrometers from the substrate feature, wherein the substrate feature is an interconnect”, as recited in claim 2.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein at least a portion of the plurality of crystals is at a distance of less than or equal to about 100 micrometers from an edge of the semiconductor structure”, as recited in claim 3.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein the layer of material comprises a keyhole, and wherein the keyhole is disposed within the layer of material at a distance of less than or equal to about 100 micrometers from the substrate feature”, as recited in claim 4.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein at least a portion of the plurality of crystals is at a distance of less than or equal to about 100 micrometers from the interface”, as recited in claim 7.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein at least a portion of the plurality of crystals forms a surface adjacent to the substrate feature having a surface roughness from about 20 nanometers to about 10 microns”, as recited in claim 9.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein the at least one device is at a distance less than or equal to about 100 micrometers from the substrate feature”, as recited in claim 16.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, 13, 15, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maeda et al. (U.S. 2019/0088673 A1, hereinafter refer to Maeda).
Regarding Claim 1: Maeda discloses a semiconductor structure (see Maeda, Figs.5 and 8 as shown below and ¶ [0002]) comprising:
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a layered structure (101/141) comprising a semiconductor material (see Maeda, Figs.5 and 8 as shown above and ¶ [0057]);
a layer of material (102) on the layered structure (101/141) (see Maeda, Figs.5 and 8 as shown above); and
a substrate feature (163) extending into at least a portion of the layer of material (102) (see Maeda, Figs.5 and 8 as shown above),
wherein a region of the layer of material (102) in proximity to the substrate feature (163) comprises a plurality of crystals (151) having an average grain (note: the arrangements of atoms forms a grains) size or an average grain density that is different from another region of the layer of material (102) that is further away from the substrate feature (163) than the region (see Maeda, Figs.5 and 8 as shown above and ¶ [0071]- ¶ [0073]).
Regarding Claim 6: Maeda discloses a semiconductor structure as set forth in claim 1 as above. Maeda further teaches wherein a region of the layer of material (102) in proximity to an interface between the layer of material (102) and the layered structure (101/141) comprises a plurality of crystals (151) having an average grain size or an average grain density that is different from another region of the layer of material (102) that is further away from the interface (see Maeda, Figs.5 and 8 as shown above).
Regarding Claim 13: Maeda discloses a semiconductor structure as set forth in claim 1 as above. Maeda further teaches wherein the substrate feature is a die street, a via, or a trench (see Maeda, Figs.5 and 8 as shown above).
Regarding Claim 15: Maeda discloses a semiconductor structure as set forth in claim 1 as above. Maeda further teaches wherein at least one device on the layered structure (101/141) or the layer of material (102) (see Maeda, Figs.5 and 8 as shown above).
Regarding Claim 18: Maeda discloses a semiconductor structure as set forth in claim 1 as above. Maeda further teaches wherein the substrate feature (163) comprises silicon (123/121) (see Maeda, Figs.5 and 8 as shown above).
Claim(s) 1, 14-15, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hall et al. (U.S. 2007/0295496 A1, hereinafter refer to Hall).
Regarding Claim 1: Hall discloses a semiconductor structure (see Hall, Fig.13 as shown below and ¶ [0002]) comprising:
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a layered structure (12) comprising a semiconductor material (semiconductor device) (see Hall, Fig.13 as shown above and ¶ [0033]);
a layer of material (10) on the layered structure (12) (see Hall, Fig.13 as shown above); and
a substrate feature (note: the edge or the die street of the semiconductor structure is equivalent to the claimed limitation of “substrate feature”) extending into at least a portion of the layer of material (10) (see Hall, Fig.13 as shown above),
wherein a region (22) of the layer of material in proximity to the substrate feature comprises a plurality of crystals having an average grain (particles) size or an average grain (particles) density that is different from another region (20) of the layer of material (10) that is further away from the substrate feature than the region (22) (see Hall, Fig.13 as shown above, ¶ [0011], ¶ [0043], and ¶ [0050]).
Regarding Claim 14: Hall discloses a semiconductor structure as set forth in claim 1 as above. Hall further teaches wherein the substrate feature is at the edge of the semiconductor structure (see Hall, Fig.13 as shown above).
Regarding Claim 15: Hall discloses a semiconductor structure as set forth in claim 1 as above. Hall further teaches wherein at least one device (14) on the layered structure (12) or the layer of material (see Hall, Fig.13 as shown above).
Regarding Claim 17: Hall discloses a semiconductor structure as set forth in claim 1 as above. Hall further teaches wherein the layer of material (10) comprises diamond (see Hall, Fig.13 as shown above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Maeda et al. (U.S. 2019/0088673 A1, hereinafter refer to Maeda).
Regarding Claim 5: Maeda discloses a semiconductor structure as applied to claim 1 above. Maeda is silent upon explicitly disclosing wherein the average grain size of the plurality of crystals increases with distance in a direction away from the substrate feature.
However, the claimed and the Maeda prior art products are identical or substantially identical in structure or composition; hence, a prima facie case of either obviousness has been established for the recited claim limitation of “the average grain size of the plurality of crystals increases with distance in a direction away from the substrate feature”.
In addition, the discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s functioning, does not render the old composition patentably new to the discoverer.
Regarding Claim 8: Maeda discloses a semiconductor structure as applied to claim 6 above. Maeda is silent upon explicitly disclosing wherein the average grain size of the plurality of crystals increases with distance in a direction away from the interface or increases in a direction parallel to a surface of the substrate feature.
However, the claimed and the Maeda prior art products are identical or substantially identical in structure or composition; hence, a prima facie case of either obviousness has been established for the recited claim limitation of “the average grain size of the plurality of crystals increases with distance in a direction away from the interface or increases in a direction parallel to a surface of the substrate feature”.
In addition, the discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s functioning, does not render the old composition patentably new to the discoverer.
Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Maeda et al. (U.S. 2019/0088673 A1, hereinafter refer to Maeda) as applied to claim 1 above, and further in view of Saito et al. (U.S. 2021/0013225 A1, hereinafter refer to Saito).
Regarding Claim 11: Maeda discloses a semiconductor structure as applied to claim 1 above. Maeda is silent upon explicitly disclosing wherein the average grain size is an average crystal grain diameter, and the average crystal grain diameter of the plurality of crystals is from about 10 nanometers to about 2,000 nanometers.
Before effective filing date of the claimed invention the disclosed average crystal grain diameter were known in order to form a channel semiconductor layer of the memory cell, which results in a high operation voltage of the memory cell.
For support see Saito, which teaches wherein the average grain size is an average crystal grain diameter, and the average crystal grain diameter of the plurality of crystals is from about 10 nanometers to about 2,000 nanometers (80 nm or more and 1600 nm or less) (see Saito, Fig.10A, ¶ [0003], ¶ [0030], and ¶ [0042]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Maeda and Saito to enable the average crystal grain diameter of the plurality of crystals of Maeda to be from about 10 nanometers to about 2,000 nanometers (80 nm or more and 1600 nm or less) as taught by Saito in order to form a channel semiconductor layer of the memory cell, which results in a high operation voltage of the memory cell.
Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hall et al. (U.S. 2007/0295496 A1, hereinafter refer to Hall) as applied to claim 1 above, and further in view of Francis et al. (WO 2020/263845 A1, hereinafter refer to Francis).
Regarding Claim 12: Hall discloses a semiconductor structure as applied to claim 1 above. Hall is silent upon explicitly disclosing wherein the semiconductor material is a wide-bandgap semiconductor material.
Before effective filing date of the claimed invention the disclosed wide-bandgap semiconductor material were known as alternative material to silicon semiconductor material in order to obtain an improved performance efficiency in high-power microwave devices, which can exhibit electron mobilities, breakdown voltages, and thermal conductivities.
For support see Francis, which teaches wherein the semiconductor material is a wide-bandgap semiconductor material (see Hall, ¶ [0041]).
Hall discloses the claimed invention except for the material of semiconductor material. Hence, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Hall and Francis to enable the known wide-bandgap semiconductor material for Hall layered structure as taught by Francis in order to obtain an improved performance efficiency in high-power microwave devices, which can exhibit electron mobilities, breakdown voltages, and thermal conductivities, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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/BITEW A DINKE/Primary Examiner, Art Unit 2812