Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 1 and 3-18 are allowed.
The following is an examiner’s statement of reasons for allowance:
In re Claim 1, Bauer et al. (U.S. 2007/0001319 A1, hereinafter refer to Bauer) teaches a semiconductor structure (see Bauer, Figs.2 and 6 and ¶ [0002]) comprising:
a layered structure (3/16) comprising a semiconductor material (see Bauer, Figs.2 and 6);
a layer of material (5/10) on the layered structure (3/16) (see Bauer, Figs.2 and 6); and
a substrate feature (a die street, a via, a trench, or a plastics composition 2) extending into at least a portion of the layer of material (5/10) (see Bauer, Figs.2 and 6),
wherein a region of the layer of material (5) in proximity to the substrate feature (a die street, a via, a trench, or a plastics composition 2) comprises a plurality of crystals having an average grain size or an average grain density that is different from another region of the layer of material (10) that is further away from the substrate feature (a die street, a via, a trench, or a plastics composition 2) than the region, wherein at least a portion of the plurality of crystals is at a distance (D) of less than or equal to about 100 micrometers laterally from the substrate feature, and wherein the substrate feature (a die street, a via, a trench, or a plastics composition 2) is an interconnect (see Bauer, Figs.2 and 6, ¶ [0031], and ¶ [0071]).
The prior arts of record do not anticipate and do not render obvious such limitations of Claim 1 as: "wherein at least a portion of the plurality of crystals is at a distance of less than or equal to about 100 micrometers laterally from the substrate feature, and wherein the substrate feature is an interconnect.”
Claims 3-18 are allowed for the same reasons as claim 1, from which they depend.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21-26, 29, 31-33, and 35-38 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bauer et al. (U.S. 2007/0001319 A1, hereinafter refer to Bauer).
Regarding Claim 21: Bauer discloses a semiconductor structure (see Bauer, Figs.2 and 6 as shown below and ¶ [0002]) comprising:
PNG
media_image1.png
468
718
media_image1.png
Greyscale
PNG
media_image2.png
381
857
media_image2.png
Greyscale
a layered structure (3 and 16) comprising a semiconductor material (see Bauer, Figs.2 and 6 as shown above);
a layer of material (5/10) on the layered structure (3 and 16), wherein the layer of material (5/10) comprises a keyhole (see Bauer, Figs.2 and 6 as shown above); and
a substrate feature (a die street, a via, a trench, or a plastics composition 2) extending into at least a portion of the layer of material (5/10) (see Bauer, Figs.2 and 6 as shown above),
wherein a region (5) of the layer of material (5/10) in proximity to the substrate feature (a die street, a via, a trench, or a plastics composition 2) comprises a plurality of crystals having an average grain size or an average grain density that is different from another region of the layer of material (10) that is further away from the substrate feature (a die street, a via, a trench, or a plastics composition 2) than the region (5), and wherein the keyhole is disposed within the layer of material (5/10) at a distance (D) of less than or equal to about 100 micrometers from the substrate feature (a die street, a via, a trench, or a plastics composition 2) (see Bauer, Figs.2 and 6 as shown above, ¶ [0031], and ¶ [0071]).
Regarding Claim 22: Bauer discloses a semiconductor structure as set forth in claim 21 as above. Bauer further teaches wherein at least a portion of the plurality of crystals is at a distance (D) of less than or equal to about 100 micrometers from an edge of the semiconductor structure (see Bauer, Figs.2 and 6 as shown above, ¶ [0031], and ¶ [0071]).
Regarding Claim 23: Bauer discloses a semiconductor structure as set forth in claim 21 as above. Bauer further teaches wherein the average grain size of the plurality of crystals increases with distance in a direction away from the substrate feature (a die street, a via, or a trench) (see Bauer, Figs.2 and 6 as shown above).
Note: the discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s functioning, does not render the old composition patentably new to the discoverer.
Regarding Claim 24: Bauer discloses a semiconductor structure as set forth in claim 21 as above. Bauer further teaches wherein a region (5) of the layer of material (5/10) in proximity to an interface between the layer of material (5/10) and the layered structure (3 and 16) comprises a plurality of crystals having an average grain size or an average grain density that is different from another region of the layer of material (10) that is further away from the interface (see Bauer, Figs.2 and 6 as shown above and Fig.5).
Regarding Claim 25: Bauer discloses a semiconductor structure as set forth in claim 24 as above. Bauer further teaches wherein at least a portion of the plurality of crystals is at a distance of less than or equal to about 100 micrometers from the interface (see Bauer, Figs.2 and 6 as shown above and Fig.5).
Regarding Claim 26: Bauer discloses a semiconductor structure as set forth in claim 25 as above. Bauer further teaches wherein the average grain size of the plurality of crystals increases with distance in a direction away from the interface or increases in a direction parallel to a surface of the substrate feature (a die street, a via, or a trench) (see Bauer, Figs.2 and 6 as shown above).
Note: the discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s functioning, does not render the old composition patentably new to the discoverer.
Regarding Claim 29: Bauer discloses a semiconductor structure as set forth in claim 21 as above. Bauer further teaches wherein the average grain size is an average crystal grain diameter, and the average crystal grain diameter of the plurality of crystals is from about 10 nanometers to about 2,000 nanometers ( 0.1 nm and 100 nm) (see Bauer, Figs.2 and 6 as shown above and ¶ [0031]).
Regarding Claim 31: Bauer discloses a semiconductor structure as set forth in claim 21 as above. Bauer further teaches wherein the substrate feature is a die street, a via, or a trench (see Bauer, Figs.2 and 6 as shown above).
Regarding Claim 32: Bauer discloses a semiconductor structure as set forth in claim 21 as above. Bauer further teaches wherein the substrate feature is at the edge of the semiconductor structure (see Bauer, Figs.2 and 6 as shown above).
Regarding Claim 33: Bauer discloses a semiconductor structure as set forth in claim 21 as above. Bauer further teaches wherein at least one device (18/3) on the layered structure (16/3) or the layer of material (5/10) (see Bauer, Figs.2 and 6 as shown above).
Regarding Claim 35: Bauer discloses a semiconductor structure as set forth in claim 21 as above. Bauer further teaches wherein the layer of material (5/10) comprises diamond (note: metal oxide such as MOx, VOx, WOx, etc and carbides and carbonitrides considered as a diamond base metal oxide materials) (see Bauer, Figs.2 and 6 as shown above and ¶ [0034]- ¶ [0035]).
Regarding Claim 36: Bauer discloses a semiconductor structure as set forth in claim 21 as above. Bauer further teaches wherein the substrate feature (2) comprises silicon (plastics composition) (see Bauer, Figs.2 and 6 as shown above).
Regarding Claim 37: Bauer discloses a semiconductor structure (see Bauer, Figs.2 and 6 as shown above and ¶ [0002]) comprising:
a layered structure (16/3) comprising a semiconductor material (see Bauer, Figs.2 and 6 as shown above);
a layer of material (5/10) on the layered structure (3/16) (see Bauer, Figs.2 and 6 as shown above); and
a substrate feature (a die street, a via, a trench, or a plastics composition 2) extending into at least a portion of the layer of material (5/10) (see Bauer, Figs.2 and 6 as shown above),
wherein a region (5) of the layer of material in proximity to the substrate feature (a die street, a via, a trench, or a plastics composition 2) comprises a plurality of crystals having an average grain size or an average grain density that is different from another region of the layer of material (10) that is further away from the substrate feature (a die street, a via, a trench, or a plastics composition 2) than the region (5), wherein at least a portion of the plurality of crystals is at a distance (D) of less than or equal to about 100 micrometers laterally from an edge of the semiconductor structure (see Bauer, Figs.2 and 6 as shown above, ¶ [0031], and ¶ [0071]).
Regarding Claim 38: Bauer discloses a semiconductor structure (see Bauer, Figs.2 and 6 as shown above and ¶ [0002]) comprising:
a layered structure (3/16) comprising a semiconductor material (see Bauer, Figs.2 and 6 as shown above);
a layer of material (5/10) on the layered structure (3/16) (see Bauer, Figs.2 and 6 as shown above);
a substrate feature (a die street, a via, a trench, or a plastics composition 2) extending into at least a portion of the layer of material (5/10) (see Bauer, Figs.2 and 6 as shown above); and
at least one device (18) on the layered structure (3/16) or the layer of material (5/10) at a distance (D) less than or equal to about 100 micrometers from the substrate feature (a die street, a via, a trench, or a plastics composition 2) (see Bauer, Figs.2 and 6 as shown above, ¶ [0031], and ¶ [0071]),
wherein a region (5) of the layer of material (5/10) in proximity to the substrate feature (a die street, a via, a trench, or a plastics composition 2) comprises a plurality of crystals having an average grain size or an average grain density that is different from another region of the layer of material (10) that is further away from the substrate feature (a die street, a via, a trench, or a plastics composition 2) than the region (5) (see Bauer, Figs.2 and 6 as shown above, ¶ [0031], and ¶ [0071]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 27-28 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Bauer et al. (U.S. 2007/0001319 A1, hereinafter refer to Bauer).
Regarding Claim 27: Bauer discloses a semiconductor structure as applied to claim 25 above. Bauer is silent upon explicitly disclosing wherein at least a portion of the plurality of crystals forms a surface adjacent to the substrate feature having a surface roughness from about 20 nanometers to about 10 microns.
However, Bauer teaches wherein at least a portion of the plurality of crystals forms a surface adjacent to the substrate feature (a die street, a via, a trench, or a plastics composition 2) having a surface roughness (see Bauer, Figs.2 and 6 as shown above).
Hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the ranges of surface roughness through routine experimentation and optimization to obtain optimal or desired adhesion because the ranges of surface roughness is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Regarding Claim 28: Bauer discloses a semiconductor structure as set forth in claim 27 as above. Bauer further teaches wherein at least a portion of the surface comprises a plurality of voids in the material wherein a diameter of the plurality of voids varies in proportion with the average grain size of the material (see Bauer, Figs.2 and 6 as shown above).
Regarding Claim 34: Bauer discloses a semiconductor structure as applied to claim 33 above. Bauer is silent upon explicitly disclosing wherein the at least one device is at a distance less than or equal to about 100 micrometers from the substrate feature.
However, Bauer teaches wherein the at least one device (18) is at a distance from the substrate feature (a die street, a via, a trench, or a plastics composition 2) (see Bauer, Figs.2 and 6 as shown above).
Hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the distance of the at least one device from the substrate feature desired adhesion because the distance of the at least one device from the substrate feature is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Claim(s) 30 is rejected under 35 U.S.C. 103 as being unpatentable over Bauer et al. (U.S. 2007/0001319 A1, hereinafter refer to Bauer) as applied to claim 21 above and further in view of Francis et al. (WO 2020/263845 A1, hereinafter refer to Francis).
Regarding Claim 30: Bauer discloses a semiconductor structure as applied to claim 21 above. Bauer is silent upon explicitly disclosing wherein the semiconductor material is a wide-bandgap semiconductor material.
For support see Francis, which teaches wherein the semiconductor material is a wide-bandgap semiconductor material (see Hall, ¶ [0041]).
Bauer discloses the claimed invention except for the material of semiconductor material. Hence, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Bauer and Francis to enable the known wide-bandgap semiconductor material for Bauer layered structure as taught by Francis in order to obtain an improved performance efficiency in high-power microwave devices, which can exhibit electron mobilities, breakdown voltages, and thermal conductivities, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BITEW A DINKE/Primary Examiner, Art Unit 2812
Prosecution Insights