Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Receipt is acknowledged of the applicant’s amendment filed April 8, 2026. The applicant has addressed all objections to the specification and claims raised in the previous office action.
Response to Arguments
Applicant’s arguments, see pp. 8-10, filed April 8, 2026, with respect to the rejection of claim 8 under Chen et. al., Pub. No. US 2022/0102518, hereafter referred to as Chen, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection of claim 1, which has been amended to incorporate the limitations recited by the original claim 8, is made in view of Ueda et. al., Pub. No. US 2013/0288445, hereafter referred to as Ueda.
Regarding claim rejections under 35 U.S.C. 102 and 103, the applicant pointed out that the grooves in the gate electrode 108 (Chen Figs. 9A-9C) do not extend from the bottom of the gate to the top of the gate, as the examiner had originally believed. As a result, the examiner concedes that the rejection of claim 8 under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Chen was improper, and is thus withdrawn. However, in light of the applicant’s amendments to the claims, the original rejections as a whole are rendered moot, and have necessitated the new grounds of rejection detailed below.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 13 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention.
Claim 13 recites the limitation, “wherein the substrate is exposed by the plurality of grooves.” The claim depends on claim 11, which recites the limitation, “further comprising an etching stop layer disposed on sidewalls of the gate.” However, the original disclosure does not describe an embodiment of the invention that simultaneously has an etching stop layer disposed on the sidewalls of the gate and has the substrate exposed between the grooves. Therefore, there is no support for this combination of limitations in the original disclosure, and thus it constitutes new matter.
It will be assumed for examination purposes that the substrate is exposed by the grooves, regardless of whether or not an etching stop layer is present; equivalently, it will be assumed that the claim was meant to depend directly on claim 1.
This rejection may be overcome by amending claim 13 to instead depend directly on claim 1, as claim 13, thus amended, would have support in the original disclosure.
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Figs. 1A and 1B of Ueda, reproduced with annotations added by the examiner.
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Figs. 2A and 2B of Ueda, reproduced with annotations added by the examiner.
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Figs. 4A and 4B of Ueda, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 9, and 11 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Ueda.
Regarding claim 1, Ueda teaches all the limitations in Figs. 1A-B, 2A-B, and 4B, reproduced above with annotations added by the examiner: “A transistor structure” (Figs. 1A-B, 2A-B, and 4B), “comprising: a gate” ([0060]; Figs. 1A-B, 2A-B, and 4B, gate electrode 122), “disposed on a substrate” ([0054]; Figs. 1A-B, 2A-B, and 4B, substrate 102); “a gate dielectric layer” ([0064]; Figs. 1A-B, 2A-B, and 4B, gate insulating film 120), “disposed between the gate and the substrate” (Figs. 1A-B, 2A-B, and 4B; note the relative positions of the gate insulating film 120 and the substrate 102); “and a source region” ([0062]; Fig. 4B, source region 112) “and a drain region” ([0062]; Fig. 4B, drain region 113), “respectively disposed at two opposite sides of the gate” (Fig. 4B; note the relative placements of the source region 112, the drain region 113, and the gate electrode 122), “wherein, from a top view above the substrate, the gate has two opposite edges in a first direction” (Fig. 4B, first direction, marked by the examiner) “intersecting a second direction where a channel length of the transistor structure is located” (Fig. 4B, second direction, marked by the examiner), “and each of the two opposite edges has a non-linear shape” (Fig. 4B; note that the edges parallel to the second direction are not continuous lines), “wherein each of sidewalls of the gate in the first direction has a plurality of grooves” (Fig. 1B; note the gaps between fingers of the gate electrode 122)), “and each groove is extended from a bottom of the gate to a top of the gate” (Fig. 1B; note that the gaps between fingers of the gate electrode 122 extend all the way from the bottom to the top).
Regarding claim 2, Ueda further teaches “The transistor structure of claim 1, wherein, from the top view above the substrate” (Fig. 4B), “each of the two opposite edges has a plurality of protrusions” (Fig. 4B; note the extensions of the gate electrode 122 on each of the opposite edges).
Regarding claim 3, Ueda further teaches “The transistor structure of claim 2, wherein, from the top view above the substrate, a profile of the protrusion is a rectangle” (Fig. 4B; note the rectangular shape of the protrusions).
Regarding claim 9, Ueda further teaches “The transistor structure of claim 1, wherein a material of the gate comprises polysilicon” ([0082]: “Here, the conductive film to be the gate electrode 122, for example, may be composed of polysilicon.”).
Regarding claim 11, Ueda further teaches “The transistor structure of claim 1, further comprising an etching stop layer” ([0084]; Figs. 1A-B, 2A-B, side wall 124; also see [0085]: “The side wall 124 can be configured by an insulating film such as an oxide film or a nitride film.”) “disposed on sidewalls of the gate” (Figs. 1A-B and 2A-B; note that the “side walls”, as they are referred to in Ueda, are disposed along sidewalls of the gate). Note that “etching stop layer” is interpreted here to include any insulating layer that can serve the purpose of an etching stop layer.
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Fig. 20 of Pogrebnyak, reproduced with annotations added by the examiner.
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Fig. 21 of Pogrebnyak, reproduced with annotations added by the examiner.
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Fig. 1A of Beach, reproduced with annotations added by the examiner.
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Fig. 2B of Beach, reproduced with annotations added by the examiner.
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Figs. 7A and 7B of Takagi, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Ueda in view of Pogrebnyak et. al., Pub. No. US 2020/0127130, hereafter referred to as Pogrebnyak.
[Beach et. al. (Pub. No.: US 2006/0081985 A1), hereafter referred to as Beach, is utilized herein as further evidence.]
Regarding claim 4, Ueda teaches “The transistor structure of claim 2”, but does not teach “wherein, from the top view above the substrate, the corners of the protrusion are rounded.”
Pogrebnyak, however, does teach “wherein, from the top view above the substrate, the corners of the protrusion are rounded” (Pogrebnyak, [0036]; Fig. 20, reproduced above with annotations added by the examiner, gate arms 80 and 82), but teaches a split gate (Pogrebnyak [0041]; Fig. 20, gate arms 80 and 82) with no dielectric deposed between the gate and the substrate (Pogrebnyak [0068]).
The rounded protrusions of Pogrebnyak can be incorporated as rounded protrusions on the edges of the gate in Ueda in place of the rectangular protrusions.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to modify the edges of the gate in Ueda with the rounded protrusions of Pogrebnyak because the gate with rounded protrusions will still properly function as a gate and the required modification to the apparatus of Ueda is a simple substitution of rounded protrusions for the rectangular protrusions with a predictable outcome (also see evidentiary reference Beach, Figs. 1A and 2B, showing two different interchangeable gate designs with the same structure, except that one has rectangular fingers and the other rounded fingers).
[Takagi (Pub. No. US 2017/0062576 A1), hereafter referred to as Takagi, is utilized herein as further evidence.]
Regarding claim 5, Ueda teaches “the transistor structure of claim 2”, but does not teach “wherein, from the top view above the substrate, the non-linear shape comprises a wave shape.”
Pogrebnyak, however, does teach “wherein, from the top view above the substrate, the non-linear shape comprises a wave shape” (Pogrebnyak [0044]: “The first gate 440… has arms with sinusoidal profiles”; Fig. 21, reproduced above with annotations added by the examiner, gate arms 442 and 444, inner boundaries 443 and 445), but teaches a split gate (Pogrebnyak [0044]; Fig. 21, gate arms 442 and 444) with no dielectric deposed between the gate and the substrate (Pogrebnyak [0068]).
The wavy edge profile of Pogrebnyak can be incorporated as wavy edge profiles on the edges of the gate in Ueda in place of the rectangular protrusions.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to modify the edges of the gate in Ueda with the wavy edges of Pogrebnyak because the gate with wavy edges will still properly function as a gate and the required modification to the apparatus of Ueda is a simple substitution of wavy edges for the edges with rectangular protrusions with a predictable outcome (also see evidentiary reference Takagi, Figs.7A and 7B, showing a transistor structure with wavy gates).
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Figs. 9A-C of Chen, reproduced above with annotations added by the examiner.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Ueda and Pogrebnyak, in further view of Chen et. al., Pub. No. US 2022/0102518, hereafter referred to as Chen.
Regarding claim 6, Ueda teaches “The transistor structure of claim 2”, but does not teach “wherein, from the top view above the substrate, a ratio of a protruding length of the protrusion from the edge to a distance between two adjacent protrusions is between 0.5 and 1.”
Pogrebnyak discloses a distance between protrusions of 175 nm (Pogrebnyak [0036]).
The 175 nm distance between protrusions disclosed by Pogrebnyak can be incorporated into the gate of Ueda as a 175 nm distance between the protrusions.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use 175 nm as the distance between two protrusions on the gate of Ueda because it would require only a simple substitution of protrusions with a distance of 175 nm between them with a predictable outcome.
However, the combination of Ueda and Pogrebnyak just described does not teach “wherein, from the top view above the substrate, a ratio of a protruding length of the protrusion from the edge to a distance between two adjacent protrusions is between 0.5 and 1.”
Chen, on the other hand, teaches a gate with grooves, as well as length ranges (Chen [0028-0029]; Figs. 9A-C, reproduced above with annotations added by the examiner) that allow for the lengths of the grooves in Fig. 9A (reproduced above with annotations added by the examiner; the lengths t1, t2, and t3 in Figs. 9B and 9C determine the protrusion lengths) to be as short as 110 nm and as long as 330 nm.
The groove lengths disclosed by Chen can be incorporated into the combination of Ueda and Pogrebnyak described above as lengths of the protrusions in the range, 110 nm-330 nm. Choosing a length of 110 nm in particular would yield a ratio of the protruding length of the protrusions to the distance between adjacent protrusions of about 0.6286, which lies within the claimed range. The combination of Ueda, Pogrebnyak, and Chen just described teaches “wherein, from the top view above the substrate, a ratio of a protruding length of the protrusion from the edge to a distance between two adjacent protrusions is between 0.5 and 1.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use a length of 110 nm-330 nm for the protrusions as suggested by the disclosure of Chen because it would only require a simple combination of the disclosures of Ueda, Pogrebnyak, and Chen, namely, the incorporation of the lengths of the grooves in Chen into the combination of Ueda and Pogrebnyak, with predictable results, and the fact that the combined disclosures teach a range of ratios that overlaps the claimed range establishes a prima facie case of obviousness (see MPEP 2144.05 I: “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)”).
Regarding claim 7, the combination of Ueda, Pogrebnyak, and Chen just described further teaches “wherein the protruding length is between 160 nm and 330 nm.” As discussed above, the combined disclosures teach a range of protruding lengths between 110 nm and 330 nm, which overlaps the claimed range, and thus establishes a prima facie case of obviousness (see MPEP 2144.05 I).
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Figure 1: Fig. 1A of Chu, reproduced with annotations added by the examiner.
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Fig. 31 of Chu, reproduced above with annotations added by the examiner.
Claims 10 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Ueda in view of Chu et. al., Pub. No. US 2021/0273069, hereafter referred to as Chu.
Regarding claim 10, Ueda teaches “The transistor structure of claim 1”, but does not teach “wherein a material of the gate comprises metal.”
Chu, on the other hand, does teach “wherein a material of the gate comprises metal” (Chu [0022]: “The gate electrode… may be, for example, doped polysilicon, metal, or some other conductive material.”; Fig. 31, reproduced above with annotations added by the examiner, gate 104).
The disclosure of metal as a gate material in Chu can be incorporated as the use of metal as the material for the gate of Ueda.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use metal as a material for the gate in the apparatus of Ueda because metal can also serve as a conducting material suitable for the gate electrode and is a simple substitution of metal as taught by Chu for the gate material of Ueda with a predictable outcome.
Regarding claim 12, Ueda teaches “The transistor structure of claim 11”, but does not teach “wherein a material of the etching stop layer comprises silicon nitride.”
Chu, on the other hand, does teach “wherein a material of the etching stop layer comprises silicon nitride” (Chu [0024]: “The sidewall spacer 708… may be, for example, silicon dioxide, silicon nitride, some other dielectric, or a combination of the foregoing”; Fig. 31).
The disclosure of silicon nitride as a material for the sidewall spacer in Chu can be incorporated as the use of silicon nitride as the material of the side walls in Ueda.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use silicon nitride as a material for the etching stop layer in the apparatus of Ueda because Chu discloses silicon nitride can also serve as an insulating material and is a simple substitution of silicon nitride as disclosed by Chu for the dielectric material of Ueda with a predictable outcome.
Regarding claim 13, Ueda teaches “The transistor structure of claim 11”, but does not teach “wherein the substrate is exposed by the plurality of grooves.”
Chu, on the other hand, does teach “wherein the substrate” (Chu [0017]; Fig. 1A, substrate 106) “is exposed by the plurality of grooves” (Chu [0017]; Fig. 1A, note that portions of the substrate 106 are exposed by the recess regions 118 in the gate structure 110).
The exposure of the substrate by the gate electrode of Chu can be incorporated into the device of Ueda by having the substrate similarly exposed between the grooves in the gate electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have had the substrate of Ueda exposed within the grooves as taught by Chu because doing so will allow the grooves in the gate to extend deeper into the gate electrode, and thus make it easier to design a gate electrode with protrusions of the correct dimensions, and it would be a simple combination of elements of the two disclosures.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT EMIL THROCKMORTON whose telephone number is (571) 272-7014. The examiner can normally be reached 7:30 AM - 12 PM and 1 PM - 5:30 PM ET Monday-Thursday, 7:30 AM - 11:30 AM and 12:30 PM - 4:30 PM ET Friday.
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/R.E.T./ Examiner, Art Unit 2818
/STEVEN H LOKE/ Supervisory Patent Examiner, Art Unit 2818
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