Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election of Inv I and Species I in the reply filed on 3/20/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)). Claims 4-5, 1 3 -20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected species and Group II claims, there being no allowable generic or linking claim . In addition, claim 10 depends on claim 4 and as such claim 10 is also withdrawn . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 1. Claim(s) 1 -3,6-9 ,12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220173094 A1 (Yoshida) in view of US 20080264901 A1 (Zhu). Regarding claim 1 , Yoshida shows (Fig. 1- 11 mainly 11 ) a semiconductor device, comprising: a cell region including cells (IGBT cells in 10, para 50); and a peripheral region (30, para 59) arranged at an outer side of the cell region and surrounding the cell region, wherein the peripheral region includes: a first semiconductor layer (1, para 74) of a first conductive type (n); a second semiconductor region (31, para 59,134) of a second conductive type (p) partially formed on the first semiconductor layer; an insulation film (4, para 134) covering a surface of the first semiconductor layer and a surface of the second semiconductor region; an opening (shown within 5) formed in the insulation film and partially exposing the surface of the second semiconductor region; an electrode (6a) in contact with a portion (top of 31) exposed from the opening; and a passivation film (34, para 134) covering the insulation film and the electrode, the electrode includes: a first part (6a within 4) arranged in the opening; and a second part (6a above the first part) including a projection projecting sideward from the first part and overlapping with the insulation film, the semiconductor device further comprises a barrier layer (5, 33 para 134 ,145 ) arranged between the passivation film and the first semiconductor layer, and the barrier layer includes a portion arranged between the projection and the second semiconductor region. Yoshida does not explicitly teach “ barrier layer having a smaller diffusion coefficient than the insulation film and the passivation film ”. Zhu teaches barrier layer having a smaller diffusion coefficient than the insulation film and the passivation film (para 2). It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Zhu , with diffusion coefficient difference , to the invention of Yoshida . The motivation to do so is that the combination produces the predictable result of protecting the diffusion of metal in the insulation film and the passivation film . Regarding claim 2 , Yoshida shows (Fig. 11) wherein the barrier layer (5 ,33 ) is formed on a surface of the insulation film (4 , para 134 ) , and the barrier layer includes a portion (part of 5 over 4 and below 6a) sandwiched between the insulation film and the projection (6a portion over barrier as shown) . Regarding claim 3 , Yoshida shows (Fig. 11) wherein the insulation film includes: a first insulation film (4 , para 134 ) formed on the surface of the first semiconductor layer and the surface of the second semiconductor region; and a second insulation film (34 , para 134 ) formed on the first insulation film, and the barrier layer (5 , 33 ) is formed on a surface of the second insulation film and is covered by the passivation film. Regarding claim 6 , Yoshida shows (Fig. 11) wherein the barrier layer (5 , 33 para 134 -135 ) includes a wall surface (inside the opening) defining a barrier layer opening into which the first part (6a lower portion) is inserted, and the wall surface defining the barrier layer opening is flush with a wall surface of the insulation film (4 surrounding the opening) defining the opening. Regarding claim 7 , Yoshida shows (Fig. 11) wherein the barrier layer (5 , 33 , para 134 -135 ) extends over an outer edge of the second semiconductor region (31) as viewed in a thickness-wise direction of the first semiconductor layer (1 , para 74 ) . Regarding claim 8 , Yoshida shows (Fig. 11) wherein a thickness of the barrier layer (5 or 33 , para 134 -135 ) is less than a thickness of the insulation film (4) [as shown above] . Regarding claim 9 , Yoshida shows (Fig. 4 ) wherein the cell region (10 , para 50 ) is a region in which a transistor is formed, the cell region includes: the first semiconductor layer (1 , para 74 ) ; a gate oxide film (11b, gate trench insulation film , para 83) formed on the surface of the first semiconductor layer; and an intermediate insulation film (4 over 11b) formed on a surface of the gate oxide film, and the barrier layer (5) is formed on a surface of the intermediate insulation film. Regarding claim 12 , Yoshida shows (Fig. 11) wherein the insulation film (4a, which is similar to 4, F-19) is a silicon oxide film (para 163), the passivation film (34) is an organic insulation film (polyimide, para 146), and the barrier layer (33) is a silicon nitride film (para 145). 2 . Claim(s) 1 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Zhu as applied to claim 1 above, further in view of US 20110233714 A1 ( L u). Regarding claim 11 , Yoshida in view of Zhu shows the peripheral region . Yoshida in view of Zhu does not show wherein the peripheral region includes a semiconductor region of a second conductive type to reduce a surface electric field. Lu shows (Fig. 43) wherein the peripheral region (33) includes a semiconductor region of a second conductive type (38, p) to reduce a surface electric field (para 7) . It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Lu , with another second conductive type semiconductor region , to the invention of Yoshida in view of Zhu . The motivation to do so is that the combination produces the predictable result of relax ing electric field intensity (para 7). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT WASIUL HAIDER whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-1554 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 9 a.m. - 6 p.m. . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT William Partridge can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 270-1402 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WASIUL HAIDER/ Primary Examiner, Art Unit 2812