Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: IGBT WITH IMPROVED TERMINATION STRUCTURE.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
1. Claim(s) 1,3,6-9,12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220173094 A1 (Yoshida) in view of US 8975662 B2 (Hutzler).
Regarding claim 1, Yoshida shows (Fig. 1-11 mainly 11) a semiconductor device, comprising:
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a cell region including cells (IGBT cells in 10, para 50); and
a peripheral region (30, para 59) arranged at an outer side of the cell region and surrounding the cell region, wherein the peripheral region includes:
a first semiconductor layer (1, para 74) of a first conductive type (n);
a second semiconductor region (31, para 59,134) of a second conductive type (p) partially formed on the first semiconductor layer;
an insulation film (4, para 134) covering a surface of the first semiconductor layer and a surface of the second semiconductor region;
an opening (shown within 5) formed in the insulation film and partially exposing the surface of the second semiconductor region;
an electrode (6a) in contact with a portion (top of 31) exposed from the opening; and
a passivation film (34, para 134) covering the insulation film and the electrode, the electrode includes:
a first part (6a within 4) arranged in the opening; and
a second part (6a above the first part) including a projection projecting sideward from the first part and overlapping with the insulation film, the semiconductor device further comprises a barrier layer (5, 33 para 134,145) arranged between the passivation film and the first semiconductor layer, and the barrier layer includes a portion (part of 5 over 4 and below 6a) arranged between the projection and the second semiconductor region;
the portion of the barrier layer is sandwiched between the insulation film and the projection.
Yoshida does not show barrier layer having a smaller diffusion coefficient than the insulation film and the passivation film;
the barrier layer is formed on a surface of the insulation film,
the portion of the barrier layer is sandwiched between the insulation film and the projection, and the barrier layer is electrically insulating.
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Hutzler shows (Fig. 2) barrier layer (220 in 690, SiN, col 4, ln 50-55);
the barrier layer is formed on a surface of the insulation film (210 in 690, col 8, ln 40-50),
the barrier layer is electrically insulating (SiN is insulating).
Yoshida in combination with Hutzler shows barrier layer (220, Hutzler) having a smaller diffusion coefficient than the insulation film (4, Yoshida) and the passivation film (34, Yoshida) [since Yoshida and Hutzler have same materials as the application].
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to modify the invention of Yoshida, including barrier layer, with the invention of Hutzler.
The motivation to do so is that the combination produces dielectric with diffusion barrier to withstand any diffusion from the metal overhangs of the electrodes.
Regarding claim 3, Yoshida shows (Fig. 11) wherein the insulation film includes:
a first insulation film (4, para 134) formed on the surface of the first semiconductor layer and the surface of the second semiconductor region; and
a second insulation film (34, para 134) formed on the first insulation film, and the barrier layer (5, 33) is formed on a surface of the second insulation film and is covered by the passivation film.
Regarding claim 6, Yoshida shows (Fig. 11) wherein the barrier layer (5,33 para 134-135) includes a wall surface (inside the opening) defining a barrier layer opening into which the first part (6a lower portion) is inserted, and the wall surface defining the barrier layer opening is flush with a wall surface of the insulation film (4 surrounding the opening) defining the opening.
Regarding claim 7, Yoshida shows (Fig. 11) wherein the barrier layer (5, 33, para 134-135) extends over an outer edge of the second semiconductor region (31) as viewed in a thickness-wise direction of the first semiconductor layer (1, para 74).
Regarding claim 8, Yoshida shows (Fig. 11) wherein a thickness of the barrier layer (5 or 33, para 134-135) is less than a thickness of the insulation film (4) [as shown above].
Regarding claim 9, Yoshida shows (Fig. 4) wherein the cell region (10, para 50) is a region in which a transistor is formed, the cell region includes:
the first semiconductor layer (1, para 74);
a gate oxide film (11b, gate trench insulation film, para 83) formed on the surface of the first semiconductor layer; and
an intermediate insulation film (4 over 11b) formed on a surface of the gate oxide film, and the barrier layer (5) is formed on a surface of the intermediate insulation film.
Regarding claim 12, Yoshida shows (Fig. 11) wherein the insulation film (4a, which is similar to 4, F-19) is a silicon oxide film (para 163), the passivation film (34) is an organic insulation film (polyimide, para 146), and the barrier layer (33) is a silicon nitride film (para 145).
2. Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Hutzler as applied to claim 1 above, further in view of US 20110233714 A1 (Lu).
Regarding claim 11, Yoshida in view of Hutzler shows the peripheral region.
Yoshida in view of Hutzler does not show wherein the peripheral region includes a semiconductor region of a second conductive type to reduce a surface electric field.
Lu shows (Fig. 43) wherein the peripheral region (33) includes a semiconductor region of a second conductive type (38, p) to reduce a surface electric field (para 7).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Lu, with another second conductive type semiconductor region, to the invention of Yoshida in view of Hutzler.
The motivation to do so is that the combination produces the predictable result of relaxing electric field intensity (para 7).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WASIUL HAIDER whose telephone number is (571)272-1554. The examiner can normally be reached M-F 9 a.m. - 6 p.m..
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/WASIUL HAIDER/Primary Examiner, Art Unit 2812
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