DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/24/2026 has been entered.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 2023-01-13. It is noted, however, that applicant has not filed a certified copy of the KR-10-2023-0005572 application as required by 37 CFR 1.55.
Response to Amendments
Applicant's response of 07/24/2026 has been acknowledged. Claims 1-2 and 17 have been amended. No new matter has been added.
This office action considers claims 1-20 pending for prosecution and are examined on their merits.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (KR 20220147771 A – hereinafter Jeon) in view of Jo et al. (US 20200185489 A1 – hereinafter Jo), Kim et al. (US 20220199746 A1 - hereinafter Kim), and Ko et al. (US 20140239270 A1 – hereinafter Ko-270).
Regarding independent claim 1, Jeon teaches
(Currently Amended) A display device (1 – Fig. 1 – [0043] – “display
device (1)”) comprising:
first (PX1 – Fig. 5 annotated, see below – [0056] – “first pixel (PX1)”), second
(PX2 – Fig. 5 annotated, see below – [0056] – “first pixel (PX2)”), and third sub-pixels (PX3 – Fig. 5 annotated, see below – [0056] – “first pixel (PX3)”) adjacent to each other, each of the first, second, and third sub-pixels including a storage capacitor (Cst – Fig. 5 – [0089] – “storage capacitor (Cst)”);
a scan line (SL – Fig 5 – [0085] – “scan line (SL)”) selectively transferring a scan signal ([0085] – “scan signal is supplied to the scan line (SL)”) and a control signal ([0087] – “third thin film transistor (T3) may be turned on according to a signal received through a scan line (SL) to initialize a pixel electrode of an organic light emitting diode (OLED)” – this describes a control signal, hereinafter ‘CS’) to each of the first, second, and third sub-pixels (PX1-PX3), the scan line (SL) extending in a first direction (x – Fig. 5 – [0046] – “x direction”);
a data line (DL – fig. 5 – [0085] – “data line (DL)”) transferring a data signal ([0092] – “data signal”) to each of the first, second, and third sub-pixels (PX1-PX3), the data line (DL) extending in a second direction (y – Fig. 5 – [0046] – “y direction”) intersecting the first direction (x – Fig. 5 shows this);
a first power line (VDL – Fig. 5 – [0084] – “driving voltage line (VDL)”) electrically connected to each of the first, second, and third sub-pixels ([0084] – “first electrode of the first thin film transistor (T1) is connected to a driving voltage line (VDL) that supplies a driving power voltage (ELVDD), and a second electrode can be connected to a pixel electrode of an organic light emitting diode (OLED)” – this describes an electrical connection to each pixel),
and the first power line (VDL) being configured to receive a first driving power voltage (ELVDD – ([0084] – “driving power voltage (ELVDD)”); and
a second power line (VSL – Fig. 5 – [0090] – “The counter electrode of the organic light-emitting diode (OLED) can be connected to a common voltage line (VSL) that provides a common power supply voltage (ELVSS)”) electrically connected to each of the first, second, and third sub-pixels (PX1-3) and the second power line (VSL) being configured to receive a second driving power voltage (ELVSS – [0090] – “The counter electrode of the organic light-emitting diode (OLED) can be connected to a common voltage line (VSL) that provides a common power supply voltage (ELVSS)”) different from the first driving power voltage (ELVDD),
wherein the first power line includes a first vertical power line and a first horizontal power line,
the second power line includes a second vertical power line and a second horizontal power line, and
in a plan view, the first vertical power line is between the storage capacitor and the data line, the storage capacitor is between the first vertical power line and the second vertical power line, and the storage capacitor is between the first horizontal power line and the second horizontal power line, and each of the first vertical power line, the first horizontal power line, the second vertical power line, and the second horizontal power line is vertically offset from the storage capacitor.
Jeon does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Jo teaches
wherein the first power line (ELVDD – Fig 2 – [0097] – “driving voltage ELVDD”) includes a first vertical power line (ELVDD in DR1 direction – Fig 2 – [0097] – “driving voltage ELVDD is transmitted in a mesh formation in the first direction DR1 and the second direction DR2 throughout the entire display device”) and a first horizontal power line (ELVDD in DR2 direction – Fig 2 – [0097] – “driving voltage ELVDD is transmitted in a mesh formation in the first direction DR1 and the second direction DR2 throughout the entire display device”),
the second power line (ELVSS – Fig. 2 – [0098] – “the common voltage ELVSS”) includes a second vertical power line (ELVSS in DR1 direction – Fig. 2 – [0098] – “the common voltage ELVSS is transmitted in the mesh formation in the first direction DR1 and the second direction DR2 throughout the entire display device”) and a second horizontal power line (ELVSS in DR2 direction – Fig. 2 – [0098] – “the common voltage ELVSS is transmitted in the mesh formation in the first direction DR1 and the second direction DR2 throughout the entire display device”),
the storage capacitor (Cst1 – Fig. 2 – [0077] – “capacitor Cst1”) is between the first vertical power line (ELVDD in DR1 direction) and the second vertical power line (ELVSS in DR1 direction – Fig. 2 – [0098] – “the common voltage ELVSS is transmitted in the mesh formation in the first direction DR1 and the second direction DR2 throughout the entire display device”), and the storage capacitor (Cst1) is between the first horizontal power line (ELVDD in DR2 direction) and the second horizontal power line (ELVSS in DR2 direction).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the power lines and capacitor structure as taught by Jo into Jeon.
An ordinary artisan would have been motivated to use the known technique of Jo in the manner set forth above to produce the predictable result of [0004] – “the light emitting diode display has characteristics such as low power consumption, high luminance, and high response speed.”
Jeon and Jo do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Kim teaches
in a plan view, the first vertical power line (VDDL – Fig. 4 – [0048] – “pixel power line VDDL”) is between the storage capacitor ([0072] – “The capacitor serves to maintain the data voltage supplied to the driving transistors TR1, TR2, TR3 and TR4 for one frame” – Jeon shows the storage capacitor and the drive transistor overlapping the pixel, Kim is interpreted to have the same type of configuration therefore the capacitor, though not shown, is overlapping the pixel and next to the drive transistor shown as TR1 in Fig. 4 – hereinafter ‘Cst’) and the data line (DL1 – Fig. 4 – [0076] – “data line DL1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the powerline and capacitor structure as taught by Kim into Jeon and Jo.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable results of [0005] – “a transparent display device may improve transparency by increasing a transmissive area. When the transmissive area is increased, the non-transmissive area is reduced. This can cause a difficulty in that a plurality of signal lines and a plurality of driving transistors that should be disposed in a non-transmissive area now should fit in an area of a more narrow size.”
Jeon, Jo, and Kim do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Ko-270 teaches
each of the first vertical power line, the first horizontal power line, the second vertical power line, and the second horizontal power line ([0099] – “the driving voltage line 26 may be connected to pixels that are adjacent each other in the row direction (i.e., the second direction), and thus may be formed in a mesh structure” – applicant’s limitations describe power lines in a mesh structure, Ko-270 has a corresponding driving voltage lines form a mesh structure) is vertically offset from the storage capacitor ([0099] – “the data line 16 and the driving voltage line 26 are formed on different layers, and the driving voltage line 26 is located between the data line 16 and the storage capacitor Cst” – this describe the limitation of the power mesh and the storage capacitor are in different layers i.e. “vertical offset”, this is shown in Fig. 5).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the powerline and capacitor structure as taught by Ko-270 into Jeon, Jo, and Kim.
An ordinary artisan would have been motivated to use the known technique of Ko-270 in the manner set forth above to produce the predictable results of [0099] – “due to the driving voltage line 26 of the mesh structure, the voltage drop of the first power voltage ELVDD may be reduced or prevented.”
Claims 2-8, 13-14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Jo, Kim, Ko-270, Chen (US 20210226156 A1 – hereinafter Chen), Sun et al. (US 20210408153 A1 – hereinafter Sun), and Ko et al. (KR 20210016003 A – hereinafter Ko).
Regarding claim 2, Jeon, as modified by Jo, Kim, and Ko-270, teaches claim 1 from which claim 2 depends. Jeon further teaches
an initialization power line (INL – Fig. 5 – [0086] – “initialization voltage
line (INL)”) configured to receive an initialization power voltage ([0094] – “initialization voltage line (INL) transmits an initialization voltage”), wherein,
the first, second, and third sub-pixels (PX1-3).
Jeon, Kim, and Ko-270 do not expressly disclose the other limitations of claim 2.
However, in an analogous art, Jo teaches
(ELVDD in DR2 direction – Fig 2 – [0097] – “driving voltage ELVDD is transmitted in a mesh formation in the first direction DR1 and the second direction DR2 throughout the entire display device”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the power lines and capacitor structure as taught by Jo into Jeon, Kim, and Ko-270.
An ordinary artisan would have been motivated to use the known technique of Jo in the manner set forth above to produce the predictable result as stated above in claim 1.
Jeon, Kim, Ko-270, and Jo do not expressly disclose the other limitations of claim 2.
However, in an analogous art, Chen teaches
(Currently Amended) The display device of claim 1, further comprising:
a substrate (10 – Fig. 3 – [0036] – “substrate 10”);
a first insulating layer (24 – Fig. 3 – [0047] – “insulating layer 24”), a second
insulating layer (23 – Fig. 3 – [0047] – “insulating layer 23”), a third insulating layer (22 – Fig. 3 – [0047] – “insulating layer 22”), and a fourth insulating layer (21 – Fig. 3 – [0047] – “insulating layer 21”), sequentially (10 – [0047] – “stacked on the substrate 10 in sequential” – fig. 3 shows this); [[;]]
and
an initialization power line configured to receive an initialization power voltage, wherein
the first vertical power line is a
first conductive layer on the substrate, and
the first horizontal powerline is a second conductive layer on the second insulating layer, and
in a plan view, the first vertical power line is between the storage capacitor of each of the first, second, and third sub-pixels and the data line.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the substrate and insulating layer structure as taught by Chen into Jeon, Kim, Ko-270, and Jo.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable result of [0047] – “packaging effect can be improved.” Packaging effect plays a vital role in thermal packaging and electromagnetic interference shielding.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Jeon, Kim, Ko-270, Jo, and Chen do not expressly disclose the other limitations of claim 2.
However, in an analogous art, Sun teaches
the first vertical power line is a first conductive layer (200 – Fig. 5a – {[0115] – “first conductive layer 200 disposed on a substrate 100”}, {[0125] – “first conductive layer 200 may include a first power line 210”}) on the substrate (100 – Fig. 5a – [0115] – “first conductive layer 200 disposed on a substrate 100”), and
the first horizontal powerline is a second conductive layer (600 – Fig. 5a –
{[0149] – “second conductive layer 600 between the second insulating layer 500 … the second conductive layer 600 may include a second power line 610”) on the second insulating layer (500 – Fig. 5a – [0149] – “second conductive layer 600 between the second insulating layer 500”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first powerline and conductive layer structure as taught by Sun into Jeon, Kim, Ko-270, Jo, and Chen.
An ordinary artisan would have been motivated to use the known technique of Sun in the manner set forth above to produce the predictable result [0003] – “to achieve a high-resolution design in a display panel” by using separate conductive layers to allow for more complex circuitry within a compact footprint.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Jeon, Kim, Ko-270, Jo, Chen, and Sun do not expressly disclose the other limitations of claim 2.
However, in an analogous art, Ko teaches
in a plan view, the first vertical power line (26) is between [0014] –
“a driving voltage line disposed between the capacitor and the data line”) the storage capacitor (Cst) of each of the first, second, and third sub-pixels and the data line (16).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first power line position as taught by Ko into Jeon, Kim, Ko-270, Jo, Chen, and Sun.
An ordinary artisan would have been motivated to use the known technique of Ko in the manner set forth above to produce the predictable result of [0004] – “a driving voltage line in a mesh structure while suppressing crosstalk defects caused by coupling between a data line and a capacitor, and an organic light-emitting display including the same.”
Regarding claim 3, Jeon as modified by Jo, Kim, Ko-270, Chen, Sun, and Ko, teaches claim 2 from which claim 3 depends. Jeon further teaches
(Original) The display device of claim 2, wherein each of the first,
second, and third sub-pixels includes (PX1-PX3):
a light emitting element (OLED – Fig. 6 – [0051] – “light emitting unit (10) may include a plurality of organic light emitting diodes (OLEDs) as light emitting elements that generate light”);
a first transistor (T1 – Fig. 4 – [0084] – “first electrode of the first thin film transistor (T1) is connected to a driving voltage line (VDL) that supplies a driving power voltage (ELVDD), and a second electrode can be connected to a pixel electrode of an organic light emitting diode (OLED)”) controlling a current of the light emitting element (OLED);
a second transistor (T2 – Fig. 4 – [0085] – “first electrode of the second thin film transistor (T2) can be connected to the data line (DL), and the second electrode can be connected to the first node (N1)”) connected between the data line (DL – Fig. 4 – [0085] – “first electrode of the second thin film transistor (T2) can be connected to the data line (DL), and the second electrode can be connected to the first node (N1)”) and a gate electrode (G1 – [0105] – “first thin film transistor (T1) may include a first semiconductor layer (A1) and a first gate electrode (G1)”}, {[0085] – “first electrode of the second thin film transistor (T2) can be connected to the data line (DL), and the second electrode can be connected to the first node (N1)”}, {[0084] – “gate electrode of the first thin film transistor (T1) can be connected to the first node (N1)”} – Fig. 4 shows this) of the first transistor (T1), the second transistor (T2) being turned on by the scan signal ([0085] – “second thin film transistor (T2) can be turned on when a scan signal is supplied to the scan line (SL)” – hereinafter ‘SSL’);
a third transistor (T3 – [0086] – “third thin film transistor (T3) can be connected to the second node (N2), and the second electrode can be connected to the initialization voltage line (INL)”) connected between the initialization power line (INL) and a source electrode of the first transistor (T1 – Fig. 4 shows this), the third transistor (T3) being turned on by the control signal (CS); and
the storage capacitor (Cst – Fig. 4 – [0089] – “storage capacitor (Cst)”) including:
a lower electrode electrically (CE1 – [[0012] – “second capacitor plate (CE2) is positioned above the first capacitor plate (CE1)”) connected to the gate electrode (G1 – [0112] – “first capacitor plate (CE1) can be formed integrally with the first gate electrode (G1)”) of the first transistor (T1) and a source electrode ([0083] – “Each thin film transistor has a first electrode and a second electrode, and depending on the type of thin film transistor, the first electrode may be one of a source electrode and a drain electrode, and the second electrode may be the other of the source electrode and the drain electrode.” – hereinafter ‘SE2’) of the second transistor (T2 – Fig. 4 shows this), and
an upper electrode (CE2 – [0112] – “second capacitor plate (CE2) is positioned above the first capacitor plate (CE1)”) electrically connected to the source electrode of the first transistor (T1) and a source electrode of the third transistor (T3 – Fig. 4 shows this).
Regarding claim 4, Jeon as modified by Jo, Kim, Ko-270, Chen, Sun, and Ko, teaches claim 3 from which claim 4 depends. Jeon further teaches
(Previously Presented) The display device of claim 3, wherein the
first transistor (T1), the second transistor (T2), and the third transistor (T3) are at a side of the storage capacitor (Cst – Fig. 5 shows this).
Regarding claim 5, Jeon as modified by Jo, Kim, Ko-270, Chen, Sun, and Ko, teaches claim 3 from which claim 5 depends. Jeon, Kim, Ko-270, Chen, and Ko do not expressly disclose the limitations of claim 5.
However, in an analogous art, Jo teaches
(Previously Presented) The display device of claim 3, wherein
the first conductive layer includes the second vertical power line (ELVSS in
DR1 direction), and
the second conductive layer includes the second horizontal power line
(ELVSS in DR2 direction – Fig. 2 – [0098] – “the common voltage ELVSS is transmitted in the mesh formation in the first direction DR1 and the second direction DR2 throughout the entire display device”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the power lines and capacitor structure as taught by Jo into Jeon, Kim, Ko-270, Chen, and Ko.
An ordinary artisan would have been motivated to use the known technique of Jo in the manner set forth above to produce the predictable result as stated above in claim 1.
Jeon, Kim, Ko-270, Chen, Ko and Jo do not expressly disclose the other limitations of claim 5.
However, in an analogous art, Sun teaches
the first conductive layer (200 – Fig. 5a – {[0115] – “first conductive layer 200 disposed on a substrate 100”}, {[0125] – “first conductive layer 200 may include a first power line 210”}),
the second conductive layer (600) (sun (600 – Fig. 5a – {[0149] – “second conductive layer 600 between the second insulating layer 500 … the second conductive layer 600 may include a second power line 610”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first powerline and conductive layer structure as taught by Sun into Jeon, Kim, Ko-270, Chen, Ko and Jo.
An ordinary artisan would have been motivated to use the known technique of Sun in the manner set forth above to produce the predictable result as stated above in claim 2.
Regarding claim 6, Jeon as modified by Jo, Kim, Ko-270, Chen, Sun, and Ko, teaches claim 5 from which claim 6 depends. Jeon further teaches
(Previously Presented) The display device of claim 5, wherein, in a
plan view, the initialization power line (INL) is between the first vertical power line (VDL – this is a vertical power line) and the data line (DL, Fig. 5 shows this).
Regarding claim 7, Jeon as modified by Jo, Kim, Ko-270, Chen, Sun, and Ko, teaches claim 6 from which claim 7 depends. Jeon further teaches
(Previously Presented) The display device of claim 6, wherein the
gate electrode (G1) of the first transistor (T1) of each of the first (PX1), second (PX2), and third sub-pixels (PX3) is between the storage capacitor (Cst) and the first vertical power line (VDL – this is a vertical power line, Fig. 5 shows this).
Regarding claim 8, Jeon as modified by Jo, Kim, Ko-270, Chen, Sun, and Ko, teaches claim 3 from which claim 8 depends. Jeon, Kim, Ko-270, Chen, Sun, and Ko do not expressly disclose the limitations of claim 8.
However, in an analogous art, Jo teaches
(Previously Presented) The display device of claim 3, wherein
the lower electrode (111 – Fig. 5 – [0050] – “lower patterns 111 as a first conductive layer may be disposed on the substrate 110”) is on the substrate (110 – Fig. 5 – [0050] – “the substrate 110”), and
the upper electrode (155 – Fig. 5 – [0077] – “driving gate electrode 155 may
overlap most of the lower pattern 111 with the buffer layer 120 and the first insulating layer 140 therebetween to form the capacitor Cst1”) is on the first insulating layer (140 – Fig. 5 – [0077] – “driving gate electrode 155 may overlap most of the lower pattern 111 with the buffer layer 120 and the first insulating layer 140 therebetween to form the capacitor Cst1”) to overlap the lower electrode (111) with the first insulating layer (140) interposed between the lower electrode (111) and the upper electrode (155 – Fig. 5 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate electrode structure as taught by Jo into Jeon, Kim, Ko-270, Chen, Sun, and Ko.
An ordinary artisan would have been motivated to use the known technique of Jo in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 13, Jeon as modified by Jo, Kim, Ko-270, Chen, Sun, and Ko, teaches claim 5 from which claim 13 depends. Jeon further teaches
(Previously Presented) The display device of claim 5, wherein, in a
plan view, the initialization power line (INL) is between the second vertical power line (VSL – this is a vertical power line) and the storage capacitor (Cst – Fig. 5 shows this).
Regarding claim 14, Jeon as modified by Jo, Kim, Ko-270, Chen, Sun, and Ko, teaches claim 13 from which claim 14 depends. Jeon further teaches
(Previously Presented) The display device of claim 13, wherein
in a plan view, the initialization power line (INL) is at a first side of the storage capacitor (Cst), and
in a plan view, the first vertical power line (VDL – this is a vertical power line) is (Cst – Fig. 5 shows this).
Regarding claim 16, Jeon as modified by Jo, Kim, Ko-270, Chen, Sun, and Ko, teaches claim 3 from which claim 16 depends. Jeon further teaches
(Previously Presented) The display device of claim 3, wherein each
of the first, second, and third sub-pixels (PX1-3) further includes:
an encapsulation layer (300 – Fig. 6 – [0148] – “encapsulating layer (300)”) over the light emitting element (OLED – Fig. 6 shows this);
a color filter layer (500 – [0150] – “Although not shown in FIG. 6, the color conversion-transmitting layer (500, see FIG. 2) described above with reference to FIG. 2 may be placed on the counter electrode (230) of the organic light-emitting diode (OLED)” – this is a color filter) on the encapsulation layer (300); and
an overcoat layer (600 – [0150] – “Additionally, the color filter layer (600) can be placed on the color conversion-transmitting layer (500)” – this is an overcoat layer) over the color filter layer (500).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Jo, Kim, Ko-270, Chen, Sun, Ko, and Lee et al. (US 20230363215 A1 – hereinafter Lee).
Regarding claim 9, Jeon as modified by Jo, Kim, Ko-270, Chen, Sun, and Ko, teaches claim 8 from which claim 9 depends. Jeon, Jo, Kim, Ko-270, Chen, Sun, and Ko do not expressly disclose the limitations of claim 9.
However, in an analogous art, Lee teaches
(Previously Presented) The display device of claim 8, wherein the upper
electrode (650B – Fig. 6A – [0169] – “second electrode 650B of the storage capacitor formed by imparting conductivity to the same material as the first oxide semiconductor pattern 474 on the same layer as the first oxide semiconductor pattern 474”) and an active pattern layer of each of the first transistor (474 – Fig. 6A – [0169] – “second electrode 650B of the storage capacitor formed by imparting conductivity to the same material as the first oxide semiconductor pattern 474 on the same layer as the first oxide semiconductor pattern 474”), the second transistor (this is a repetition of the first transistor), and the third transistor are (this is a repetition of the first transistor) on a same layer (Fig. 6A – [0169] – “second electrode 650B of the storage capacitor formed by imparting conductivity to the same material as the first oxide semiconductor pattern 474 on the same layer as the first oxide semiconductor pattern 474”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the upper electrode and transistor active pattern structure as taught by Lee into Jeon, Jo, Kim, Ko-270, Chen, Sun, and Ko.
An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable result [0006] – “to provide an organic light emitting display apparatus having a capacitor structure capable of providing a capacitance value of a predetermined capacity or more in a subpixel while realizing high resolution.”
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Jo, Kim, Ko-270, Chen, Sun, Ko, and Lee, Hwang et al. (US 20200006401 A1 – hereinafter Hwang), and Yuan et al. (US 20240268148 A1 – hereinafter Yuan).
Regarding claim 10, Jeon as modified by Jo, Kim, Ko-270, Chen, Sun, Ko, and Lee, teaches claim 9 from which claim 10 depends. Jeon, Jo, Kim, Ko-270, Chen, Sun, Ko, and Lee do not expressly disclose the limitations of claim 10.
However, in an analogous art, Hwang teaches
(Original) The display device of claim 9, wherein the upper electrode (Cse21
– Fig. 9 – [0138] – “capacitor Cse2 is formed by the first electrode Cse21 which is the first electrode E11 of the first transistor T1”) is integral with the source electrode of the first transistor ([0070] – ‘’ electrodes E11, E21, E31, E41, E51, E61, and E71 and second electrodes E12, E22, E32, E42, E52, E62, and E72 of FIG. 2 may be a source electrode”) and the source electrode of the third transistor.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the upper electrode and drive transistor source electrode structure as taught by Hwang into Jeon, Jo, Kim, Ko-270, Chen, Sun, Ko, and Lee.
An ordinary artisan would have been motivated to use the known technique of Hwang in the manner set forth above to produce the predictable result of [0006] – “Devices constructed according to exemplary implementations of the invention are capable of reducing or preventing color smear phenomenon by compensating for hysteresis. For example, compensation capacitors in the pixel driving circuits of the display may compensate for hysteresis by voltage stabilization.”
Jeon, Jo, Kim, Ko-270, Chen, Sun, Ko, Lee, and Hwang do not expressly disclose the other limitations of claim 10.
However, in an analogous art, Yuan teaches
wherein the upper electrode is integral with the source electrode of the first
transistor and the source electrode of the third transistor ([0068] – “active layer pattern 122 of the first initialization transistor T2 and the active layer pattern 121 of the driving transistor T1 are both in direct contact with and electrically connected to the first electrode plate C1 of the storage capacitor Cst, so that the active layer pattern 122 of the first initialization transistor T2 is electrically connected to the active layer pattern 121 of the driving transistor T1 through the first electrode plate C1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the upper electrode and initialization transistor source electrode structure as taught by Yuan into Jeon, Jo, Kim, Ko-270, Chen, Sun, Ko, Lee, and Hwang. The electrode plate C1 of Yuan can be substituted with a semiconductor material as taught by Hwang thus making the source electrodes of the two transistors of Yuan integral.
An ordinary artisan would have been motivated to use the known technique of Yuan in the manner set forth above to produce the predictable result of [0003] – “A display panel with high resolution and high pixel density has become an important direction for the development of the display panel due to its dearer picture display effect.”
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Jo, Kim, Ko-270, Chen, Sun, Ko, and Moon et al. (US 20200119115 A1 – hereinafter Moon).
Regarding claim 11, Jeon as modified by Jo, Kim, Ko-270, Chen, Sun, and Ko, teaches claim 3 from which claim 11 depends. Jeon, Jo, Kim, Ko-270, Chen, and Ko do not expressly disclose the limitations of claim 11.
However, in an analogous art, Sun teaches
a third conductive layer ([0115] - “a first conductive layer 200 disposed on a substrate 100, a first insulating layer 300 above the first conductive layer 200, and an anode 400 on the first insulating layer 300” – 400 can be considered a third conductive layer).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive layer structure as taught by Sun into Jeon, Jo, Kim, Ko-270, Chen, and Ko.
An ordinary artisan would have been motivated to use the known technique of Sun in the manner set forth above to produce the predictable result [0003] – “to achieve a high-resolution design in a display panel” by using separate conductive layers to allow for more complex circuitry within a compact footprint.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Jeon, Jo, Kim, Ko-270, Chen, Ko, and Sun do not expressly disclose the other limitations of claim 11.
However, in an analogous art, Moon teaches
(Previously Presented) The display device of claim 3, wherein the light
emitting element (PX1– Fig. 9 – [0098] – “first pixel PX1” – this is a light emitting element) includes:
a first electrode (320R – Fig. 9 – [0099] – “first pixel electrode 320R”) formed
as a third conductive layer on the fourth insulating layer (107 – Fig. 9 – [0089] – “insulating layer 107”);
a light emitting layer (312 – Fig. 9 – [0099] – “emission layer 312”) on the first electrode (320R); and
a second electrode (330 – Fig. 9 – [0101] – “opposite electrode 330”) on the light emitting layer (312).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the light emitting element structure as taught by Moon into Jeon, Jo, Kim, Ko-270, Chen, Ko, and Sun.
An ordinary artisan would have been motivated to use the known technique of Moon in the manner set forth above to produce the predictable result of [0004] – “display apparatuses having high resolution.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 12, Jeon as modified by Jo, Kim, Ko-270, Chen, Sun, Ko, and Moon, teaches claim 11 from which claim 12 depends. Jeon, Jo, Kim, Ko-270, Chen, Sun, and Ko do not expressly disclose the limitations of claim 11.
However, in an analogous art, Moon teaches
(Previously Presented) The display device of claim 11, wherein the first
electrode (320R) is electrically connected to the source electrode of the first transistor (SA11 – [0065] – “first driving source area SA11” – this is shown as A11 in Fig. 9) through a contact part (320a – Fig. 9 annotated, see below – [0090] – “pixel electrodes 320R, 320G, and 320B are connected to the first, second, and third upper electrode layers 161, 162, and 163 via a contact hole 320a”) passing through the second insulating layer, the third insulating layer, and the fourth insulating layer (Fig. 9 shows {103 – [0069] – “insulating layer 103”}, {105 – [0078] – “insulating layer 105”}, and {107}).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the light emitting element structure as taught by Moon into Jeon, Jo, Kim, Ko-270, Chen, Sun, and Ko.
An ordinary artisan would have been motivated to use the known technique of Moon in the manner set forth above to produce the predictable result as stated above in claim 11.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Jo, Kim, Ko-270, Chen, Sun, Ko, and Yuan.
Regarding claim 15, Jeon as modified by Jo, Kim, Ko-270, Chen, Sun, and Ko, teaches claim 14 from which claim 15 depends. Jeon, Jo, Kim, Ko-270, Chen, Sun, and Ko, do not expressly disclose the limitations of claim 15.
However, in an analogous art, Yuan teaches
(Previously Presented) The display device of claim 14, wherein
in a plan view, the third transistor (T2 – Fig. 3 – [0066] – “initialization
transistor T2”) among the first transistor (T1 – Fig. 3 – [0066] – “driving transistor T1”), the second transistor (T3 – Fig. 3 – [0074] – “data writing transistor T3”), and the third transistor is disposed at the first side of the storage capacitor (Cst – Fig. 4 – [0066] – “storage capacitor Cst”), and
in a plan view, the first transistor (T1) and the second transistor (T3) among the first transistor (T1), the second transistor (T3), and the third transistor (T2) are at the second side of the storage capacitor (Cst – Fig. 4 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to substitute the transistor and capacitor locations as taught by Yuan into Jeon, Jo, Kim, Ko-270, Chen, Sun, and Ko.
An ordinary artisan would have been motivated to use the known technique of Yuan in the manner set forth above to produce the predictable result of [0003] – “A display panel with high resolution and high pixel density has become an important direction for the development of the display panel due to its dearer picture display effect.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Moon, Jo, and Kim.
Regarding independent claim 17, Jeon teaches
(Currently Amended) A display device (1 – Fig. 1 – [0043] – “display
device (1)”) comprising:
a substrate;
a first insulating layer, a second insulating layer, a third insulating layer, and a
fourth insulating layer sequentially on the substrate;
a first sub-pixel, a second sub-pixel, and a third sub-pixel each including:
a pixel circuit including a storage capacitor and a first transistor, a second transistor, and a third transistor, which are on the substrate, and
a light emitting element electrically connected to the pixel circuit;
a scan line on the substrate, the scan line being configured to selectively transfer
a scan signal and a control signal to each of the first sub-pixel, the second sub-pixel, and the third sub-pixel;
a data line configured to transfer a data signal to each of the first sub-pixel, the second sub-pixel, and the third sub-pixel;
a first power line configured to receive a first power voltage;
a second power line (VSL – Fig. 5 – [0090] – “The counter electrode of the organic light-emitting diode (OLED) can be connected to a common voltage line (VSL) that provides a common power supply voltage (ELVSS)”) configured to receive a second driving power voltage (ELVSS – [0090] – “common power supply voltage (ELVSS)”), the second power voltage being different from the first power voltage (ELVDD – ([0084] – “driving power voltage (ELVDD)”); and
an initialization power line (INL – Fig. 5 – [0086] – “initialization voltage line (INL)”) configured to receive an initialization power voltage ([0094] – “initialization voltage line (INL) transmits an initialization voltage”), the initialization power voltage being different ([0094] – “initialization voltage line (INL) transmits an initialization voltage (e.g., about 2 volts) that is lower than the voltage for emitting light (e.g., about 8 volts)”) from the first power voltage (ELVDD) and the second (ELVSS) power voltage,
wherein a gate electrode (G1 – [0105] – “first thin film transistor (T1) may include a first semiconductor layer (A1) and a first gate electrode (G1)”) of the first transistor (T1 – [0105] – “first thin film transistor (T1)”) is between the storage capacitor (Cst – Fig. 5 – [0089] – “storage capacitor (Cst)”) and the first power line (VDL – Fig. 5 – [0084] – “driving voltage line (VDL)” – Fig. 5 shows this),
the first power line includes a first vertical power line and a first horizontal power line,
the second power line includes a second vertical power line and a second horizontal power line, and
in a plan view, the first vertical power line is between the storage capacitor and the data line, the storage capacitor is between the first vertical power line and the second vertical power line, and the storage capacitor is between the first horizontal power line and the second horizontal power line, and each of the first vertical power line, the first horizontal power line, the second vertical power line, and the second horizontal power line is vertically offset from the storage capacitor.
Jeon does not expressly disclose the other limitations of claim 17.
However, in an analogous art, Moon teaches
a substrate (100 – Fig. 9 – [0040] – “substrate 100”);
a first insulating layer (101 – Fig. 9 – [0061] – “buffer layer 101”), a second
insulating layer (103 – Fig. 9 – [0069] – “insulating layer 103”), a third insulating layer (105 – Fig. 9 – [0078] – “insulating layer 105”), and a fourth (107 – Fig. 9 – [0089] – “insulating layer 107”) insulating layer sequentially on the substrate (100 – Fig. 9 shows this);
a first sub-pixel (PX1 – Fig. 4 – [0054] – “Each of the first through third pixels PX1, PX2, and PX3 may include one or more TFT and a storage capacitor”), a second sub-pixel (PX2 – Fig. 4 – [0054] – “Each of the first through third pixels PX1, PX2, and PX3 may include one or more TFT and a storage capacitor”), and a third sub-pixel (PX3 – Fig. 4 – [0054] – “Each of the first through third pixels PX1, PX2, and PX3 may include one or more TFT and a storage capacitor”) each including:
a pixel circuit (PC – Fig. 3 – [0048] – “pixel circuit PC of FIG. 3 may include the first TFT T1, the second TFT T2, a third TFT T3, and the storage capacitor Cst”) including a storage capacitor (Cst – Fig. 3 – [0048] – “pixel circuit PC of FIG. 3 may include the first TFT T1, the second TFT T2, a third TFT T3, and the storage capacitor Cst”) and a first transistor (T1 – Fig. 3 – [0048] – “pixel circuit PC of FIG. 3 may include the first TFT T1, the second TFT T2, a third TFT T3, and the storage capacitor Cst”), a second transistor (T2 – Fig. 3 – [0048] – “pixel circuit PC of FIG. 3 may include the first TFT T1, the second TFT T2, a third TFT T3, and the storage capacitor Cst”), and a third transistor (T3 – Fig. 3 – [0048] – “pixel circuit PC of FIG. 3 may include the first TFT T1, the second TFT T2, a third TFT T3, and the storage capacitor Cst”), which are on the substrate (100), and
a light emitting element (OLED – Fig. 2 – [0041] – “organic light-emitting devices (OLEDs)”) electrically connected to the pixel circuit (PC);
a scan line (SL – Fig. 3 – [0046] – “scan line SL”) on the substrate (100), the scan line (SL) being configured to selectively transfer a scan signal ([0057] – “pixel unit PXU includes a scan line 121 and a sensing line 123, which intersect with the data wiring unit 150, apply each of a scan signal and a sensing signal”) and a control signal ({[0057] – “sensing signal”}, {SSL – Fig. 3 – [0050] – “third TFT T3 is a sensing TFT and includes a gate electrode connected to a sensing line SSL”} – this is a control signal) to each of the first sub-pixel (PX1), the second sub-pixel (PX2), and the third sub-pixel (PX3);
a data line (DL – Fig. 3 – [0046] – “data line DL”) configured to transfer a data signal ([0024] – “first data line for transmitting a data signal to the first pixel, a second data line for transmitting a data signal to the second pixel, and a third data line for transmitting a data signal to the third pixel”) to each of the first sub-pixel (PX1) , the second sub-pixel (PX2), and the third sub-pixel (PX3);
a first power line (PL– [0046] – “driving voltage line PL”) configured to receive a first power voltage (ELVDD – Fig. 3 – [0046] – “first power supply voltage ELVDD”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the light emitting element structure as taught by Moon into Jeon.
An ordinary artisan would have been motivated to use the known technique of Moon in the manner set forth above to produce the predictable result of [0004] – “display apparatuses having high resolution.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Jeon and Moon do not expressly disclose the other limitations of claim 17.
However, in an analogous art, Jo teaches
the first power line (ELVDD – Fig 2 – [0097] – “driving voltage ELVDD”) includes a first vertical power line (ELVDD in DR1 direction – Fig 2 – [0097] – “driving voltage ELVDD is transmitted in a mesh formation in the first direction DR1 and the second direction DR2 throughout the entire display device”) and a first horizontal power line (ELVDD in DR2 direction – Fig 2 – [0097] – “driving voltage ELVDD is transmitted in a mesh formation in the first direction DR1 and the second direction DR2 throughout the entire display device”),
the second power line (ELVSS – Fig. 2 – [0098] – “the common voltage ELVSS”) includes a second vertical power line (ELVSS in DR1 direction – Fig. 2 – [0098] – “the common voltage ELVSS is transmitted in the mesh formation in the first direction DR1 and the second direction DR2 throughout the entire display device”) and a second horizontal power line (ELVSS in DR2 direction – Fig. 2 – [0098] – “the common voltage ELVSS is transmitted in the mesh formation in the first direction DR1 and the second direction DR2 throughout the entire display device”),
the storage capacitor (Cst1 – Fig. 2 – [0077] – “capacitor Cst1”) is between the first vertical power line (ELVDD in DR1 direction) and the second vertical power line (ELVSS in DR1 direction – Fig. 2 – [0098] – “the common voltage ELVSS is transmitted in the mesh formation in the first direction DR1 and the second direction DR2 throughout the entire display device”), and the storage capacitor (Cst1) is between the first horizontal power line (ELVDD in DR2 direction) and the second horizontal power line (ELVSS in DR2 direction).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the power lines and capacitor structure as taught by Jo into Jeon and Moon.
An ordinary artisan would have been motivated to use the known technique of Jo in the manner set forth above to produce the predictable result of [0004] – “the light emitting diode display has characteristics such as low power consumption, high luminance, and high response speed.”
Jeon, Moon, and Jo do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Kim teaches
in a plan view, the first vertical power line (VDDL – Fig. 4 – [0048] – “pixel power line VDDL”) is between the storage capacitor ([0072] – “The capacitor serves to maintain the data voltage supplied to the driving transistors TR1, TR2, TR3 and TR4 for one frame” – Jeon shows the storage capacitor and the drive transistor overlapping the pixel, Kim is interpreted to have the same type of configuration therefore the capacitor, though not shown, is overlapping the pixel and next to the drive transistor shown as TR1 in Fig. 4 – hereinafter ‘Cst’) and the data line (DL1 – Fig. 4 – [0076] – “data line DL1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the powerline and capacitor structure as taught by Kim into Jeon, Moon, and Jo.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable of [0005] – “a transparent display device may improve transparency by increasing a transmissive area. When the transmissive area is increased, the non-transmissive area is reduced. This can cause a difficulty in that a plurality of signal lines and a plurality of driving transistors that should be disposed in a non-transmissive area now should fit in an area of a more narrow size.”
Jeon, Moon, Jo, and Kim do not expressly disclose the other limitations of claim 17.
However, in an analogous art, Ko-270 teaches
each of the first vertical power line, the first horizontal power line, the second vertical power line, and the second horizontal power line ([0099] – “the driving voltage line 26 may be connected to pixels that are adjacent each other in the row direction (i.e., the second direction), and thus may be formed in a mesh structure” – applicant’s limitations describe power lines in a mesh structure, Ko-270 has a corresponding driving voltage lines form a mesh structure) is vertically offset from the storage capacitor ([0099] – “the data line 16 and the driving voltage line 26 are formed on different layers, and the driving voltage line 26 is located between the data line 16 and the storage capacitor Cst” – this describe the limitation of the power mesh and the storage capacitor are in different layers i.e. “vertical offset”, this is shown in Fig. 5).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the powerline and capacitor structure as taught by Ko-270 into Jeon, Moon, Jo, and Kim.
An ordinary artisan would have been motivated to use the known technique of Ko-270 in the manner set forth above to produce the predictable results of [0099] – “due to the driving voltage line 26 of the mesh structure, the voltage drop of the first power voltage ELVDD may be reduced or prevented.”
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Moon, Jo, Kim, Ko-270, and Sun.
Regarding claim 18, Jeon as modified by Moon, Jo, Kim, and Ko-270, teaches claim 17 from which claim 18 depends. Jeon, Moon, and Ko-270 do not expressly disclose the limitations of claim 18.
However, in an analogous art, Jo teaches
(Previously Presented) The display device of claim 17, wherein
the first vertical power line (ELVDD in DR1 direction) is on the substrate (SUB) (110) , and
the first horizontal power line (ELVDD in DR2 direction) is on the second insulating layer.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the power line structure as taught by Jo into Jeon, Moon, and Ko-270.
An ordinary artisan would have been motivated to use the known technique of Jo in the manner set forth above to produce the predictable result as stated above in claim 17.
Jeon, Moon, Ko-270, and Jo do not expressly disclose the other limitations of claim 18.
However, in an analogous art, Sun teaches
the second insulating layer (500 – [0149] – “second conductive layer 600 between the second insulating layer 500”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive layer structure as taught by Sun into Jeon, Moon, Ko-270, and Jo.
An ordinary artisan would have been motivated to use the known technique of Sun in the manner set forth above to produce the predictable result [0003] – “to achieve a high-resolution design in a display panel” by using separate conductive layers to allow for more complex circuitry within a compact footprint.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 19, Jeon as modified by Moon, Jo, Kim, Ko-270, and Sun, teaches claim 18 from which claim 20 depends. Jeon further teaches
(Previously Presented) The display device of claim 18, wherein, in a
plan view, the first transistor (T1), the second transistor (T2 – Fig. 4 – [0085] – “first electrode of the second thin film transistor (T2)”),
and the third transistor (T3 – [0086] – “third thin film transistor (T3)”) are at a side of the storage capacitor (Cst – Fig. 5 shows this).
Regarding claim 20, Jeon as modified by Moon, Jo, Kim, Ko-270, and Sun, teaches claim 18 from which claim 20 depends. Jeon further teaches
(Previously Presented) The display device of claim 18, wherein, in a
plan view, the storage capacitor (Cst) is between the initialization power line (INL – Fig. 5 – [0086] – “initialization voltage line (INL)”) and the first vertical power line (VDL – this is a vertical power line – Fig. 5 shows this).
Pertinent Art
For the benefits of the Applicant, US 20180151649 A1 is cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the capacitor and transistor locations.
Conclusion
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights