DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (KR 20220147771 A – hereinafter Jeon) in view of Ko et al. (KR 20210016003 A – hereinafter Ko).
Regarding independent claim 1, Jeon teaches:
A display device (1 – Fig. 1 – [0043] – “display device (1)”) comprising:
first (PX1 – Fig. 5 annotated, see below – [0056] – “first pixel (PX1)”), second
(PX2 – Fig. 5 annotated, see below – [0056] – “first pixel (PX2)”), and third sub-pixels (PX3 – Fig. 5 annotated, see below – [0056] – “first pixel (PX3)”) adjacent to each other, each of the first (PX1), second (PX2), and third sub-pixels (PX3) including a storage capacitor (Cst – Fig. 5 – [0089] – “storage capacitor (Cst)”);
a scan line (SL – Fig 5 – [0085] – “scan line (SL)”) selectively transferring a scan signal ([0085] – “scan signal is supplied to the scan line (SL)”) and a control signal ([0087] – “third thin film transistor (T3) may be turned on according to a signal received through a scan line (SL) to initialize a pixel electrode of an organic light emitting diode (OLED)” – this describes a control signal, hereinafter ‘CS’) to each of the first to third sub-pixels (PX1-PX3), the scan line (SL) extending in a first direction (x – Fig. 5 – [0046] – “x direction”);
a data line (DL – fig. 5 – [0085] – “data line (DL)”) transferring a data signal ([0092] – “data signal”) to each of the first to third sub-pixels (PX1-PX3), the data line (DL) extending in a second direction (y – Fig. 5 – [0046] – “y direction”) intersecting the first direction (x – Fig. 5 shows this); and
a first power line (VDL – Fig. 5 – [0084] – “driving voltage line (VDL)”) electrically connected to each of the first, second, and third sub-pixels (PX1-PX3 – [0084] – “first electrode of the first thin film transistor (T1) is connected to a driving voltage line (VDL) that supplies a driving power voltage (ELVDD), and a second electrode can be connected to a pixel electrode of an organic light emitting diode (OLED)” – this describes an electrical connection to each pixel), and the first power line (VDL) being supplied with a first driving power voltage (ELVDD – ([0084] – “driving power voltage (ELVDD)”),
wherein the first power line is disposed between the storage capacitor and the data line.
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Jeon does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Ko teaches
wherein the first power line (26 – Fig. 3 – [0040] – “driving voltage line (26)”) is disposed between ([0014] – “a driving voltage line disposed between the capacitor and the data line”) the storage capacitor (Cst – Fig. 3 – [0038] – “storage capacitor (Cst)”) and the data line (16 – Fig. 3 – [0040] – “data line (16)”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first power line position as taught by Ko into Jeon.
An ordinary artisan would have been motivated to use the known technique of Ko in the manner set forth above to produce the predictable result of [0004] – “a driving voltage line in a mesh structure while suppressing crosstalk defects caused by coupling between a data line and a capacitor, and an organic light-emitting display including the same.”
Claims 2-7, 13-14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Ko, Chen (US 20210226156 A1 – hereinafter Chen), Choi et al. (US 20170358603 A1 – hereinafter Choi), and Sun et al. (US 20210408153 A1 – hereinafter Sun).
Regarding claim 2, Jeon as modified by Ko, teaches claim 1 from which claim 2 depends. Jeon further teaches
further comprising: a substrate;
a first insulating layer, a second insulating layer, a third insulating layer, and a
fourth insulating layer, sequentially disposed on the substrate;
a second power line (VSL – Fig. 5 – [0090] – “The counter electrode of the organic light-emitting diode (OLED) can be connected to a common voltage line (VSL) that provides a common power supply voltage (ELVSS)”) supplied with a second driving power voltage (ELVSS – [0090] – “common power supply voltage (ELVSS)”), which is different from the first driving power voltage (ELVDD); and
an initialization power line (INL – Fig. 5 – [0086] – “initialization voltage line (INL)”) supplied with an initialization power voltage ([0094] – “initialization voltage line (INL) transmits an initialization voltage”), wherein
the first power line includes:
a first vertical power line formed as a first conductive layer disposed on the substrate, and
a first horizontal power line formed as a second conductive layer disposed on the second insulating layer, and
in a plan view, the first vertical power line is disposed between the storage capacitor of each of the first, second, and third sub-pixels (PX1-PX3) and the data line.
Jeon does not expressly disclose the other limitations of claim 2.
However, in an analogous art, Ko teaches
in a plan view, the first vertical power line (26) is disposed between
([0014] – “a driving voltage line disposed between the capacitor and the data line”) the
storage capacitor (Cst) of each of the first, second, and third sub-pixels and the data line (16).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first vertical power line position as taught by Ko into Jeon.
An ordinary artisan would have been motivated to use the known technique of Ko in the manner set forth above to produce the predictable result of as stated above in claim 1.
Jeon and Ko do not expressly disclose the other limitations of claim 2.
However, in an analogous art, Chen teaches
a substrate (10 – Fig. 3 – [0036] – “substrate 10”);
a first insulating layer (24 – Fig. 3 – [0047] – “insulating layer 24”), a second
insulating layer (23 – Fig. 3 – [0047] – “insulating layer 23”), a third insulating layer (22 – Fig. 3 – [0047] – “insulating layer 22”), and a fourth insulating layer (21 – Fig. 3 – [0047] – “insulating layer 21”), sequentially disposed on the substrate (10 – [0047] – “stacked on the substrate 10 in sequential” – fig. 3 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the substrate and insulating layer structure as taught by Chen into Jeon and Ko.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable result of [0047] – “packaging effect can be improved.” Packaging effect plays a vital role in thermal packaging and electromagnetic interference shielding.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Jeon, Ko, and Chen do not expressly disclose the other limitations of claim 2.
However, in an analogous art, Choi teaches
the first power line (VDD – [0047] – “first power line VDD”) includes:
a first vertical power line ([0015] – “first vertical power line”),
a first horizontal power line (VDDH – [0046] – “horizontal high power line VDDH”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first power line structure as taught by Choi into Jeon, Ko, and Chen.
An ordinary artisan would have been motivated to use the known technique of Choi in the manner set forth above to produce the predictable result of [0005] – “a display apparatus with an improved arrangement of its fan-out lines, which enables the peripheral area of its non-display area to be reduced in size.” The fan-out lines are associated with the power lines.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Jeon, Ko, Chen, and Choi do not expressly disclose the other limitations of claim 2.
However, in an analogous art, Sun teaches
a first vertical power line formed as a first conductive layer (200 – [0115] – “first conductive layer 200 disposed on a substrate 100”) disposed on the substrate (100 – [0115] – “first conductive layer 200 disposed on a substrate 100”), and
a first horizontal power line formed as a second conductive layer (600 – [0149] – “second conductive layer 600 between the second insulating layer 500”) disposed on the second insulating layer (500 – [0149] – “second conductive layer 600 between the second insulating layer 500”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive layer structure as taught by Sun into Jeon, Ko, Chen, and Choi.
An ordinary artisan would have been motivated to use the known technique of Sun in the manner set forth above to produce the predictable result [0003] – “to achieve a high-resolution design in a display panel” by using separate conductive layers to allow for more complex circuitry within a compact footprint.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 3, Jeon as modified by Ko, Chen, Choi, and Sun, teaches claim 2 from which claim 3 depends. Jeon further teaches
wherein each of the first, second, and third sub-pixels includes (PX1-
PX3):
a light emitting element (OLED – Fig. 6 – [0051] – “light emitting unit (10) may include a plurality of organic light emitting diodes (OLEDs) as light emitting elements that generate light”);
a first transistor (T1 – Fig. 4 – [0084] – “first electrode of the first thin film transistor (T1) is connected to a driving voltage line (VDL) that supplies a driving power voltage (ELVDD), and a second electrode can be connected to a pixel electrode of an organic light emitting diode (OLED)”) controlling a current of the light emitting element (OLED);
a second transistor (T2 – Fig. 4 – [0085] – “first electrode of the second thin film transistor (T2) can be connected to the data line (DL), and the second electrode can be connected to the first node (N1)”) connected between the data line (DL – Fig. 4 – [0085] – “first electrode of the second thin film transistor (T2) can be connected to the data line (DL), and the second electrode can be connected to the first node (N1)”) and a gate electrode (G1 – [0105] – “first thin film transistor (T1) may include a first semiconductor layer (A1) and a first gate electrode (G1)”}, {[0085] – “first electrode of the second thin film transistor (T2) can be connected to the data line (DL), and the second electrode can be connected to the first node (N1)”}, {[0084] – “gate electrode of the first thin film transistor (T1) can be connected to the first node (N1)”} – Fig. 4 shows this) of the first transistor (T1), the second transistor (T2) being turned on by the scan signal ([0085] – “second thin film transistor (T2) can be turned on when a scan signal is supplied to the scan line (SL)” – hereinafter ‘SSL’);
a third transistor (T3 – [0086] – “third thin film transistor (T3) can be connected to the second node (N2), and the second electrode can be connected to the initialization voltage line (INL)”) connected between the initialization power line (INL) and a source electrode of the first transistor (T1 – Fig. 4 shows this), the third transistor (T3) being turned on by the control signal (CS); and
the storage capacitor (Cst – Fig. 4 – [0089] – “storage capacitor (Cst)”) including:
a lower electrode electrically (CE1 – [[0012] – “second capacitor plate (CE2) is positioned above the first capacitor plate (CE1)”) connected to the gate electrode (G1 – [0112] – “first capacitor plate (CE1) can be formed integrally with the first gate electrode (G1)”) of the first transistor (T1) and a source electrode ([0083] – “Each thin film transistor has a first electrode and a second electrode, and depending on the type of thin film transistor, the first electrode may be one of a source electrode and a drain electrode, and the second electrode may be the other of the source electrode and the drain electrode.” – hereinafter ‘SE2’) of the second transistor (T2 – Fig. 4 shows this), and
an upper electrode (CE2 – [0112] – “second capacitor plate (CE2) is positioned above the first capacitor plate (CE1)”) electrically connected to the source electrode of the first transistor (T1) and a source electrode of the third transistor (T3 – Fig. 4 shows this).
Regarding claim 4, Jeon as modified by Ko, Chen, Choi, and Sun, teaches claim 3 from which claim 4 depends. Jeon further teaches
wherein the first, second, and third transistors (T1-T3) are disposed
at a side of the storage capacitor (Cst – Fig. 5 shows this).
Regarding claim 5, Jeon as modified by Ko, Chen, Choi, and Sun, teaches claim 3 from which claim 5 depends. Jeon further teaches
in a plan view, the storage capacitor (Cst) is disposed between the
second vertical power line (VSL – this is a vertical power line) and the first vertical power line (VDL – this is a vertical power line, Fig. 5 shows this).
Regarding claim 6, Jeon as modified by Ko, Chen, Choi, and Sun, teaches claim 5 from which claim 6 depends. Jeon further teaches
wherein, in a plan view, the initialization power line (INL) is disposed
between the first vertical power line (VDL – this is a vertical power line) and the data line (DL, Fig. 5 shows this).
Regarding claim 7, Jeon as modified by Ko, Chen, Choi, and Sun, teaches claim 6 from which claim 7 depends. Jeon further teaches
wherein the gate electrode (G1) of the first transistor (T1) of each of
the first (PX1), second (PX2), and third sub-pixels (PX3) is disposed between the storage capacitor (Cst) and the first vertical power line (VDL – this is a vertical power line, Fig. 5 shows this).
Regarding claim 13, Jeon as modified by Ko, Chen, Choi, and Sun, teaches claim 5 from which claim 13 depends. Jeon further teaches
wherein, in a plan view, the initialization power line (INL) is disposed
between the second vertical power line (VSL – this is a vertical power line) and the storage capacitor (Cst – Fig. 5 shows this).
Regarding claim 14, Jeon as modified by Ko, Chen, Choi, and Sun, teaches claim 13 from which claim 14 depends. Jeon further teaches
wherein
in a plan view, the initialization power line (INL) is disposed at a first side of the storage capacitor (Cst), and
in a plan view, the first vertical power line (VDL – this is a vertical power line) is disposed at a second side of the storage capacitor (Cst – Fig. 5 shows this).
Regarding claim 16, Jeon as modified by Ko, Chen, Choi, and Sun, teaches claim 3 from which claim 16 depends. Jeon further teaches
wherein each of the first, second, and third sub-pixels (PX1-PX3)
further includes:
an encapsulation layer (300 – Fig. 6 – [0148] – “encapsulating layer (300)”) disposed over the light emitting element (OLED – Fig. 6 shows this);
a color filter layer (500 – [0150] – “Although not shown in FIG. 6, the color conversion-transmitting layer (500, see FIG. 2) described above with reference to FIG. 2 may be placed on the counter electrode (230) of the organic light-emitting diode (OLED)” – this is a color filter) disposed on the encapsulation layer (300); and
an overcoat layer (600 – [0150] – “Additionally, the color filter layer (600) can be placed on the color conversion-transmitting layer (500)” – this is an overcoat layer) disposed over the color filter layer (500).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Ko, Chen, Choi, Sun, and Jo et al. (US 20200185489 A1 – hereinafter Jo).
Regarding claim 8, Jeon as modified by Ko, Chen, Choi, and Sun, teaches claim 3 from which claim 8 depends. Jeon, Ko, Chen, Choi, and Sun do not expressly disclose the limitations of claim 8.
However, in an analogous art, Jo teaches
wherein
the lower electrode (111 – Fig. 5 – [0050] – “lower patterns 111 as a first
conductive layer may be disposed on the substrate 110”) is disposed on the substrate (110 – Fig. 5 – [0050] – “the substrate 110”), and
the upper electrode (155 – Fig. 5 – [0077] – “driving gate electrode 155 may
overlap most of the lower pattern 111 with the buffer layer 120 and the first insulating layer 140 therebetween to form the capacitor Cst1”) is disposed on the first insulating layer (140 – Fig. 5 – [0077] – “driving gate electrode 155 may overlap most of the lower pattern 111 with the buffer layer 120 and the first insulating layer 140 therebetween to form the capacitor Cst1”) to overlap the lower electrode (111) with the first insulating layer (140) interposed between the lower electrode (111) and the upper electrode (155 – Fig. 5 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the lower and upper electrode structure as taught by Jo into Jeon, Ko, Chen, Choi, and Sun.
An ordinary artisan would have been motivated to use the known technique of Jo in the manner set forth above to produce the predictable result of [0004] – “the light emitting diode display has characteristics such as low power consumption, high luminance, and high response speed.”
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Ko, Chen, Choi, Sun, Jo, and Lee et al. (US 20230363215 A1 – hereinafter Lee).
Regarding claim 9, Jeon as modified by Ko, Chen, Choi, Sun, and Jo, teaches claim 8 from which claim 9 depends. Jeon, Ko, Chen, Choi, Sun, and Jo do not expressly disclose the limitations of claim 9.
However, in an analogous art, Lee teaches
wherein the upper electrode (UE) (650B – Fig. 6A – [0169] – “second electrode
650B of the storage capacitor formed by imparting conductivity to the same material as the first oxide semiconductor pattern 474 on the same layer as the first oxide semiconductor pattern 474”) and an active pattern layer of each of the first (474 – Fig. 6A – [0169] – “second electrode 650B of the storage capacitor formed by imparting conductivity to the same material as the first oxide semiconductor pattern 474 on the same layer as the first oxide semiconductor pattern 474”), second (this is a repetition of the first transistor), and third (this is a repetition of the first transistor) transistors are disposed on a same layer (Fig. 6A – [0169] – “second electrode 650B of the storage capacitor formed by imparting conductivity to the same material as the first oxide semiconductor pattern 474 on the same layer as the first oxide semiconductor pattern 474”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the upper electrode and transistor active pattern structure as taught by Lee into Jeon, Ko, Chen, Choi, Sun, and Jo.
An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable result [0006] – “to provide an organic light emitting display apparatus having a capacitor structure capable of providing a capacitance value of a predetermined capacity or more in a subpixel while realizing high resolution.”
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Ko, Chen, Choi, Sun, Jo, Lee, Hwang et al. (US 20200006401 A1 – hereinafter Hwang), and Yuan et al. (US 20240268148 A1 – hereinafter Yuan).
Regarding claim 10, Jeon as modified by Ko, Chen, Choi, Sun, Jo, and Lee, teaches claim 9 from which claim 10 depends. Jeon, Ko, Chen, Choi, Sun, Jo, and Lee do not expressly disclose the limitations of claim 10.
However, in an analogous art, Hwang teaches
wherein the upper electrode (Cse21 – Fig. 9 – [0138] – “capacitor Cse2 is
formed by the first electrode Cse21 which is the first electrode E11 of the first transistor T1”) is integral with the source electrode of the first transistor ([0070] – ‘’ electrodes E11, E21, E31, E41, E51, E61, and E71 and second electrodes E12, E22, E32, E42, E52, E62, and E72 of FIG. 2 may be a source electrode”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the upper electrode and drive transistor source electrode structure as taught by Hwang into Jeon, Ko, Chen, Choi, Sun, Jo, and Lee.
An ordinary artisan would have been motivated to use the known technique of Hwang in the manner set forth above to produce the predictable result of [0006] – “Devices constructed according to exemplary implementations of the invention are capable of reducing or preventing color smear phenomenon by compensating for hysteresis. For example, compensation capacitors in the pixel driving circuits of the display may compensate for hysteresis by voltage stabilization.”
Jeon, Ko, Chen, Choi, Sun, Jo, Lee, and Hwang do not expressly disclose the other limitations of claim 10.
However, in an analogous art, Yuan teaches
wherein the upper electrode is integral with the source electrode of the first
transistor and the source electrode of the third transistor ([0068] – “active layer pattern 122 of the first initialization transistor T2 and the active layer pattern 121 of the driving transistor T1 are both in direct contact with and electrically connected to the first electrode plate C1 of the storage capacitor Cst, so that the active layer pattern 122 of the first initialization transistor T2 is electrically connected to the active layer pattern 121 of the driving transistor T1 through the first electrode plate C1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the upper electrode and initialization transistor source electrode structure as taught by Yuan into Jeon, Ko, Chen, Choi, Sun, Jo, Lee, and Hwang. The electrode plate C1 of Yuan can be substituted with a semiconductor material as taught by Hwang thus making the source electrodes of the two transistors of Yuan integral.
An ordinary artisan would have been motivated to use the known technique of Yuan in the manner set forth above to produce the predictable result of [0003] – “A display panel with high resolution and high pixel density has become an important direction for the development of the display panel due to its dearer picture display effect.”
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Ko, Chen, Choi, Sun, and Moon et al. (US 20200119115 A1 – hereinafter Moon).
Regarding claim 11, Jeon as modified by Ko, Chen, Choi, and Sun, teaches claim 3 from which claim 11 depends. Jeon, Ko, Chen, and Choi do not expressly disclose the limitations of claim 11.
However, in an analogous art, Sun teaches
a third conductive layer ([0115] - “a first conductive layer 200 disposed on a substrate 100, a first insulating layer 300 above the first conductive layer 200, and an anode 400 on the first insulating layer 300” – 400 can be considered a third conductive layer).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive layer structure as taught by Sun into Jeon, Ko, Chen, and Choi.
An ordinary artisan would have been motivated to use the known technique of Sun in the manner set forth above to produce the predictable result [0003] – “to achieve a high-resolution design in a display panel” by using separate conductive layers to allow for more complex circuitry within a compact footprint.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Jeon, Ko, Chen, Choi, and Sun do not expressly disclose the other limitations of claim 11.
However, in an analogous art, Moon teaches
wherein the light emitting element (PX1– Fig. 9 – [0098] – “first pixel PX1” – this is a light emitting element) includes:
a first electrode (320R – Fig. 9 – [0099] – “first pixel electrode 320R”) formed
as a third conductive layer disposed on the fourth insulating layer (107 – Fig. 9 – [0089] – “insulating layer 107”);
a light emitting layer (312 – Fig. 9 – [0099] – “emission layer 312”) disposed on the first electrode (320R); and
a second electrode (330 – Fig. 9 – [0101] – “opposite electrode 330”) disposed on the light emitting layer (312).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the light emitting element structure as taught by Moon into Jeon, Ko, Chen, Choi, and Sun.
An ordinary artisan would have been motivated to use the known technique of Moon in the manner set forth above to produce the predictable result of [0004] – “display apparatuses having high resolution.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 12, Jeon as modified by Ko, Chen, Choi, Sun, and Moon, teaches claim 11 from which claim 12 depends. Jeon, Ko, Chen, Choi, and Sun do not expressly disclose the limitations of claim 11.
However, in an analogous art, Moon teaches
wherein the first electrode (320R) is electrically connected to the source
electrode of the first transistor (SA11 – [0065] – “first driving source area SA11” – this is shown as A11 in Fig. 9) through a contact part (320a – Fig. 9 annotated, see below – [0090] – “pixel electrodes 320R, 320G, and 320B are connected to the first, second, and third upper electrode layers 161, 162, and 163 via a contact hole 320a”) passing through the second to fourth insulating layers (Fig. 9 shows {103 – [0069] – “insulating layer 103”}, {105 – [0078] – “insulating layer 105”}, and {107}).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the light emitting element structure as taught by Moon into Jeon, Ko, Chen, Choi, and Sun.
An ordinary artisan would have been motivated to use the known technique of Moon in the manner set forth above to produce the predictable result as stated above in claim 11.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Ko, Chen, Choi, Sun, and Yuan.
Regarding claim 15, Jeon as modified by Ko, Chen, Choi, and Sun, teaches claim 14 from which claim 15 depends. Jeon, Ko, Chen, Choi, and Sun do not expressly disclose the limitations of claim 15.
However, in an analogous art, Yuan teaches
wherein
in a plan view, the third transistor (T2 – Fig. 3 – [0066] – “initialization
transistor T2”) among the first, second, and third transistors is disposed at the first side of the storage capacitor (Cst – Fig. 4 – [0066] – “storage capacitor Cst”), and
in a plan view, the first (T1 – Fig. 3 – [0066] – “driving transistor T1”) and second (T3 – Fig. 3 – [0074] – “data writing transistor T3”) transistors among the first, second, and third transistors are disposed at the second side of the storage capacitor (Cst – Fig. 4 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to substitute the transistor and capacitor locations as taught by Yuan into Jeon, Ko, Chen, Choi, and Sun.
An ordinary artisan would have been motivated to use the known technique of Yuan in the manner set forth above to produce the predictable result of [0003] – “A display panel with high resolution and high pixel density has become an important direction for the development of the display panel due to its dearer picture display effect.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Moon.
Regarding independent claim 17, Jeon teaches:
A display device (1 – Fig. 1 – [0043] – “display device (1)”) comprising:
a substrate;
first, second, third, and fourth insulating layers sequentially stacked on the
substrate;
first, second, and third sub-pixels each including:
a pixel circuit including a storage capacitor and first, second, and third transistors, which are disposed on the substrate, and
a light emitting element electrically connected to the pixel circuit;
a scan line disposed on the substrate, the scan line selectively transferring a scan signal and a control signal to each of the first, second, and third sub-pixels;
a data line transferring a data signal to each of the first, second, and third sub-pixels;
a first power line supplied with a first power voltage;
a second power line (VSL – Fig. 5 – [0090] – “The counter electrode of the organic light-emitting diode (OLED) can be connected to a common voltage line (VSL) that provides a common power supply voltage (ELVSS)”) supplied with a second driving power voltage (ELVSS – [0090] – “common power supply voltage (ELVSS)”), which is different from the first power voltage (ELVDD – ([0084] – “driving power voltage (ELVDD)”); and
an initialization power line (INL – Fig. 5 – [0086] – “initialization voltage line (INL)”) supplied with an initialization power voltage ([0094] – “initialization voltage line (INL) transmits an initialization voltage”), which is different from the first (ELVDD) and second (ELVSS) power voltages,
wherein a gate electrode (G1 – [0105] – “first thin film transistor (T1) may include a first semiconductor layer (A1) and a first gate electrode (G1)”) of the first transistor (T1 – [0105] – “first thin film transistor (T1)”) is disposed between the storage capacitor (Cst – Fig. 5 – [0089] – “storage capacitor (Cst)”) and the first power line (VDL – Fig. 5 – [0084] – “driving voltage line (VDL)” – Fig. 5 shows this).
Jeon does not expressly disclose the other limitations of claim 17.
However, in an analogous art, Moon teaches
a substrate (100 – Fig. 9 – [0040] – “substrate 100”);
first (101 – Fig. 9 – [0061] – “buffer layer 101”), second (103 – Fig. 9 – [0069] –
“insulating layer 103”), third (105 – Fig. 9 – [0078] – “insulating layer 105”), and fourth (moon (107 – Fig. 9 – [0089] – “insulating layer 107”) insulating layers sequentially stacked on the substrate (100 – Fig. 9 shows this);
first (PX1 – Fig. 4 – [0054] – “Each of the first through third pixels PX1, PX2, and PX3 may include one or more TFT and a storage capacitor”), second (PX2 – Fig. 4 – [0054] – “Each of the first through third pixels PX1, PX2, and PX3 may include one or more TFT and a storage capacitor”), and third sub-pixels (PX3 – Fig. 4 – [0054] – “Each of the first through third pixels PX1, PX2, and PX3 may include one or more TFT and a storage capacitor”) each including:
a pixel circuit (PC – Fig. 3 – [0048] – “pixel circuit PC of FIG. 3 may include the first TFT T1, the second TFT T2, a third TFT T3, and the storage capacitor Cst”) including a storage capacitor (Cst – Fig. 3 – [0048] – “pixel circuit PC of FIG. 3 may include the first TFT T1, the second TFT T2, a third TFT T3, and the storage capacitor Cst”) and first (T1 – Fig. 3 – [0048] – “pixel circuit PC of FIG. 3 may include the first TFT T1, the second TFT T2, a third TFT T3, and the storage capacitor Cst”), second (T2 – Fig. 3 – [0048] – “pixel circuit PC of FIG. 3 may include the first TFT T1, the second TFT T2, a third TFT T3, and the storage capacitor Cst”), and third transistors (T3 – Fig. 3 – [0048] – “pixel circuit PC of FIG. 3 may include the first TFT T1, the second TFT T2, a third TFT T3, and the storage capacitor Cst”), which are disposed on the substrate (100), and
a light emitting element (OLED – Fig. 2 – [0041] – “organic light-emitting devices (OLEDs)”) electrically connected to the pixel circuit (PC);
a scan line (SL – Fig. 3 – [0046] – “scan line SL”) disposed on the substrate (100), the scan line (SL) selectively transferring a scan signal ([0057] – “pixel unit PXU includes a scan line 121 and a sensing line 123, which intersect with the data wiring unit 150, apply each of a scan signal and a sensing signal”) and a control signal ({[0057] – “sensing signal”}, {SSL – Fig. 3 – [0050] – “third TFT T3 is a sensing TFT and includes a gate electrode connected to a sensing line SSL”} – this is a control signal) to each of the first (PX1), second (PX2), and third sub-pixels (PX3);
a data line (DL – Fig. 3 – [0046] – “data line DL”) transferring a data signal ([0024] – “first data line for transmitting a data signal to the first pixel, a second data line for transmitting a data signal to the second pixel, and a third data line for transmitting a data signal to the third pixel”) to each of the first (PX1), second (PX2), and third sub-pixels (PX3);
a first power line (PL– [0046] – “driving voltage line PL”) supplied with a first power voltage (ELVDD – Fig. 3 – [0046] – “first power supply voltage ELVDD”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the light emitting element structure as taught by Moon into Jeon.
An ordinary artisan would have been motivated to use the known technique of Moon in the manner set forth above to produce the predictable result as stated above in claim 11.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Moon, Ko, Choi, and Sun.
Regarding claim 18, Jeon as modified by Moon, teaches claim 17 from which claim 18 depends. Jeon and Moon do not expressly disclose the limitations of claim 18.
However, in an analogous art, Ko teaches
the first vertical power line (26 – Fig. 3 – [0040] – “driving voltage line (26)” –
this is a vertical power line) is disposed between ([0014] – “a driving voltage line disposed between the capacitor and the data line”) the storage capacitor (Cst – Fig. 3 – [0038] – “storage capacitor (Cst)”) and the data line (16 – Fig. 3 – [0040] – “data line (16)”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first power line position as taught by Ko into Jeon and Moon.
An ordinary artisan would have been motivated to use the known technique of Ko in the manner set forth above to produce the predictable result of [0004] – “a driving voltage line in a mesh structure while suppressing crosstalk defects caused by coupling between a data line and a capacitor, and an organic light-emitting display including the same.”
Jeon, Moon, and Ko do not expressly disclose the other limitations of claim 18.
However, in an analogous art, Choi teaches
the first power line (VDD – [0047] – “first power line VDD”) includes:
a first vertical power line ([0015] – “first vertical power line”) disposed on the substrate (100 – [0046] – “base substrate 100”), and
a first horizontal power line (VDDH – [0046] – “horizontal high power line VDDH”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first power line structure as taught by Choi into Jeon, Moon, and Ko.
An ordinary artisan would have been motivated to use the known technique of Choi in the manner set forth above to produce the predictable result of [0005] – “a display apparatus with an improved arrangement of its fan-out lines, which enables the peripheral area of its non-display area to be reduced in size.” The fan-out lines are associated with the power lines.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Jeon, Moon, Ko, and Choi do not expressly disclose the other limitations of claim 18.
However, in an analogous art, Sun teaches
disposed on the second insulating layer (500 – [0149] – “second conductive layer 600 between the second insulating layer 500”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second insulating layer structure as taught by Sun into Jeon, Moon, Ko, and Choi.
An ordinary artisan would have been motivated to use the known technique of Sun in the manner set forth above to produce the predictable result [0003] – “to achieve a high-resolution design in a display panel.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 19, Jeon as modified by Moon, Ko, Choi, and Sun, teaches claim 18 from which claim 19 depends. Jeon further teaches
wherein, in a plan view, the first (T1), second (T2 – Fig. 4 – [0085] –
“first electrode of the second thin film transistor (T2)”), and third (T3 – [0086] – “third thin film transistor (T3)”) transistors are disposed at a side of the storage capacitor (Cst – Fig. 5 shows this).
Regarding claim 20, Jeon as modified by Moon, Ko, Choi, and Sun, teaches claim 18 from which claim 20 depends. Jeon further teaches
wherein, in a plan view, the storage capacitor (Cst) is disposed
between the initialization power line (INL – Fig. 5 – [0086] – “initialization voltage line (INL)”) and the first vertical power line (VDL – this is a vertical power line – Fig. 5 shows this).
Pertinent Art
For the benefits of the Applicant, US 20180151649 A1 is cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the capacitor and transistor locations.
Conclusion
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897