Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restriction
Applicant’s election without traverse of Species IA, Species IIA and Species IIIA in the reply filed on 2 February, 2026 is acknowledged.
Claims 4 and 17 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2 Feb 2026. Claim 4 was withdrawn by applicant in filed reply. Claim 17 is withdrawn because it speaks to Fig. 10, which is part of non-elected species IB. Claim 17 recites the limitation “wherein the first contact and the second contact overlap the device isolation layer and the extension portion in the second direction.” This means that the first and second contact must be disposed on the branch active pattern, the distinguishing feature of species IB, as in claim 4, rather than the disposed on the central active pattern as in claim 3 and Species IA.
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Foreign Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection because a translation of said application has not been made of record in accordance with 37 CFR 1.55. When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216.
Objections to the Drawings
New corrected drawings in compliance with 37 CFR 1.121(d) are required in this application because Fig. 15 does not show how the structure of the semiconductor device, which is described with reference to FIGS. 3 to 14, may be disposed in the peripheral circuit region PERI. Applicant is advised to employ the services of a competent patent draftsperson outside the Office, as the U.S. Patent and Trademark Office no longer prepares new drawings. The corrected drawings are required in reply to the Office action to avoid abandonment of the application. The requirement for corrected drawings will not be held in abeyance.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 7-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yi et al., (US Patent 7078775), hereinafter referred to as Yi,
Regarding claim 1, Yi teaches a semiconductor device, comprising: an active region (Yi, 620, Fig 6A, Col 5, lines 58-63); a first source/drain region on the active region (Yi, 640, Fig 6A, Col 5, lines 52-55); a first contact electrically connected to the first source/drain region (Yi, Fig 6A, see below); a second source/drain region spaced apart from the first source/drain region, on the active region (Yi, 650, Fig. 6B Col 5, lines 58-63); a first gate electrode on the active region, said first gate electrode including a first ring portion that surrounds the first contact (Yi, 600, Fig. 6A, Col. 5, lines 46-50); and a second contact, which extends outside the first ring portion relative to the first contact, and is electrically connected to the second source/drain region (Yi, Fig. 6A, see diagram below).
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Regarding claim 7, Yi teaches the semiconductor device of Claim 1, further comprising: a third source/drain region (Yi, Fig 6A, see below), which is spaced apart from the first source/drain region and the second source/drain region, and is disposed on the active region; and a third contact on the third source/drain region (Yi, Fig 6A, see below); wherein the third contact extends external to the first ring portion; and wherein the first gate electrode further includes an extension portion, which is connected to the first ring portion, and extends between the second contact and the third contact (Yi, Fig. 6A, see below).
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Regarding claim 8, Yi teaches the semiconductor device of Claim 1, wherein the first ring portion has a closed ring shape that surrounds the first contact (Yi, 600, Fig 6A, see above).
Regarding claim 9, Yi teaches the semiconductor device of Claim 1, further comprising: a fourth source/drain region disposed on the active region (Yi, Fig 6A, see below) and a fourth contact on the fourth source/drain region (Yi, Fig 6A, see below);
wherein the fourth contact extends outside the first ring portion (Yi, Fig 6A, see below);
and wherein the first contact, the second contact and the fourth contact are arranged in a zigzag layout pattern (Yi, Fig 6A, see below).
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Regarding claim 10, Yi teaches the semiconductor device of Claim 1, further comprising: a fifth source/drain region disposed on the active region (Yi, Fig. 6A);
and a fifth contact extending on the fifth source/drain region (Yi, Fig. 6A); wherein the first gate electrode further includes a second ring portion, which extends on the active region and surrounds the fifth contact (Yi, 600, Fig. 6A); and wherein the first ring portion and the second ring portion are electrically connected to each other (Yi, Fig. 6A, see below).
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Regarding claim 11, Yi teaches the semiconductor device of Claim 1, wherein the first ring portion has a rhombus layout shape (Yi, 600, Fig. 6A, the ring portions of electrode 600 are a rhombus shape).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-3 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Yi as applied to claim 1 above, and further in view of Noro et. al. (US Pub. 20200202954) hereinafter referred to as Noro.
Regarding claim 2, Yi teaches the semiconductor device of claim 1,
but does not teach wherein the active region is defined by a device isolation layer,
and includes: (i) a central active pattern extended in a first direction, and (ii) a plurality of branch active patterns, which extend from the central active pattern in a second direction that crosses the first direction, and are spaced apart from each other in the first direction; wherein the device isolation layer extends in the second direction, and between the plurality of branch active patterns; and wherein the first source/drain region and the first contact are disposed on the central active pattern.
However, Noro teaches, wherein the active region is defined by a device isolation layer Noro, 101, 112, Fig 9A/9B paras. 76, 96 ), and includes: (i) a central active pattern extended in a first direction (Noro, 101, Fig. 8, para 76), and (ii) a plurality of branch active patterns, which extend from the central active pattern in a second direction that crosses the first direction, and are spaced apart from each other in the first direction (Noro, 115, Fig. 8, para. 97); wherein the device isolation layer extends in the second direction, and between the plurality of branch active patterns (Noro, 112, Fig. 9A/9B).
and wherein the first source/drain region and the first contact are disposed on the central active pattern (Noro, 101, Fig 8, see below).
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Therefore it would have been obvious to a person of ordinary skill in the art before the filing date of the invention to combine the teachings of Yi and Noro to create a semiconductor device having a ring shaped electrodes and multiple source/drain regions to lower gate resistances and provide semiconductor devices with enhanced reliability.
Regarding claim 3, modified Yi teaches the semiconductor device of Claim 2, wherein the second source/drain region and the second contact are disposed on the central active pattern (Noro, 116, Fig 8, see diagram above).
Regarding claim 5, modified Yi teaches the semiconductor device of claim 2, wherein the first gate electrode further includes an extension portion, which is connected to the first ring portion and extends in the second direction (Yi, 600, Fig. 6A, shows the extension portion attached to the ring portion of the gate electrode), and wherein the extension portion extends between the plurality of branch active patterns (Noro, 113, Fig. 8, 113 is the gate electrode for Noro), overlaps the device isolation layer (Noro, 112, Fig.9A), and overlaps the second contact (Noro, Fig 8, see diagram above) in the first direction.
Regarding claim 6, modified Yi teaches the semiconductor device of Claim 2, further comprising a second gate electrode (Noro, 120, Fig. 8, para. 100) , which extends in the first direction, is spaced apart from the first gate electrode in the second direction, and crosses the plurality of branch active patterns.
Claims 12-16 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Noro, in view of Yi.
Regarding claim 12, Noro teaches a semiconductor device, comprising: a first active pattern extending in a first direction across a substrate (Noro, 115, Fig.8, para. 97);
a second active pattern extending in the first direction, and adjacent the first active pattern in a second direction crossing the first direction (Noro, 101, Fig. 8, para. 76);
a device isolation layer extending in the first direction (Noro, 112, Fig. 9B, para. 96), and adjacent to the first active pattern in the second direction, and adjacent to the second active pattern in the first direction (Noro, Fig 8, see diagram below); a first source/drain region disposed on the first active pattern (Noro, Fig 8, see diagram below); a second source/drain region disposed on the first active pattern and spaced apart from the first source/drain region in the first direction (Noro, Fig 8, see diagram below); a third source/drain region disposed on the second active pattern and spaced apart from the first source/drain region and the second source/drain region (Noro, Fig 8, see diagram below); a first contact on the first source/drain region (Noro, Fig 8, see diagram below); a second contact on the second source/drain region (Noro, Fig 8, see diagram below); and a third contact on the third source/drain region (Noro, Fig 8, see diagram below).
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Noro does not teach a first gate electrode disposed over the first active pattern and the second active pattern, including a first ring portion surrounding the third contact;
wherein the first source/drain region and the second source/drain region are disposed outside the first ring portion; and wherein the third contact is spaced apart from the first contact in a third direction crossing the first direction and the second direction, and is spaced apart from the second contact in a fourth direction crossing the first direction, the second direction and the third direction.
However, Yi teaches a mesh type gate (Yi, 600, Fig. 6A, Col. 5, lines 46-50) over an active region (Yi, 620, Fig. 6A, Col 5, lines 58-63), which includes a plurality of ring portions surrounding a plurality of contacts (Yi, Fig. 6A, see diagram below), wherein some of the contacts are fully surrounded, and some are not.
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Therefore it would have been obvious to a person of ordinary skill in the art before the filing date of the invention to combine the teachings of Yi and Noro to create a semiconductor device having ring shaped electrodes and multiple source/drain regions to lower gate resistances and provide semiconductor devices with enhanced reliability.
Regarding claim 13, modified Noro teaches he semiconductor device of Claim 12, wherein the first active pattern and the second active pattern are connected to each other (Noro, 101, Fig 9A/B, it is an n type doped region connecting all the active patterns); and wherein a first length in which the first active pattern is extended in the first direction (Noro, 115, Fig. 8) is longer than a second length in which the second active pattern is extended in the first direction (Noro 113, Fig 8, 115 extends further than 113).
Regarding claim 14, modified Noro teaches the semiconductor device of Claim 12, further comprising: a second gate electrode ((Noro, 120, Fig 8, para. 120) spaced apart from the first gate electrode in the first direction), and extending in the second direction; and wherein the second gate electrode crosses the first active pattern and the device isolation layer (Noro, Fig. 9B, shows 120 crossing 115(first active pattern) and 112 (element separation region)) and does not overlap the second active pattern (120 does not cross 101).
Regarding claim 15, modified Noro teaches the semiconductor device of Claim 12, wherein the first gate electrode further includes an extension portion extended from the first ring portion (Yi, 600, Fig. 6A); but does not teach wherein the extension portion extends in the first direction and over the second active pattern and the device isolation layer.
However, the extension portion of Yi does go over the active portion (Yi, 620, Fig 6A). Additionally, Noro teaches a gate electrode (Noro, 113, Fig. 9A, para. 96) that extends over the element separation region (Noro, 112, Fig. 9A).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the extended ring shaped gate of Yi with the element separation region of Noro to create a ring shaped gate electrode that extends over the isolation layer to provide semiconductor devices with enhanced reliability.
Regarding claim 16, modified Noro teaches the semiconductor device of Claim 15, but does not explicitly teach wherein the first contact and the second contact do not overlap the device isolation layer, but overlap the extension portion in the second direction.
However, Noro teaches the first contact and the second contact do not overlap the element separation region (Noro, 112, Fig 8, see diagram above), while Yi teaches the first and second contacts overlap the extension portion in the second direction (Yi, Fig 6A, see above).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the contact placement regarding the element separation region of Noro with the contacts overlapping the extension of Yi to enhance semiconductor reliability.
Regarding claim 18, modified Noro teaches the semiconductor device of claim 15, further comprising: a third active pattern extending adjacent to the second active pattern in the second direction and extending in the first direction (Noro, Fig.8, see diagram below); a fourth source/drain region disposed on the third active pattern (Noro, Fig.8, see diagram below); and a fourth contact extending on the fourth source/drain region((Noro, Fig.8, see diagram below);
wherein the second active pattern is disposed between the first active pattern and the third active pattern in the second direction (Noro, Fig.8, see diagram below); wherein the fourth contact is spaced apart from the first contact in the second direction and is spaced apart from the third contact in the fourth direction (Noro, Fig.8, see diagram below);
and wherein the extension portion extends between the first contact and the fourth contact ((Noro, Fig.8, see diagram below).
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Regarding claim 19, modified Noro teaches the semiconductor device of Claim 12, further comprising: a fourth active pattern adjacent to the first active pattern in the second direction and extended in the first direction (Noro, Fig. 8, see diagram above); a fifth source/drain region disposed on the fourth active pattern; and a fifth contact on the fifth source/drain region ((Noro, Fig. 8, see diagram above);wherein the first gate electrode further includes a second ring portion surrounding the fifth contact (Yi, Fig. 6A, see diagram below);
wherein the first ring portion and the second ring portion are connected to each other (Yi, Fig 6A, see below); wherein the first gate electrode has a first width in the second direction between the third contact and the fifth contact (Yi, Fig. 6A, see diagram below, W1) and has a second width in the third direction between the first contact and the third contact ((Yi, Fig. 6A, see diagram below, W2); and wherein the first width is greater than the second width (Yi, Fig. 6A, see diagram below, W1 is longer than W2).
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Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al, (US Patent 7173861), in view of Yi.
Regarding claim 20, Cho teaches a semiconductor device, comprising: a cell region including a plurality of memory cells (Cho, 100,Fig. 5,);
a plurality of bit lines connected to the plurality of memory cells (Cho, Ble0, Blo0, Ble1, BL01, Fig. 5), and a peripheral region including a page buffer connected to the plurality of bit lines (Cho, 200, Fig. 5).
Cho does not teach wherein the page buffer includes: an active pattern; a first source/drain region disposed on the active pattern; a second source/drain region spaced apart from the first source/drain region in a first direction and disposed on the active pattern;
a third source/drain region spaced apart from the first source/drain region in a second direction crossing the first direction and disposed on the active pattern; a fourth source/drain region spaced apart from the first source/drain region in a third direction crossing the first direction and the second direction and disposed on the active pattern; a first contact on the first source/drain region; a second contact on the second source/drain region; a third contact on the third source/drain region; a fourth contact on the fourth source/drain region; and a first gate electrode disposed on the active pattern, including a ring portion surrounding the fourth contact;
wherein the first source/drain region, the second source/drain region, the third source/drain region, the first contact, the second contact and the third contact are disposed outside the ring portion; and wherein the first gate electrode further includes an extension portion extended between the first contact and the second contact.
However, Yi teaches a semiconductor memory device including an active pattern (Yi, 620 Fig. 6A, Col 5, lines 58-63); a first source/drain region disposed on the active pattern (Yi, Fig 6A, see diagram below);
a second source/drain region spaced apart from the first source/drain region in a first direction and disposed on the active pattern (Yi, Fig 6A, see diagram below);
a third source/drain region spaced apart from the first source/drain region in a second direction crossing the first direction and disposed on the active pattern (Yi, Fig 6A, see diagram below);
a fourth source/drain region spaced apart from the first source/drain region in a third direction crossing the first direction and the second direction and disposed on the active pattern ((Yi, Fig 6A, see diagram below); a first contact on the first source/drain region ((Yi, Fig 6A, see diagram below); a second contact on the second source/drain region ((Yi, Fig 6A, see diagram below); a third contact on the third source/drain region ((Yi, Fig 6A, see diagram below); a fourth contact on the fourth source/drain region ((Yi, Fig 6A, see diagram below; and a first gate electrode disposed on the active pattern, including a ring portion surrounding the fourth contact (Yi, 600, Fig. 6A, Col. 5, lines 46-50); wherein the first source/drain region, the second source/drain region, the third source/drain region, the first contact, the second contact and the third contact are disposed outside the ring portion (Yi, Fig 6A, see diagram below); and wherein the first gate electrode further includes an extension portion extended between the first contact and the second contact (Yi, 600, Fig. 6A).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the nonvolatile semiconductor memory device of Cho with the mesh shaped gate of Yi to create a semiconductor device with ring shaped gate electrodes to reduce process costs, enhance performance and allow easy integration.
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicants’ disclosure:
Shin et al. (US Pub. 20210057419) teaches a semiconductor memory device with multiple conductive lines and a device isolation layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893