Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application KR 10-2022-0152236 filed on 11/15/2022 The foreign application is not in English. The certified copy of the foreign priority application has been received. Filing Dates for the Claims — All Claims Not Entitled to Priority DateTo be entitled to the filing date of the foreign priority application KR 10-2022-0152236 that is not in English, an English translation of the non-English language foreign application and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Response to Arguments: Drawings
Applicant’s arguments, see page 10, lines 10-21, filed 5/27/2026, with respect to figures 15 and 17 have been fully considered and are persuasive. The objection of figures 15 and 17 has been withdrawn.
Claim 7 recites the limitation “and a third contact on the third source/drain region.” A third contact has already been claimed in claim 1. This renders the claim indefinite
Claim Rejections 35 U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 recites the limitation " said first gate electrode including a first ring portion with inner edges that surround the first contact, wherein at least one of the inner edges of the first ring portion is arranged parallel to a first contact direction and at least one of the inner edges of the first ring portion is arranged parallel to a second contact direction; a second contact, which extends outside the first ring portion relative to the first contact and is spaced from the first contact in the first contact direction, and is electrically connected to the second source/drain region; a third contact which is spaced from the second contact in a third contact direction and spaced apart from the first contact in the second contact direction, wherein the third contact extends outside the first ring portion relative to the first contact: and a fourth contact which is spaced from the first contact in the third contact direction and spaced apart from the third contact in the first contact direction, wherein the fourth contact extends outside the first ring portion relative to the first contact, such that the first, second, third, and fourth contacts are disposed in a zigzag shape relative to one another." In lines 7-20. There is insufficient antecedent basis for this limitation in the claim.
The specification does not list “first contact direction”, “second contact direction” or “third contact direction.” Therefore there is insufficient antecedent basis for these directions. Additionally, the lack of antecedent basis renders the location of the second through fourth contacts relative to the first indefinite.
Note: For examination purposes of claims 1-11, the examiner will be using the following meanings:
The first contact direction is equivalent to D3 of the specification.
The second contact direction is equivalent to D4 of the specification.
The third contact direction is equivalent to D1 of the specification.
Additionally, the phrases “in the first/second/third contact direction” are being interpreted to read “in a vector primarily along the first/second/third direction”
Examiner has used these to determine the locations of the first through fifth contacts in claims 1-11, and will be interpreting them according to the diagram below.
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Claim 7 recites the limitation “and a third contact on the third source/drain region.” A third contact has already been claimed in claim 1. This renders the claim indefinite because there are now two claimed third contacts.
NOTE: For examination purposes this is being interpreted as reading “and the third contact on the third source/drain region.”
Claim 9 recites the limitation “and a fourth contact on the fourth source/drain region.” A fourth contact has already been claimed in claim 1. This renders the claim indefinite because there are now two claimed fourth contacts.
NOTE: For examination purposes this is being interpreted as reading “and the fourth contact on the fourth source/drain region.”
Claim Rejections 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 7-9, and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang et al.(US. Pub. 20140264622), hereinafter known as Jang.
Regarding claim 1, Jang teaches a semiconductor device, comprising: an active region (Jang, 114, Fig. 2A,para. 46) a first source/drain region on the active region (Jang, 115, Fig. 2A, para. 45, in the center); a first contact electrically connected to the first source/drain region (Jang, 132, Fig. 2A, para. 49, see image below); a second source/drain region ( Jang, 117, Fig. 2A, para. 45, see image below) spaced apart from the first source/drain region, on the active region; a first gate electrode (Jang, 120, Fig. 2A, para. 45) on the active region, said first gate electrode including a first ring portion with inner edges that surround the first contact, wherein at least one of the inner edges of the first ring portion is arranged parallel to a first contact direction and at least one of the inner edges of the first ring portion is arranged parallel to a second contact direction (Jang, Fig. 2A, see image below); a second contact (Jang, 132, Fig. 2A, para.49, see image below) which extends outside the first ring portion relative to the first contact and is spaced from the first contact in a vector primarily along the first contact direction, and is electrically connected to the second source/drain region; a third contact (Jang, 132, Fig. 2A, para.49, see image below) which is spaced from the second contact in a vector primarily along the third contact direction and spaced apart from the first contact in a vector primarily along the second contact direction, wherein the third contact extends outside the first ring portion relative to the first contact: and a fourth contact (Jang, 132, Fig. 2A, para. 49, see image below); which is spaced from the first contact in a vector primarily along the third contact direction and spaced apart from the third contact in a vector primarily along the first contact direction, wherein the fourth contact extends outside the first ring portion relative to the first contact, such that the first, second, third, and fourth contacts are disposed in a zigzag shape relative to one another (Jang, Fig. 2A, see image below).
Regarding claim 7, Jang teaches the semiconductor device of Claim 1, further comprising: a third source/drain region (Jang, 117, Fig. 2A, para. 45, see Fig. below), which is spaced apart from the first source/drain region and the second source/drain region, and is disposed on the active region (Jang, 114, Fig. 2A, para.46); and the third contact (Jang, 132, Fig. 2A, para.49, see image below) on the third source/drain region; wherein the third contact extends external to the first ring portion (Jang, Fig. 2A, see below); and wherein the first gate electrode further includes an extension portion (Jang, Fig. 2A, see below), which is connected to the first ring portion, and extends between the second contact and the third contact.
Regarding claim 8, Jang teaches the semiconductor device of Claim 1, wherein the first ring portion has a closed ring shape that surrounds the first contact (Jang, Fig. 2A, see image below).
Regarding claim 9, Jang teaches the semiconductor device of Claim 1, further comprising: a fourth source/drain region (Jang, 115, Fig. 2A, see image below) disposed on the active region; and the fourth contact on the fourth source/drain region; wherein the fourth contact extends outside the first ring portion; and wherein the first contact, the second contact and the fourth contact are arranged in a zigzag layout pattern
Regarding claim 11, Jang teaches the semiconductor device of Claim 1, wherein the first ring portion has a rhombus layout shape (Jang, para. 48, states that he source and drain regions may be square in shape, the first ring portion surrounds the first source/drain region, and therefore may be square. A square is a case of a rhombus which has four right angles).
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Claim Rejections 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jang.
Regarding claim 10, Jang teaches the semiconductor device of Claim 1, but the embodiment of Fig. 2A does not explicitly teach further comprising: a fifth source/drain region disposed on the active region; and a fifth contact extending on the fifth source/drain region; wherein the first gate electrode further includes a second ring portion, which extends on the active region and surrounds the fifth contact; and wherein the first ring portion and the second ring portion are electrically connected to each other.
However, in the embodiment of Fig. 9, Jang teaches a semiconductor device which comprises a first through fifth source/drain region, disposed on an active region, wherein the first, fourth and fifth source drain regions are inside ring shaped gates and the first through fourth source drain regions are arranged in a zig-zag.
Therefore, it would have been obvious to one having ordinary skill in the art to combine the embodiments of Jang to create a semiconductor device with a fifth source drain region, containing a fifth contact and a second ring portion on the first gate electrode, and the first and second ring portion are electrically connected to each other. This modification would serve to provide superior current drivability and allow the size of the device to be reduced (Jang, para. 73).
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Claims 2-3 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Jang as applied to claim 1 above, and further in view of Noro et. al. (US Pub. 20200202954) hereinafter referred to as Noro.
Regarding claim 2, Jang teaches the semiconductor device of claim 1,
wherein the active region (Jang, 114, Fig. 2A, para. 46) is defined by a device isolation layer (Jang, 113, Fig. 2A, para. 46).
Jang does not teach wherein the semiconductor device includes: (i) a central active pattern extended in a first direction, and (ii) a plurality of branch active patterns, which extend from the central active pattern in a second direction that crosses the first direction, and are spaced apart from each other in the first direction; wherein the device isolation layer extends in the second direction, and between the plurality of branch active patterns; and wherein the first source/drain region and the first contact are disposed on the central active pattern.
However, Noro teaches, a semiconductor device wherein the active region is defined by a device isolation layer (Noro, 101, 112, Fig 9A/9B paras. 76, 96 ), and includes: (i) a central active pattern extended in a first direction (Noro, 101, Fig. 8, para 76), and (ii) a plurality of branch active patterns, which extend from the central active pattern in a second direction that crosses the first direction, and are spaced apart from each other in the first direction (Noro, 115, Fig. 8, para. 97); wherein the device isolation layer extends in the second direction, and between the plurality of branch active patterns (Noro, 112, Fig. 9A/9B), and wherein the first source/drain region and the first contact are disposed on the central active pattern (Noro, 101, Fig 8, see below).
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Regarding claim 3, modified Jang teaches the semiconductor device of Claim 2, wherein the second source/drain region and the second contact are disposed on the central active pattern (Noro, 116, Fig 8, see diagram above).
Regarding claim 5, modified Jang teaches the semiconductor device of claim 2, wherein the first gate electrode further includes an extension portion, which is connected to the first ring portion and extends in the second direction ((Jang, Fig. 2A, see diagram below); and wherein the extension portion extends between the plurality of branch active patterns (Noro, 113, Fig. 8, 113 is the gate electrode for Noro), overlaps the device isolation layer (Noro, 112, Fig.9A), and overlaps the second contact (Noro, Fig 8, see diagram above) in the first direction.
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Regarding claim 6, modified Jang teaches the semiconductor device of Claim 2, further comprising a second gate electrode (Noro, 120, Fig. 8, para. 100) , which extends in the first direction, is spaced apart from the first gate electrode in the second direction, and crosses the plurality of branch active patterns.
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Therefore it would have been obvious to a person of ordinary skill in the art before the filing date of the invention to combine the teachings of Yi and Noro to create a semiconductor device having a ring shaped electrodes and multiple source/drain regions to lower gate resistances and provide semiconductor devices with enhanced reliability.
Claims 12-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Noro, in view of Jang
Regarding claim 12, Noro teaches a semiconductor device, comprising: a first active pattern extending in a first direction across a substrate (Noro, 115, Fig.8, para. 97); a second active pattern extending in the first direction, and adjacent the first active pattern in a second direction crossing the first direction (Noro, 101, Fig. 8, para. 76); a device isolation layer extending in the first direction, (Noro, 112, Fig. 9B, para. 96), and adjacent to the first active pattern in the second direction, and adjacent to the second active pattern in the first direction (Noro, Fig 8, see diagram below);a first source/drain region disposed on the first active pattern (Noro, Fig 8, see diagram below); a second source/drain region disposed on the first active pattern and spaced apart from the first source/drain region in the first direction (Noro, Fig 8, see diagram below); a third source/drain region disposed on the second active pattern and spaced apart from the first source/drain region and the second source/drain region (Noro, Fig 8, see diagram below); a fourth source/drain region disposed on the second active pattern and spaced apart from the first source/drain region, the second source/drain region, and the third source/drain region (Noro, Fig 8, see diagram below); a first contact on the first source/drain region (Noro, Fig 8, see diagram below; a second contact on the second source/drain region (Noro, Fig 8, see diagram below; a third contact on the third source/drain region (Noro, Fig 8, see diagram below; a fourth contact on the fourth source/drain region (Noro, Fig 8, see diagram below;
Noro does not teach and a first gate electrode disposed over the first active pattern and the second active pattern, including a first ring portion with inner edges which surround
However, Jang teaches a semiconductor device including a first gate electrode (Jang 120, Fig. 2A) disposed over the active pattern (Jang, 114, Fig. 2A), including a first ring portion with inner edges which surround
Therefore, it would have been obvious to one having ordinary skill in the art to combine the device of Noro with the configuration of Jang to provide superior current drivability and allow the size of the device to be reduced (Jang, para. 73).
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Regarding claim 13, modified Noro teaches he semiconductor device of Claim 12, wherein the first active pattern and the second active pattern are connected to each other (Noro, 101, Fig 9A/B, it is an n type doped region connecting all the active patterns); and wherein a first length in which the first active pattern is extended in the first direction (Noro, 115, Fig. 8) is longer than a second length in which the second active pattern is extended in the first direction (Noro 113, Fig 8, 115 extends further than 113).
Regarding claim 14, modified Noro teaches the semiconductor device of Claim 12, further comprising: a second gate electrode ((Noro, 120, Fig 8, para. 120) spaced apart from the first gate electrode in the first direction), and extending in the second direction; and wherein the second gate electrode crosses the first active pattern and the device isolation layer (Noro, Fig. 9B, shows 120 crossing 115(first active pattern) and 112 (element separation region)) and does not overlap the second active pattern (120 does not cross 101)).
Regarding claim 15, modified Noro teaches the semiconductor device of Claim 12, wherein the first gate electrode further includes an extension portion extended from the first ring portion (Jang, Fig. 2A, see diagram above); wherein the extension portion (Jang, Fig. 2A, see diagram above) extends over the active pattern (Jang, 114, Fig. 2A) and the device isolation layer (Jang, 113, Fig. 2A). Additionally, Noro teaches a gate electrode (Noro, 113, Fig. 9A, para. 96) that extends over the element separation region (Noro, 112, Fig. 9A). Combining the extension region of Jang with the active patterns of Noro will yield the claimed properties.
Regarding claim 16, the semiconductor device of Claim 15, wherein the first contact and the second contact do not overlap the device isolation layer, but overlap the extension portion in the second direction (Jang, Fig. 2A, see diagram above).
Regarding claim 19, modified Noro teaches the semiconductor device of Claim 12, further comprising: a fourth active pattern adjacent to the first active pattern in the second direction and extended in the first direction (Noro, Fig 8, see diagram above); a fifth source/drain region disposed on the fourth active pattern (Nor, Fig. 8, see diagram above); and a fifth contact on the fifth source/drain region (Noro, Fi. 8, see diagram above).
Modified Noro does not explicitly teach wherein the first gate electrode further includes a second ring portion surrounding the fifth contact; wherein the first ring portion and the second ring portion are connected to each other; wherein the first gate electrode has a first width in the second direction between the third contact and the fifth contact and has a second width in the third direction between the first contact and the third contact; and wherein the first width is greater than the second width.
However, Jang teaches an embodiment wherein
However, in the embodiment of Fig. 9, Jang teaches a semiconductor device which comprises a first through fifth source/drain region (Jang, Fig. 9, see diagram below), disposed on an active region (Jang, Fig. 9, see diagram below), wherein the third, fourth and fifth source drain regions are inside ring shaped gates and the first through fifth source drain regions are arranged in a zig-zag (Jang, Fig. 9, see diagram below). Additionally, the first width between the third and fifth contact is greater than the second width between the first and third contacts. (Jang, Fig. 9, see diagram below).
Therefore, it would have been obvious to one having ordinary skill in the art to combine the additional embodiment of Jang with the teachings of Noro and Jang to create a semiconductor device with a fifth source drain region, containing a fifth contact and a second ring portion on the first gate electrode, and the first and second gate electrode are electrically connected to each other. This modification would serve to provide superior current drivability and allow the size of the device to be reduced (Jang, para. 73).
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Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al, (US Patent 7173861), in view of Jang
Regarding claim 20, Cho teaches a semiconductor device, comprising: a cell region including a plurality of memory cells (Cho, 100,Fig. 5,); a plurality of bit lines connected to the plurality of memory cells (Cho, Ble0, Blo0, Ble1, BL01, Fig. 5), and a peripheral region including a page buffer connected to the plurality of bit lines (Cho, 200, Fig. 5).
Cho does not teach wherein the page buffer includes: wherein the page buffer includes; an active pattern; a first source/drain region disposed on the active pattern; a second source/drain region spaced apart from the first source/drain region in a first direction and disposed on the active pattern; a third source/drain region spaced apart from the first source/drain region in a second direction crossing the first direction and disposed on the active pattern; a fourth source/drain region spaced apart from the first source/drain region in a third direction crossing the first direction and the second direction and disposed on the active pattern; a first contact on the first source/drain region; a second contact on the second source/drain region; a third contact on the third source/drain region; a fourth contact on the fourth source/drain region; and a first gate electrode disposed on the active pattern, including a ring portion with inner edges which surround the fourth contact, wherein the second contact is spaced apart from the fourth contact in a fourth direction crossing the first direction, the second direction, and the third direction; wherein at least one of the inner edges of the ring portion is parallel to the third direction and at least one of the inner edges of the ring portion is parallel to the fourth direction, and wherein the first, second, third, and fourth contacts are disposed in a zigzag shape relative to one another; wherein the first source/drain region, the second source/drain region, the third source/drain region, the first contact, the second contact and the third contact are disposed outside the ring portion; and wherein the first gate electrode further includes an extension portion extended between the first contact and the second contact.
However, Jang teaches a semiconductor device which includes; an active pattern (Jang, 114, Fig. 2A, para. 46); a first source/drain region (Jang, 115, Fig. 2A, para, 45, see diagram below) disposed on the active pattern; a second source/drain region (Jang, 115, Fig. 2A, para, 45, see diagram below) spaced apart from the first source/drain region in a first direction and disposed on the active pattern; a third source/drain region spaced (Jang, 115, Fig. 2A, para, 45, see diagram below) apart from the first source/drain region in a second direction crossing the first direction and disposed on the active pattern; a fourth source/drain (Jang, 117, Fig. 2A, para, 45, see diagram below) region spaced apart from the first source/drain region in a third direction crossing the first direction and the second direction and disposed on the active pattern; a first contact (Jang, 132, Fig. 2A, para, 45, see diagram below) on the first source/drain region; a second contact (Jang, 132, Fig. 2A, para, 45, see diagram below) on the second source/drain region; a third contact (Jang, 132, Fig. 2A, para, 45, see diagram below) on the third source/drain region; a fourth contact (Jang, 131, Fig. 2A, para, 45, see diagram below) on the fourth source/drain region; and a first gate electrode (Jang, 120, Fig. 2A, para. 45) disposed on the active pattern, including a ring portion (Jang, Fig. 2A, see diagram below) with inner edges which surround the fourth contact, wherein the second contact is spaced apart from the fourth contact in a fourth direction crossing the first direction, the second direction, and the third direction; wherein at least one of the inner edges of the ring portion is parallel to the third direction and at least one of the inner edges of the ring portion is parallel to the fourth direction, and wherein the first, second, third, and fourth contacts are disposed in a zigzag shape relative to one another (Jang, Fig. 2A, see diagram below); wherein the first source/drain region, the second source/drain region, the third source/drain region, the first contact, the second contact and the third contact are disposed outside the ring portion (Jang, Fig. 2A, see diagram below); and wherein the first gate electrode further includes an extension portion extended between the first contact and the second contact (Jang, Fig. 2A, see diagram below).
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Response to Arguments
Applicant’s arguments with respect to claims 1, 12 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hasunuma et al. (US Pub. 20100197097) teaches a semiconductor device with ring-shaped gate electrodes.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:00-4:3.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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