DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Interpretation
The originally filed Specification at Paragraph [0049] defines the phrase “connected to” accordingly to mean “directly on, connected, coupled, or adjacent to the other component, or intervening components may be present.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-7, 9-13, 15-16, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (hereinafter “Zhang” US 2022 / 0302240) in view of Ramsbey et al. (hereinafter “Ramsbey” US 5,981,364).
(It should be noted that the Zhang references was submitted by the applicant via Information Disclosure Statement on 12 September 2023.)
As pertaining to Claim 1, Zhang discloses (see Fig. 2) a gate driving circuit comprising a plurality of stages (see Page 4, Para. [0064]), wherein each of the plurality of stages comprises (see Page 4 through Page 5, Para. [0065]-[0081]):
a first node controller (T1, T4, T6) configured to control a voltage level of a first node (PD_in) and a voltage level of a second node (U4);
a second node controller (T2, T3) configured to control a voltage level of a third node (PD_ox); and
a first output unit (T11, T12) connected between a first voltage input terminal (VGH) to which a first voltage (VGH) is input and a second voltage input terminal (see (VGL) at (T12)) to which a second voltage (VGL) is input, and configured to output the first voltage (VGH) or the second voltage (see (VGL) at (T12)) as a gate signal (GO) according to the voltage levels of the second node (U4) and the third node (PD_ox; see Page 5, Para. [0075] and note that the first voltage is mislabeled in Fig. 2 and is intended to show (VGH), rather than (VGL), as the first voltage),
wherein the first node controller (T1, T4, T6) comprises:
a first transistor (T1) connected between an input terminal (IN1) to which a start signal (IN1) is input and the first node (PD_in), and comprising a gate connected to a first clock terminal (CK1) to which a first clock signal (CK1) is input;
a second transistor (T6) connected between the first node (PD_in) and a third voltage input terminal (see (VGL) at (T10)) to which a third voltage (see (VGL) at (T10)) is input, and comprising a first gate and a second gate which are connected to the third node (PD_ox); and
a third transistor (T4) connected between the first node (PD_in) and the second node (U4), and comprising a gate connected to the first voltage input terminal (VGH),
wherein the first gate and the second gate of the second transistor (T4) are disposed in different layers with a semiconductor (see (500) in Fig. 4) disposed therebetween, and
wherein a gate signal input to the gate of the third transistor (T4) is the first voltage (VGH; see Page 5 through Page 6, Para. [0078], [0083], [0085], and [0088]; and see Fig. 4).
Zhang explicitly suggests that only some (i.e., at least one) of the transistors of the gate driving circuit may be a double-gate transistor (see Page 5, Para. [0083]), implying that at least one of the first, second, and third transistors can be a single-gate transistor. Further, in this regard, it would have been obvious to one of ordinary skill in the art that there is a design incentive in incorporating both double-gate transistors and single-gate transistors in the gate driving circuit of Zhang in order to take advantage of the structural and/or functional benefits offered by each of the double-gate transistor and the single-gate transistor. One of ordinary skill in the art would have readily identified a finite number of predictable possible solutions in implementing the gate driving circuit of Zhang using a combination of both double-gate transistors and single-gate transistors, and these predictable possible solutions are explicitly anticipated and suggested by Zhang (again, see Page 5, Para. [0083]). As such, it would have been obvious to one of ordinary skill in the art to try an implementation in which each of the first transistor and the third transistor is a single gate transistor comprising one gate, as one of ordinary skill in the art would have pursued this implementation with a reasonable expectation of success in taking advantage of the distinct benefits offered by the single-gate transistor and the double-gate transistor in the gate driving circuit.
Still, Zhang does not explicitly provide a rationale for implementing each of the first transistor and the third transistor as a single gate transistor comprising one gate.
However, in the same field of endeavor, Ramsbey discloses that a method for fabricating high quality semiconductor devices (see Col. 1, Ln. 8-10) was well-known in the art before the effective filing date of the claimed invention, wherein the method includes fabricating single gate transistors having uniform thickness in a gate layer and oxide layer interfaces such that the single gate transistors operate with less variations in threshold voltages and drive current requirements (see Col. 1, Ln. 35-55 and Col. 9, Ln. 63-67 through Col. 10, Ln. 1-2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang with the teachings of Ramsbey, such that each of the first transistor and the third transistor of Zhang is implemented as a single gate transistor comprising one gate for reducing a change in threshold voltage due to repeated driving in the gate driving circuit, as suggested by Ramsbey, in order to provide a high quality gate driving circuit using at least two transistors that operate with less variations in threshold voltages and drive current requirements.
As pertaining to Claim 6, Zhang discloses (see Fig. 2) that the first node controller (T1, T4, T6) comprises:
a fourth transistor (T5) connected between the second node (U4) and a second clock terminal (CK2) to which a second clock signal (CK2) is input, and comprising a gate connected to the second node (U4); and
a first capacitor (C1) connected between the second node (U4) and the fourth transistor (T5; see Page 5, Para. [0069] and [0077]),
wherein the first clock signal (CK1) and the second clock signal (CK2) repeat (i.e., as a clock signal) a voltage of a first voltage level (i.e., a high level) and a voltage of a second voltage level (i.e., a low level), and the second clock signal (see (CK2) for an odd/even row) is shifted by a half cycle from the first clock signal (see (CK1) for an even/odd row; and see Page 5, Para. [0082] and note that (CK1) and (CK2) are on alternating lines for even/odd rows).
As pertaining to Claim 7, Zhang discloses (see Fig. 2) that the second node controller (T2, T3) comprises:
a fourth transistor (T2) connected between the third node (PD_ox) and the third voltage input terminal (VGL), and comprising a first gate connected to the first node (PD_in) and a second gate connected to the third voltage input terminal (VGL; see Page 4, Para. [0066]).
As pertaining to Claim 9, Zhang discloses (see Fig. 2) that the first output unit (T11, T12) comprises:
a first pull-up transistor (T11) connected between the first voltage input terminal (VGH) and a first output node (GO), and comprising a gate connected to the second node (U4); and
a first pull-down transistor (T12) connected between the second voltage input terminal (VGL) and the first output node (GO), and comprising a gate connected to the third node (PD_ox; see Page 5, Para. [0075]-[0076] and again note that the first voltage is mislabeled in Fig. 2 and is intended to show (VGH), rather than (VGL), as the first voltage).
As pertaining to Claim 10, Zhang discloses (see Fig. 2) that the first output unit (T11, T12) comprises:
a first pull-up transistor (T11) connected between the first voltage input terminal (VGH) and a first output node (GO), and comprising a first gate and a second gate which are connected to the second node (U4); and
a first pull-down transistor (T12) connected between the second voltage input terminal (VGL) and the first output node (GO), and comprising a first gate and a second gate which are connected to the third node (PD_ox; see Page 5, Para. [0075]-[0076] and again note that the first voltage is mislabeled in Fig. 2 and is intended to show (VGH), rather than (VGL), as the first voltage),
wherein the first gate and the second gate of each of the first pull-up transistor (T11) and the first pull-down transistor (T12) are disposed in different layers with a semiconductor (see (500) in Fig. 4) disposed therebetween (see Page 5 through Page 6, Para. [0083], [0085], and [0088]; and see Fig. 4).
As pertaining to Claim 11, Zhang discloses (see Fig. 2) that each of the plurality of stages further comprises:
a second output unit (T9, T10) connected between the first voltage input terminal (VGH) and the third voltage input terminal (VGL), and configured to output the first voltage (VGH) or the third voltage (VGL) as a carry signal (i.e., a signal at (PD_ox)) according to the voltage levels of the second node (U4) and the third node (PD_ox; see Page 5, Para. [0073]-[0074]).
As pertaining to Claim 12, Zhang discloses (see Fig. 2) that the second output unit (T9, T10) comprises:
a pull-up transistor (T9) connected between the first voltage input terminal (VGH) and an output node (see (PD_ox)), and comprising a first gate and a second gate which are connected to the second node (U4); and
a pull-down transistor (T10) connected between the third voltage input terminal (VGL) and the output node (PD_ox), and comprising a first gate and a second gate which are connected (i.e., adjacent to or electrically connected) to the third node (PD_ox; see Page 5, Para. [0073]-[0074]),
wherein the first gate and the second gate of each of the pull-up transistor (T9) and the pull-down transistor (T10) are disposed in different layers with a semiconductor (see (500) in Fig. 4) disposed therebetween (see Page 5 through Page 6, Para. [0083], [0085], and [0088]; and see Fig. 4).
As pertaining to Claim 13, Zhang discloses (see Fig. 2) that a start signal (i.e., see (IN1)) of a first stage among the plurality of stages is an external signal (see (14) in Fig. 1), and start signals of second and later stages among the plurality of stages are carry signals output from a preceding stage (see Page 4, Para. [0064]).
As pertaining to Claim 15, Zhang discloses (see Fig. 2) that a timing when an on-time of the start signal (see (IN1)) of the first stage starts is the same as a timing when an on-time of a first gate signal output (GO) from the first stage starts (i.e., the start signal (IN1) for the first stage starts to produce the output (GO) from the first stage), and
a timing when an on-time of a gate signal output (GO) from each of the second and later stages starts (i.e., the subsequent cascaded stages) is delayed by a certain time (i.e., an arbitrary propagation time) from a timing when an on-time of a start signal (IN1) of each of the second and later stages starts (again, see Page 4, Para. [0064] and see Fig. 2 as a representation of a first stage and subsequent cascaded stages).
As pertaining to Claim 16, Zhang discloses (see Fig. 2) that each of the plurality of stages further comprises:
a reset transistor (i.e., see (T7)) connected between the first node (PD_in) and the second voltage input terminal (VGL), and configured to reset the first node (PD_in),
wherein the reset transistor (T7) comprises a first gate and a second gate which are connected to a reset terminal (CK2) to which a reset signal (see (CK2)) is input (see Page 5, Para. [0071]).
As pertaining to Claim 21, Zhang discloses (see Fig.1 and Fig. 2) an electronic device, comprising:
a display panel (see Fig. 1) comprising a plurality of gate lines (i.e., see (EM, GA)); and
a gate driving circuit (14) comprising a plurality of stages (see Page 4, Para. [0064]), each configured to output a gate signal (GO) to a corresponding gate line (i.e., see (EM)) of the display panel,
wherein (see Fig. 2) each of the plurality of stages comprises (see Page 4 through Page 5, Para. [0065]-[0081]):
a first node controller (T1, T4, T6) configured to control a voltage level of a first node (PD_in) and a voltage level of a second node (U4);
a second node controller (T2, T3) configured to control a voltage level of a third node (PD_ox); and
a first output unit (T11, T12) connected between a first voltage input terminal (VGH) to which a first voltage (VGH) is input and a second voltage input terminal (see (VGL) at (T12)) to which a second voltage (VGL) is input, and configured to output the first voltage (VGH) or the second voltage (see (VGL) at (T12)) as a gate signal (GO) according to the voltage levels of the second node (U4) and the third node (PD_ox; see Page 5, Para. [0075] and note that the first voltage is mislabeled in Fig. 2 and is intended to show (VGH), rather than (VGL), as the first voltage),
wherein the first node controller (T1, T4, T6) comprises:
a first transistor (T1) connected between an input terminal (IN1) to which a start signal (IN1) is input and the first node (PD_in), and comprising a gate connected to a first clock terminal (CK1) to which a first clock signal (CK1) is input;
a second transistor (T6) connected between the first node (PD_in) and a third voltage input terminal (see (VGL) at (T10)) to which a third voltage (see (VGL) at (T10)) is input, and comprising a first gate and a second gate which are connected to the third node (PD_ox); and
a third transistor (T4) connected between the first node (PD_in) and the second node (U4), and comprising a gate connected to the first voltage input terminal (VGH),
wherein the first gate and the second gate of the second transistor (T4) are disposed in different layers with a semiconductor (see (500) in Fig. 4) disposed therebetween, and
wherein a gate signal input to the gate of the third transistor (T4) is the first voltage (VGH; see Page 5 through Page 6, Para. [0078], [0083], [0085], and [0088]; and see Fig. 4).
Zhang explicitly suggests that only some (i.e., at least one) of the transistors of the gate driving circuit may be a double-gate transistor (see Page 5, Para. [0083]), implying that at least one of the first, second, and third transistors can be a single-gate transistor. Further, in this regard, it would have been obvious to one of ordinary skill in the art that there is a design incentive in incorporating both double-gate transistors and single-gate transistors in the gate driving circuit of Zhang in order to take advantage of the structural and/or functional benefits offered by each of the double-gate transistor and the single-gate transistor. One of ordinary skill in the art would have readily identified a finite number of predictable possible solutions in implementing the gate driving circuit of Zhang using a combination of both double-gate transistors and single-gate transistors, and these predictable possible solutions are explicitly anticipated and suggested by Zhang (again, see Page 5, Para. [0083]). As such, it would have been obvious to one of ordinary skill in the art to try an implementation in which each of the first transistor and the third transistor is a single gate transistor comprising one gate, as one of ordinary skill in the art would have pursued this implementation with a reasonable expectation of success in taking advantage of the distinct benefits offered by the single-gate transistor and the double-gate transistor in the gate driving circuit.
Still, Zhang does not explicitly provide a rationale for implementing each of the first transistor and the third transistor as a single gate transistor comprising one gate for reducing a change in threshold voltage due to repeated driving in the gate driving circuit.
However, in the same field of endeavor, Ramsbey discloses that a method for fabricating high quality semiconductor devices (see Col. 1, Ln. 8-10) was well-known in the art before the effective filing date of the claimed invention, wherein the method includes fabricating single gate transistors having uniform thickness in a gate layer and oxide layer interfaces such that the single gate transistors operate with less variations in threshold voltages and drive current requirements (see Col. 1, Ln. 35-55 and Col. 9, Ln. 63-67 through Col. 10, Ln. 1-2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang with the teachings of Ramsbey, such that each of the first transistor and the third transistor of Zhang is implemented as a single gate transistor comprising one gate for reducing a change in threshold voltage due to repeated driving in the gate driving circuit, as suggested by Ramsbey, in order to provide a high quality gate driving circuit using at least two transistors that operate with less variations in threshold voltages and drive current requirements.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Ramsbey and further in view of Chung (US 2012 / 0038609).
As pertaining to Claim 2, Zhang discloses (see Fig. 2) that a voltage level of the first voltage (VGH; see Page 4 through Page 5, Para. [0068]) is greater than a voltage level of the second voltage (see (VGL) at (T12); and see Page 5, Para. [0076]; and note that (VGH) is arbitrarily a “high” voltage and (VGL) is arbitrarily a “low” voltage).
Zhang discloses a first output unit (T11, T12) connected between the first voltage input terminal (VGH) and the second voltage input terminal (VGL), and a second output unit (T9, T10) connected between the first voltage input terminal (VGH) and the second voltage input terminal (VGL). Neither Zhang nor Ramsbey explicitly discloses that the second output unit (T9, T10) is connected to a third voltage input terminal such that a voltage level of the third voltage is less than the voltage level of the second voltage.
However, in the same field of endeavor, Chung discloses (see Fig. 3A) a gate driving circuit in which a first output unit (M15, M16) is connected between a first voltage input terminal (VGH) and a second voltage input terminal (VGL1), and a second output unit (M11, M13) connected between the first voltage input terminal (VGH) and a third voltage input terminal (VGL2), wherein a voltage level of the first voltage (VGH) is greater than a voltage level of the second voltage (VGL1), and a voltage level of the third voltage (VGL2) is less than the voltage level of the second voltage (VGL1; see Page 6, Para. [0104]-[0106]; and Page 7, Para. [0129], [0131], and [0133]-[0134]). It is a goal of Chung to provide a simple gate driving circuit structure for implementation in a display device (see Page 1, Para. [0009]). Further, Chung explicitly discloses that by incorporating a second voltage (VGL1) associated with the first output unit and a third voltage (VGL2) for a second output unit, such that the third voltage (VGL2) is less than the second voltage (VGL1), an output voltage of a gate driving circuit can be made stable, an operational margin of a transistor can be improved, and a yield of a display device can be improved (see Page 8, Para. [0147]-[0148]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang and Ramsbey with the teachings of Chung, such that the second output unit (T9, T10) is Ramsbey to a third voltage input terminal, wherein a voltage level of the third voltage is less than the voltage level of the second voltage, as suggested by Chung, in order to provide a gate driving circuit that is made stable with an improved operational margin of a transistor and an improved yield of a display device.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Ramsbey and further in view of Feng et al. (hereinafter “Feng” US 2022 / 0005417).
As pertaining to Claim 3, neither Zhang nor Ramsbey explicitly discloses (see Fig. 2) that the first transistor (T1) comprises a plurality of sub-transistors connected in series with each other, and a gate of each of the plurality of sub-transistors is connected to the first clock terminal (CLK1).
However, in the same field of endeavor, Feng discloses (see Fig. 10) that it was well-known in the art before the effective filing date of the claimed invention that electric leakage can be prevented in a gate driving circuit by replacing a single transistor with a pair of sub-transistors and utilizing a leakage prevention transistor connected between the pair of sub-transistors. In fact, Feng suggests that a first transistor (M5) connected between an input terminal (STU2) and a first node (Q) and comprising a gate connected to a first clock terminal (CLKA), and a second transistor (M9) connected between the first node (Q) and a third voltage input (VSS3) and comprising a gate connected to a third node (QB), can both include a plurality of sub-transistors (see (M5_a, M5_b) of (M5) and see (M9_a, M9_b) of (M9)) connected in series with each other, wherein a gate of each of the plurality of sub-transistors (M5_a, M5_b) of the first transistor (M5) is connected to the first clock terminal (CLKA; see Page 12, Para. [0167]-[0168]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang and Ramsbey with the teachings of Feng, such that the first transistor (T1) comprises a plurality of sub-transistors connected in series with each other, and a gate of each of the plurality of sub-transistors is connected to the first clock terminal (CLK1), as suggested by Feng, in order to allow for the implementation of leakage prevention in the gate driving circuit to thereby improve the performance of the gate driving circuit.
As pertaining to Claim 4, neither Zhang nor Ramsbey explicitly discloses (see Fig. 2) that the second transistor (T6) comprises a plurality of sub-transistors connected in series with each other, and a first gate and a second gate of each of the plurality of sub-transistors are connected to the third node (PD_ox).
However, in the same field of endeavor, Feng discloses (see Fig. 10) that it was well-known in the art before the effective filing date of the claimed invention that electric leakage can be prevented in a gate driving circuit by replacing a single transistor with a pair of sub-transistors and utilizing a leakage prevention transistor connected between the pair of sub-transistors. In fact, Feng suggests that a first transistor (M5) connected between an input terminal (STU2) and a first node (Q) and comprising a gate connected to a first clock terminal (CLKA), and a second transistor (M9) connected between the first node (Q) and a third voltage input (VSS3) and comprising a gate connected to a third node (QB), can both include a plurality of sub-transistors (see (M5_a, M5_b) of (M5) and see (M9_a, M9_b) of (M9)) connected in series with each other, wherein a gate of each of the plurality of sub-transistors (M9_a, M9_b) of the second transistor (M9) is connected to the third node (QB; see Page 12, Para. [0167]-[0168]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang and Ramsbey with the teachings of Feng, such that the second transistor (T6) comprises a plurality of sub-transistors connected in series with each other, and a first gate and a second gate of each of the plurality of sub-transistors are connected to the third node (PD_ox), as suggested by Feng, in order to allow for the implementation of leakage prevention in the gate driving circuit to thereby improve the performance of the gate driving circuit.
As pertaining to Claim 5, neither Zhang nor Ramsbey explicitly discloses (see Fig. 2) that each of the first transistor (T1) and the second transistor (T6) comprises a pair of sub-transistors connected in series with each other, and each of the plurality of stages further comprises a leakage prevention transistor comprising a gate connected to the first node, and comprising a first end connected to the first voltage input terminal and a second end connected to an intermediate node of the pair of sub-transistors.
However, in the same field of endeavor, Feng discloses (see Fig. 10) that it was well-known in the art before the effective filing date of the claimed invention that electric leakage can be prevented in a gate driving circuit by replacing a single transistor with a pair of sub-transistors and utilizing a leakage prevention transistor connected between the pair of sub-transistors. In fact, Feng suggests that a first transistor (M5) connected between an input terminal (STU2) and a first node (Q) and comprising a gate connected to a first clock terminal (CLKA), and a second transistor (M9) connected between the first node (Q) and a third voltage input (VSS3) and comprising a gate connected to a third node (QB), can both include a pair of sub-transistors (see (M5_a, M5_b) of (M5) and see (M9_a, M9_b) of (M9)) connected in series with each other, and each of a plurality of stages further comprises a leakage prevention transistor (M16) comprising a gate connected to the first node (Q), and comprising a first end connected to a first voltage input terminal (i.e., a high voltage input terminal (VA)) and a second end connected to an intermediate node of the pair of sub-transistors (see (M5) and (M9); and see Page 12, Para. [0167]-[0168]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang and Ramsbey with the teachings of Feng, such that each of the first transistor (T1) and the second transistor (T6) comprises a pair of sub-transistors connected in series with each other, and each of the plurality of stages further comprises a leakage prevention transistor comprising a gate connected to the first node, and comprising a first end connected to the first voltage input terminal and a second end connected to an intermediate node of the pair of sub-transistors, as suggested by Feng, in order to allow for the implementation of leakage prevention in the gate driving circuit to thereby improve the performance of the gate driving circuit.
Claims 17, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Ramsbey in view of Feng and further in view of Chung.
As pertaining to Claim 17, Zhang discloses (see Fig. 2) a gate driving circuit comprising a plurality of stages (see Page 4, Para. [0064]), wherein each of the plurality of stages comprises (see Page 4 through Page 5, Para. [0065]-[0081]):
a first node controller (T1, T4, T6) configured to control a voltage level of a first node (PD_in) and a voltage level of a second node (U4);
a second node controller (T2, T3) configured to control a voltage level of a third node (PD_ox); and
a first output unit (T11, T12) connected between a first voltage input terminal (VGH) to which a first voltage (VGH) is input and a second voltage input terminal (see (VGL) at (T12)) to which a second voltage (VGL) is input, and configured to output the first voltage (VGH) or the second voltage (see (VGL) at (T12)) as a gate signal (GO) according to the voltage levels of the second node (U4) and the third node (PD_ox; see Page 5, Para. [0075] and note that the first voltage is mislabeled in Fig. 2 and is intended to show (VGH), rather than (VGL), as the first voltage),
wherein the first node controller (T1, T4, T6) comprises:
a first transistor (T1) connected between an input terminal (IN1) to which a start signal (IN1) is input and the first node (PD_in), and comprising a gate connected to a first clock terminal (CK1) to which a first clock signal (CK1) is input;
a second transistor (T6) connected between the first node (PD_in) and a third voltage input terminal (see (VGL) at (T10)) to which a third voltage (see (VGL) at (T10)) is input, and comprising a first gate and a second gate which are connected to the third node (PD_ox); and
a third transistor (T4) connected between the first node (PD_in) and the second node (U4), and comprising a gate connected to the first voltage input terminal (VGH),
wherein a voltage level of the first voltage (VGH; see Page 4 through Page 5, Para. [0068]) is greater than a voltage level of the second voltage (see (VGL) at (T12); and see Page 5, Para. [0076]; and note that (VGH) is arbitrarily a “high” voltage and (VGL) is arbitrarily a “low” voltage)), and
wherein a gate signal input to the gate of the third transistor (T4) is the first voltage (VGH; see Page 5 through Page 6, Para. [0078], [0083], [0085], and [0088]; and see Fig. 4).
Zhang explicitly suggests that only some (i.e., at least one) of the transistors of the gate driving circuit may be a double-gate transistor (see Page 5, Para. [0083]), implying that at least one of the first, second, and third transistors can be a single-gate transistor. Further, in this regard, it would have been obvious to one of ordinary skill in the art that there is a design incentive in incorporating both double-gate transistors and single-gate transistors in the gate driving circuit of Zhang in order to take advantage of the structural and/or functional benefits offered by each of the double-gate transistor and the single-gate transistor. One of ordinary skill in the art would have readily identified a finite number of predictable possible solutions in implementing the gate driving circuit of Zhang using a combination of both double-gate transistors and single-gate transistors, and these predictable possible solutions are explicitly anticipated and suggested by Zhang (again, see Page 5, Para. [0083]). As such, it would have been obvious to one of ordinary skill in the art to try an implementation in which each of the first transistor and the third transistor is a single gate transistor comprising one gate, as one of ordinary skill in the art would have pursued this implementation with a reasonable expectation of success in taking advantage of the distinct benefits offered by the single-gate transistor and the double-gate transistor in the gate driving circuit.
Still, Zhang does not explicitly provide a rationale for implementing each of the first transistor and the third transistor as a single gate transistor comprising one gate for reducing a change in threshold voltage due to repeated driving in the gate driving circuit.
However, in the same field of endeavor, Ramsbey discloses that a method for fabricating high quality semiconductor devices (see Col. 1, Ln. 8-10) was well-known in the art before the effective filing date of the claimed invention, wherein the method includes fabricating single gate transistors having uniform thickness in a gate layer and oxide layer interfaces such that the single gate transistors operate with less variations in threshold voltages and drive current requirements (see Col. 1, Ln. 35-55 and Col. 9, Ln. 63-67 through Col. 10, Ln. 1-2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang with the teachings of Ramsbey, such that each of the first transistor and the third transistor of Zhang is implemented as a single gate transistor comprising one gate for reducing a change in threshold voltage due to repeated driving in the gate driving circuit, as suggested by Ramsbey, in order to provide a high quality gate driving circuit using at least two transistors that operate with less variations in threshold voltages and drive current requirements.
Further, neither Zhang nor Ramsbey explicitly discloses (see Fig. 2) that the first transistor (T1) comprises a pair of first sub-transistors connected in series with each other, wherein a gate of each of the first sub-transistors is connected to the first clock terminal (CLK1). Further, neither Zhang nor Ramsbey explicitly discloses (see Fig. 2) that the second transistor (T6) comprises a pair of second sub-transistors connected in series with each other, wherein a gate of each of the second sub-transistors is connected to the third node (PD_ox).
However, in the same field of endeavor, Feng discloses (see Fig. 10) that it was well-known in the art before the effective filing date of the claimed invention that electric leakage can be prevented in a gate driving circuit by replacing a single transistor with a pair of sub-transistors and utilizing a leakage prevention transistor connected between the pair of sub-transistors. In fact, Feng suggests that a first transistor (M5) connected between an input terminal (STU2) and a first node (Q) and comprising a gate connected to a first clock terminal (CLKA), and a second transistor (M9) connected between the first node (Q) and a third voltage input (VSS3) and comprising a gate connected to a third node (QB), can both include a pair of sub-transistors (see (M5_a, M5_b) of (M5) and see (M9_a, M9_b) of (M9)) connected in series with each other, and each of a plurality of stages further comprises a leakage prevention transistor (M16) comprising a gate connected to the first node (Q), and comprising a first end connected to a first voltage input terminal (i.e., a high voltage input terminal (VA)) and a second end connected to an intermediate node of the pair of sub-transistors (see (M5) and (M9); and see Page 12, Para. [0167]-[0168]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang and Ramsbey with the teachings of Feng, such that each of the first transistor (T1) and the second transistor (T6) comprises a pair of sub-transistors connected in series with each other, wherein a gate of each of the first sub-transistors is connected to the first clock terminal (CLK1) and a gate of each of the second sub-transistors is connected to the third node (PD_ox), and each of the plurality of stages further comprises a leakage prevention transistor, as suggested by Feng, in order to allow for the implementation of leakage prevention in the gate driving circuit to thereby improve the performance of the gate driving circuit.
Still, none of Zhang, Ramsbey, and Feng explicitly discloses that a voltage level of the third voltage is less than the voltage level of the second voltage.
However, in the same field of endeavor and in the same manner as Zhang, Chung discloses (see Fig. 3A) a gate driving circuit in which a first output unit (M15, M16) is connected between a first voltage input terminal (VGH) and a second voltage input terminal (VGL1), and a second output unit (M11, M13) connected between the first voltage input terminal (VGH) and a third voltage input terminal (VGL2), wherein a voltage level of the first voltage (VGH) is greater than a voltage level of the second voltage (VGL1), and a voltage level of the third voltage (VGL2) is less than the voltage level of the second voltage (VGL1; see Page 6, Para. [0104]-[0106]; and Page 7, Para. [0129], [0131], and [0133]-[0134]). It is a goal of Chung to provide a simple gate driving circuit structure for implementation in a display device (see Page 1, Para. [0009]). Further, Chung explicitly discloses that by incorporating a second voltage (VGL1) associated with the first output unit and a third voltage (VGL2) for a second output unit, such that the third voltage (VGL2) is less than the second voltage (VGL1), an output voltage of a gate driving circuit can be made stable, an operational margin of a transistor can be improved, and a yield of a display device can be improved (see Page 8, Para. [0147]-[0148]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang, Ramsbey, and Feng with the teachings of Chung, such that a second output unit (T9, T10), as disclosed by Zhang, is connected to a third voltage input terminal, wherein a voltage level of the third voltage is less than the voltage level of the second voltage, as suggested by Chung, in order to provide a gate driving circuit that is made stable with an improved operational margin of a transistor and an improved yield of a display device.
As pertaining to Claim 18, Feng discloses (see Fig. 10) a leakage prevention transistor (M16) comprising a gate connected to the first node (Q), and comprising a first end connected to a first voltage input terminal (i.e., a high voltage input terminal (VA)) and a second end connected to an intermediate node of the first sub-transistors and an intermediate node of the second sub-transistors (see (M5) and (M9); and see Page 12, Para. [0167]-[0168]).
Again, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang with the teachings of Feng, such that each of the plurality of stages further comprises a leakage prevention transistor comprising a gate connected to the first node, and comprising a first end connected to the first voltage input terminal and a second end connected to an intermediate node of the pair of sub-transistors, as suggested by Feng, in order to allow for the implementation of leakage prevention in the gate driving circuit to thereby improve the performance of the gate driving circuit.
As pertaining to Claim 20, Zhang discloses (see Fig. 2) that each of the plurality of stages further comprises:
a second output unit (T9, T10) connected between the first voltage input terminal (VGH) and the second voltage input terminal (VGL), and configured to output the first voltage (VGH) or the second voltage (VGL) as a carry signal (i.e., a signal at (PD_ox)) according to the voltage levels of the second node (U4) and the third node (PD_ox; see Page 5, Para. [0073]-[0074]).
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the references relied upon by the examiner, considered alone or in reasonable combination, teach or fairly suggest the combination of features recited in Claims 1 and 7, wherein the second node controller further comprises: a fifth transistor connected between the first clock terminal and a fourth node, and comprising a gate connected to the first node; a sixth transistor connected between the first voltage input terminal and the fourth node, and comprising a first gate and a second gate which are connected to the first clock terminal; a seventh transistor connected between the fourth node and a fifth node, and comprising a gate connected to the first voltage input terminal; a capacitor connected between the fifth node and a sixth node; an eighth transistor connected between a second clock terminal to which a second clock signal is input and the sixth node, and comprising a gate connected to the fifth node; and a ninth transistor connected between the first voltage input terminal and the third node, and comprising a first gate and a second gate which are connected to the sixth node, wherein the first clock signal and the second clock signal repeat a voltage of a first voltage level and a voltage of a second voltage level, and the second clock signal is shifted by a half cycle from the first clock signal, as recited in Claim 8.
As pertaining to the most relevant prior art relied upon by the examiner, Zhang and Ramsbey disclose the features of Claims 1 and 7. However, neither Zhang nor Ramsbey nor any reasonable combination of references relied upon by the examiner teach or fairly suggest the combined features of Claims 1, 7, and 8. The claimed combination of features appears to be suggested solely by the applicant’s disclosure.
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the references relied upon by the examiner, considered alone or in reasonable combination, teach or fairly suggest the combination of features recited in Claim 17, wherein the second node controller further comprises: a fourth transistor connected between the first clock terminal and a fourth node, and comprising a gate connected to the first node; a fifth transistor connected between the first voltage input terminal and the fourth node, and comprising a gate connected to the first clock terminal; a sixth transistor connected between the fourth node and a fifth node, and comprising a gate connected to the first voltage input terminal; a capacitor connected between the fifth node and a sixth node; a seventh transistor connected between a second clock terminal to which a second clock signal is input and the sixth node, and comprising a gate connected to the fifth node; an eighth transistor connected between the first voltage input terminal and the third node, and comprising a gate connected to the sixth node; and a ninth transistor connected between the third node and the third voltage input terminal, and comprising a gate connected to the first node, wherein the first clock signal and the second clock signal repeat a voltage of a first voltage level and a voltage of a second voltage level, and the second clock signal is shifted by a half cycle from the first clock signal, as recited in Claim 19.
As pertaining to the most relevant prior art relied upon by the examiner, the combined teachings of Zhang, Ramsbey, Feng, and Chung disclose the features of independent Claim 17. However, none of Zhang, Ramsbey, Feng, and Chung, nor any reasonable combination of references relied upon by the examiner, teach or fairly suggest the combined features of Claims 17 and 19. The claimed combination of features appears to be suggested solely by the applicant’s disclosure.
Response to Arguments
Applicant's arguments filed 11 February 2026 have been fully considered but they are not persuasive. The applicant has argued, specifically with respect to independent Claims 1, 17, and 21, that none of the references relied upon by the examiner in the prior Office Action, particularly Zhang, teach or fairly suggest that “a gate signal input to the gate of the third transistor is the first voltage.” The examiner respectfully disagrees as this feature is clearly shown by Zhang at Figure 2, wherein a gate signal input to the gate of the third transistor (T4) is the first voltage (VGH) via the coupling of the capacitor (C2; see at least Page 5, Para. [0078]). The applicant has asserted with respect to the teachings of Zhang that a “gate of T4 is electrically connected to node PU, and the voltage present at node PU constitutes the gate signal applied to T4” and that “PU may, at certain times during operation, be charged to a volage level equal to VGH” (see Remarks at Page 12). Respectfully, this feature explicitly requires that “a gate signal input to the gate of the third transistor” (T4) “is the first voltage” (VGH) as maintained by the examiner.
Therefore, the rejection of Claims 1-7, 9-13, 15-18, and 20-21 is maintained. Claims 8 and 19 remain objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Han et al. (US 2024 / 0144885), Zheng et al. (US 11,574,597), Hong et al. (US 2022 / 0093028) all disclose gate driving circuits relevant to the applicant’s disclosed invention.
Son et al. (US 8,586,979) appears to assert (see Fig. 1) that a dual-gate oxide semiconductor transistor having gates (112, 122) formed in different layers enables “reduced threshold volage degradation from repeated driving” in a manner that is superior to a single-gate oxide semiconductor transistor (see Col. 9, Ln. 7-16).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON M MANDEVILLE whose telephone number is (571)270-3136. The examiner can normally be reached Mon - Fri 7:30AM-4:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON M MANDEVILLE/Primary Examiner, Art Unit 2623
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