Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-13 in the reply filed on 07 January 2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, a minimum lateral distance between a first end surface of a p-doped region of the pn or pin junction and a second end surface of an n-doped region of the pn or pin junction is in a range from 0.5 to 3 times a diffusion length of at least one of the p-doped regions or the n-doped region must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 5, 7, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaguchi et al. (US Patent Pub 20150014705 A1) in view of Sakurai et al. (US Patent Pub 20060215341 A1).
Regarding Claim 1, Kaguchi teaches an (Insulated Gate Bipolar Transistor) IGBT power semiconductor device, comprising:
a semiconductor body (Fig. 1, semiconductor body 10, 12, and 13);
a current sensing element including a pn or pin junction (Paragraph 0049 teaches a current sensing portion of the IGBT semiconductor device. Paragraph 0030 teaches the IGBT device main body is formed of a wide gap semiconductor material. Paragraph 0051 teaches the wide gap semiconductor material can be a PN junction diode. Therefore, the current sensing element can include a PN junction).
and an optical window configured to allow electromagnetic radiation caused by an on- current of the bipolar power semiconductor element to pass to the current sensing element (Kaguchi, Abstract teaches that emitted light at the time of emission of the semiconductor active portion is received at the photodiode. Paragraph 0032 teaches that light is received at the photodiode through optical window 20. Paragraph 0009 teaches the output current of the photodiode is determined by a light emission intensity of the emitted light and a current (operating current) flowing during operation of the semiconductor element).
Kaguchi fails to specifically teach a wiring area over a first surface of the semiconductor body, and the bipolar power semiconductor element having a first load electrode in the wiring area, an active area in the semiconductor body, and a second load electrode at a second surface of the semiconductor body
However, Sakurai teaches a bipolar power semiconductor device with a current sensing element, wherein wiring area over a first surface of the semiconductor body, and the bipolar power semiconductor element having a first load electrode in the wiring area, an active area in the semiconductor body, and a second load electrode at a second surface of the semiconductor body (Sakurai, Fig. 2, area above top surface of semiconductor body (102, 101, and 100) is the wiring area. First load electrode 121 in wiring area, active area 102, and second load electrode 122 at bottom surface of semiconductor body (102, 101, and 100).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Sakurai into the method of Kaguchi by forming the IGBT semicondcuctor device with a wiring area over a first surface of the semiconductor body, and the bipolar power semiconductor element having a first load electrode in the wiring area, an active area in the semiconductor body, and a second load electrode at a second surface of the semiconductor body. The ordinary artisan would have been motivated to modify Kaguchi in the manner set forth above for at least the purpose of improving device response and reliability (Sakurai, paragraph 0046).
Regarding Claim 3, Kaguchi in view of Sakurai teaches the power semiconductor device of claim 1, wherein the current sensing element is arranged in the wiring area (Sakurai, Fig. 2, a portion of current sensing element (region labeled sense IGBT) arranged in wiring area).
Regarding Claim 5, Kaguchi in view of Sakurai teaches the power semiconductor device of claim 1, wherein a surface of the current sensing element is textured (Sakurai, Fig. 2. 121, which is part of current sensing element (region labeled sense IGBT) is above the semiconductor body (102, 101, and 100). Therefore, the current sensing element is textured).
Regarding Claim 7, Kaguchi in view of Sakurai teaches the power semiconductor device of claim 1, further comprising deep level impurities in the current sensing element (Sakurai, fig. 2, layers 100, 101, and 102 are all doped regions containing deep level impurities).
Regarding Claim 11, Kaguchi in view of Sakurai teaches the power semiconductor device of claim 1, wherein an equipotential plane in the pn or pin junction is predominantly parallel to a vertical direction (Sakurai, Fig. 2. PN junction between 103B and 104B consists of two vertical portions and only one horizontal portion. Therefore, the equipotential plane at the PN junction between 103B and 104B is predominately parallel to a vertical direction).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaguchi in view of Sakurai as applied to claims 1, 3, 5, 7, and 11 above, and further in view of Cardwell et al. (US Patent Pub 20210020798 A1).
Regarding Claim 2, Kaguchi in view of Sakurai teaches the power semiconductor device of claim 1.
Kaguchi in view of Sakurai fails to specifically teach the materials the optical window comprises are a semiconductor material and dielectric material .
However, Cardwell teaches an optical window comprising semiconductor material and dielectric material (Cardwell, Fig. 3, optical window (layers 317, 319, 321, 101, 105, 107, 109, 111, 321, 319, and 315) comprising semiconductor material layers and dielectric material layers for reflecting light in a within the device. Paragraph 0044 teaches layer 105 comprises AlGaN, which is a semiconductor material. Paragraph 0076 teaches layer 319 is made of a dielectric material such as TiO2. Applicant’s own drawing (Fig. 1B) teaches the semiconductor body as well as the semiconductor and dielectric material layers are a part of the optical window and used to reflect light within the device.
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Cardwell into the method of Kaguchi in view of Sakurai by forming the IGBT semiconductor device with an optical window comprising semiconductor material and dielectric material. The ordinary artisan would have been motivated to modify Kaguchi in view of Sakurai in the manner set forth above for at least the purpose of tuning device performance to the desired wavelength and refractive index (Cardwell, paragraph 0076).
Regarding Claim 6, Kaguchi in view of Sakurai teaches the power semiconductor device of claim 1.
Kaguchi in view of Sakurai fail to teach a power semiconductor device further comprising a reflection layer configured to reflect the electromagnetic radiation back into the optical window.
However, Cardwell teaches a power semiconductor device comprising a reflection layer configured to reflect the electromagnetic radiation back into the optical window (Cardwell, Fig. 2, reflection layers 113 and 114).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Cardwell into the method of Kaguchi in view of Sakurai by forming the power semiconductor device having a reflection layer configured to reflect the electromagnetic radiation back into the optical window. The ordinary artisan would have been motivated to modify Kaguchi in view if Sakurai in the manner set forth above for at least the purpose of defining a reflector for reflecting light within the device (Cardwell, paragraph 0076).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaguchi in view of Sakurai as applied to claims 1, 3, 5, 7, and 11 above, and further in view of Wood (US Patent Pub 20160005732 A1).
Regarding Claim 4, Kaguchi in view of Sakurai teaches the power semiconductor device of claim 1.
Kaguchi in view of Sakurai fails to specifically teach the device having the pn or pin junction is a monocrystalline or a polycrystalline or a nanocrystalline silicon pn or pin junction.
However, Wood teaches a power semiconductor device with a polysilicon pn junction (Wood, Fig. 4b-4c. Paragraph 0177 teaches 4b and 4c are polysilicon PN junctions. Paragraph 0034 teaches these PN junctions (or “emitters”) are coupled to the current sensing element).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Wood into the method of Kaguchi in view of Sakurai by forming the pn or pin junction is a monocrystalline or a polycrystalline or a nanocrystalline silicon pn or pin junction. The ordinary artisan would have been motivated to modify Kaguchi in view if Sakurai in the manner set forth above for at least the purpose of achieve higher gain at higher current densities (Wood, paragraph 0177).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaguchi in view of Sakurai as applied to claims 1, 3, 5, 7, and 11 above, and further in view of Uchida et al. (US Patent Pub 20220216056 A1).
Regarding Claim 8, Kaguchi in view of Sakurai teaches the IGBT power semiconductor device of claim 1.
Kaguchi in view of Sakurai fails to teach the IGBT power semiconductor device wherein the semiconductor body is a silicon semiconductor body and the deep level impurities include at least one of selenium, sulfur, thallium, and zinc.
However, Uchida teaches an IGBT power semiconductor device wherein the semiconductor body is a silicon semiconductor body and the deep level impurities include at least one of selenium, sulfur, thallium, and zinc (Uchida, Fig. 22A, semiconductor body 10. Paragraph 0051 teaches 10 is formed of a semiconductor material such as silicon. Paragraph 0053 teaches 10 can be doped with selenium or sulfur).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Uchida into the method of Kaguchi in view of Sakurai by forming the power semiconductor device wherein the semiconductor body is a silicon semiconductor body and the deep level impurities include at least one of selenium, sulfur, thallium, and zinc. The ordinary artisan would have been motivated to modify Kaguchi in view if Sakurai in the manner set forth above for at least the purpose of tuning the power semiconductor device performance (Uchida, paragraph 0053).
Claim(s) 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaguchi in view of Sakurai as applied to claims 1, 3, 5, 7, and 11 above, and further in view of Kim et al. (US Patent Pub 20210202341 A1).
Regarding Claim 9, Kaguchi in view of Sakurai teaches the power semiconductor device of claim 1.
Kaguchi in view of Sakurai fails to teach the current sensing element including a plurality of the pn or pin junctions connected in series or in parallel.
However, Kim teaches a power semiconductor device having a current sensing element including a plurality of the pn or pin junctions connected in series or in parallel (Kim, Fig. 7, current sensor element 22 including a plurality of pn junctions connected in series).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Kim into the method of Kaguchi in view of Sakurai by forming the current sensing element including a plurality of the pn or pin junctions connected in series or in parallel. The ordinary artisan would have been motivated to modify Kaguchi in view if Sakurai in the manner set forth above for at least the purpose of tailoring the forward voltage to a particular sensing circuitry (Kim, paragraph 0065).
Regarding Claim 10, Kaguchi in view of Sakurai teaches the power semiconductor device of claim 1.
Kaguchi in view of Sakurai fail to teach a surface recombination reduction structure on a surface of the current sensing element.
However, Kim teaches a power semiconductor device having a surface recombination reduction structure on a surface of the current sensing element (Kim, Fig. 5, current sensing element (layers 54, 52, 58, 60, 50B, and 44). Paragraph 0060 teaches surface recombination reduction structure 58, which can be SiO2, is on a surface of the current sensing element. Paragraph 0036 of the Applicant’s own specification teaches that the surface recombination structure may include one or more thin dielectric layers of SiO2, therefore 58 is a surface recombination structure.
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Kim into the method of Kaguchi in view of Sakurai by forming a surface recombination reduction structure on a surface of the current sensing element. The ordinary artisan would have been motivated to modify Kaguchi in view if Sakurai in the manner set forth above for at least the purpose of providing the current sensing element with increased shielding (Kim, paragraph 0060).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaguchi in view of Sakurai as applied to claims 1, 3, 5, 7, and 11 above, and further in view of Laven et al. (US 20160352326 A1).
Regarding Claim 13, Kaguchi in view of Sakurai teaches teaches the power semiconductor device of claim 1.
Kaguchi in view of Sakurai fails to teach the current sensing element is thermally coupled to the semiconductor body of the power semiconductor device.
However, Laven teaches an IGBT semiconductor device wherein the current sensing element is thermally coupled to the semiconductor body (Laven, paragraph 0136 teaches all electrodes are thermally coupled to the semiconductor body, including the current sensing element).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Laven into the method of Kaguchi in view of Sakurai by forming the power semiconductor device wherein the current sensing element is thermally coupled to the semiconductor body. The ordinary artisan would have been motivated to modify Kaguchi in view if Sakurai in the manner set forth above for at least the purpose of better adjusting the electrical performance of the device (Laven, paragraph 0136).
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/V.R.G./Examiner, Art Unit 2899
/JOHN M PARKER/Examiner, Art Unit 2899