DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on 6/17/2026 is/are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Response to Amendment
The amendment with respect to claim(s) 1, 11, and 16 filed on 6/17/2026 have been fully considered for examination based on their merits. The previously presented claim(s) 2-10, 12-15, and 17-24 have been considered.
Response to Arguments
Applicant's arguments filed 04/14/2026 have been fully considered but they are not persuasive.
Regarding Independent Claim(s) 1, 11, and 16. The independent claims 1, 11, and 16 are amended, now recite, “a display device comprising: wherein a lower surface of the semiconductor pattern of the semiconductor thin-film transistor is in contact with an upper surface of the conductive pattern.” The Applicant argues (see Remarks, page 10) that the cited references except AFZALI-ARDAKANI (US9553056B1) disclose or suggest a configuration corresponding to a surface-to-surface contact between a metal layer and a semiconductor layer as mentioned in the amendment above. The Applicant further argues that the amended limitations as recited in Claims 1, 11, and 16, differ from AFZALI-ARDAKANI, because of the instant application wherein the configuration in which a metal layer is in direct contact with a semiconductor material layer. The Examiner reviewed the amended features of Claims 1, 11 and 16, and confirmed that it is currently stated, “a lower surface of the driving semiconductor pattern is in contact” and not precisely “in direct contact” as argued above. Therefore, per the current limitations to amended claims 1, 11, and 16, the prior art (OH, US20220367772) applied in the previous Office Action filed on 01/21/2026 are still read those claimed features (see annotated drawing of OH below) as mentioned above. Based on the broadest reasonable interpretation (BRI), the Examiner maintains the rejection of the record with respect to independent claims 1, 11, and 16.
Regarding Claim(s) 2-10, 12-15, and 17-24: The dependent claims 2-10, 12-15, and 17-24 follow similar arguments as Claims 1, 11, and 16 mentioned above.
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Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, and 8-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eon Seok Oh et al, (hereinafter OH), US 20220367772 A1.
Regarding Claim 1, OH teaches a display device (Figs. 7, 100, display panel) comprising:
a pixel driving circuit (Fig. 7, PC3, third pixel circuit) located on a device substrate (Fig. 7, 110, base layer), the pixel driving circuit (Fig. 7, PC3, third pixel circuit) comprising a driving thin-film transistor (Fig. 7, S-TFT/O-TFT);
a conductive pattern (Fig. 7, BML, back metal layer) located between the device substrate (Fig. 7, 110, base layer) and the driving thin-film transistor (Fig. 7, S-TFT/O-TFT), the conductive pattern (Fig. 7, BML, back metal layer) made of a metal (BML may include for example, molybdenum (Mo), titanium (Ti), aluminum (Al), silver (Ag), copper (Gu), or the like, [0130]); and
a light-emitting device (Fig. 7, LD3, third light-emitting elements) located on the device substrate (Fig. 7, 110, base layer) and electrically connected (Fig. 7, similar to AE1, the third lower electrode, AE3 may be electrically connected to the third pixel circuit, PC3 through a connection electrode, CNE2/CNE1, [0154]) to the driving thin-film transistor (Fig. 7, S-TFT/O-TFT),
wherein the driving thin-film transistor (Fig. 7, S-TFT/O-TFT) comprises a driving semiconductor pattern (Fig. 7, AC1, active region, a portion of the semiconductor pattern may be an active region of the transistor, [0134]) made of an oxide semiconductor (Fig. 7, the second semiconductor pattern may include an oxide semiconductor, [0139]),
wherein a lower surface (annotated Figure 7) of the driving semiconductor pattern (Fig. 7, AC1, active region, a portion of the semiconductor pattern may be an active region of the transistor, [0134]) is in contact with an upper surface (annotated Figure 7) of the conductive pattern (Fig. 7, BML, back metal layer), the upper surface being (annotated Figure 7) opposite the device substrate (Fig. 7, 110, base layer), and
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wherein the metal (BML may include for example, molybdenum (Mo), titanium (Ti), aluminum (Al), silver (Ag), copper (Gu), or the like, [0130]) of the conductive pattern (Fig. 7, BML, back metal layer) has a larger work function (work function of the said metals in range of 4.06-5.10 eV compared to metal oxides, according to Wikipedia regarding the work function of metals) than the oxide semiconductor (Fig. 7, the second semiconductor pattern may include an oxide semiconductor, [0139]) of the driving semiconductor pattern (Fig. 7, AC1, active region, a portion of the semiconductor pattern may be an active region of the transistor, [0134]).
Regarding Claim 3, OH teaches the display device (Fig. 7, 100, display panel) according to claim 1, wherein the conductive pattern (Fig. 7, BML, back metal layer) is electrically connected (Fig. 7, CPN, connection bridge/ CNE1/CNE2, connection electrode) to a driving source electrode (Fig. 7, SE1/SE2) of the driving thin-film transistor (Fig. 7, S-TFT/O-TFT).
Regarding Claim 4, OH teaches the display device (Figs. 7, 100, display panel) according to claim 3.
wherein the conductive pattern (Fig. 7, BML, back metal layer) comprises a region located outside (Figs. 7-8) the driving semiconductor pattern (Fig. 7, AC1, active region, a portion of the semiconductor pattern may be an active region of the transistor, [0134]) so as not to overlap (Figs. 7-8) with the driving semiconductor pattern (Fig. 7, AC1, active region, a portion of the semiconductor pattern may be an active region of the transistor, [0134]), and
wherein the driving source electrode (Fig. 7, SE1/SE2) is in contact with the conductive pattern (Fig. 7, BML, back metal layer) at the region located outside (Figs. 7-8) the driving semiconductor pattern (Fig. 7, AC1, active region, a portion of the semiconductor pattern may be an active region of the transistor, [0134]).
Regarding Claim 8, OH teaches the display device (Figs. 7, 100, display panel) according to claim 1, wherein the conductive pattern (Fig. 7, BML, back metal layer) comprises one of copper, molybdenum, nickel, cobalt, and platinum ([0173]).
Regarding Claim 9, OH teaches the display device (Figs. 7, 100, display panel) according to claim 1, wherein the conductive pattern (Fig. 7, BML, back metal layer) overlaps a first portion of the driving semiconductor pattern (Fig. 7, AC1, active region, a portion of the semiconductor pattern may be an active region of the transistor, [0134]; right side of the BML) and does not overlap a second portion of the driving semiconductor pattern (Fig. 7, AC1, active region, a portion of the semiconductor pattern may be an active region of the transistor, [0134]; left side of the BML).
Regarding Claim 10, OH teaches the display device (Figs. 7, 100, display panel) according to claim 9, wherein the driving semiconductor pattern (Fig. 7, AC1, active region, a portion of the semiconductor pattern may be an active region of the transistor, [0134]) comprises a channel region (Fig. 7, AC1) overlapping with the conductive pattern (Fig. 7, BML, back metal layer).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over OH as applied to claims 1, 3-4, and 8-10 above, in view of Ali Afzali-Ardakani et al, (hereinafter AFZALI-ARDAKANI), US 9553056 B1.
Regarding Claim 2, OH teaches the display device (Figs. 7, 100, display panel) according to claim 1, wherein the driving semiconductor pattern (Fig. 7, AC1, active region, a portion of the semiconductor pattern may be an active region of the transistor, [0134]) comprises a rear portion located adjacent to the conductive pattern (Fig. 7, BML, back metal layer).
OH does not explicitly disclose the display device, wherein the driving semiconductor pattern, the rear portion comprises a depletion region.
AFZALI-ARDAKANI teaches the display device (Fig. 1, 20, semiconductor structure), wherein the driving semiconductor pattern (Fig. 10, 24, semiconductor layer), the rear portion comprises a depletion region (Fig. 10 WD, depletion region width, [Col. 11, Lines 5-10]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified OH to incorporate the teachings of AFZALI-ARDAKANI, such that the display device, wherein the driving semiconductor pattern, the rear portion comprises a depletion region, so that the width of the depletion region which is a function of voltage, therefore, by illumination creates an additional voltage (AFZALI-ARDAKANI, [Col. 11, Lines 5-10])
Claim(s) 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over OH as applied to claims 1, 3-4, and 8-10 above, in view of Kyeong-Ju Moon et al, (hereinafter MOON), US 20210202634 A1
Regarding Claim 5, OH teaches the display device (Figs. 7, 100, display panel) according to claim 1.
OH does not explicitly disclose the display device, wherein the conductive pattern comprises a first pattern layer and a second pattern layer located on the first pattern layer, wherein the driving semiconductor pattern is in contact with the second pattern layer, and wherein the second pattern layer has a larger work function than the driving semiconductor pattern.
MOON teaches the display device (Fig. 2, 200, display apparatus), wherein the conductive pattern (Fig. 1, 150, second storage capacitor) comprises a first pattern layer (Fig. 1, 151, lower electrode) and a second pattern layer (Fig. 1, 152, upper electrode) located on the first pattern layer (Fig. 1, 151, lower electrode),
wherein the driving semiconductor pattern (Fig. 1, 331, third semiconductor pattern) is in contact with the second pattern layer (Fig. 1, 152, upper electrode), and
wherein the second pattern layer (Fig. 1, 152, upper electrode) has a larger work function (work function of the said metals [0056] in range of 4.06-5.10 eV compared to metal oxides, according to Wikipedia regarding the work function of metals) than the driving semiconductor pattern (Fig. 1, 331, third semiconductor pattern).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified OH to incorporate the teachings of MOON, such that the display device, wherein the conductive pattern comprises a first pattern layer and a second pattern layer located on the first pattern layer, wherein the driving semiconductor pattern is in contact with the second pattern layer, and wherein the second pattern layer has a larger work function than the driving semiconductor pattern, so that the display device demonstrate with high reflection efficiency (MOON, [0096]).
Regarding Claim 6, OH as modified by MOON teaches the display device according to claim 5.
MOON further teaches the display device (Fig. 2, 200, display apparatus), wherein the second pattern layer (Fig. 1, 152, upper electrode) is made of a conductive metal oxide ([0059]).
Regarding Claim 7, OH as modified by MOON teaches the display device according to claim 6.
MOON further teaches the display device (Fig. 2, 200, display apparatus), wherein the first pattern layer (Fig. 1, 151, lower electrode) comprises a same metal ([0059]) as the second pattern layer (Fig. 1, 152, upper electrode).
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jinsung An et al, (hereinafter AN), US 20220336564 A1, in view of Kangyoung Lee et al, (hereinafter LEE), US 20210118968 A1, Chi-Wen Chen et al, (CHEN), US 20060124930 A1, and OH as applied to claims 1, 2-4, and 8-10.
Regarding Claim 11, AN teaches a display device (Figs. 5, 10, display panel) comprising:
a first conductive pattern (Fig. 5, BSL, bottom shielding layer) located on a device substrate (Fig. 5, 100);
an upper buffer layer (Fig. 5, 111) located on the device substrate (Fig. 5, 100) to cover the first conductive pattern (Fig. 5, BSL, bottom shielding layer);
a second conductive pattern (Fig. 5, BGE, bottom gate electrode) located on the upper buffer layer (Fig. 5, 111), the second conductive pattern (Fig. 5, BGE, bottom gate electrode) made of a metal (BGE include the same material as CE2, [0112], [0203]);
a pixel driving circuit (Fig. 5, PC3, third pixel circuit) located on the device substrate (Fig. 5, 100), the pixel driving circuit (Fig. 5, PC3, third pixel circuit) comprising a first thin-film transistor (Fig. 5, TFT1) located on the first conductive pattern (Fig. 5, BSL, bottom shielding layer) and a second thin-film transistor (Fig. 5, TFT2) located on the second conductive pattern (Fig. 5, BGE, bottom gate electrode); and
wherein the second thin-film transistor (Fig. 5, TFT2) comprises a semiconductor pattern (Fig. 5, Act2, semiconductor layer, [0165]) made of an oxide semiconductor (Fig. 5, TFT2 may include an oxide semiconductor, [0165]).
Though AN teaches a light-emitting device electrically connected to the first thin-film transistor, AN does not explicitly disclose a display device comprising: a light-emitting device electrically connected to the second thin-film transistor.
LEE teaches a display device (Fig. 1, 1) comprising: a light-emitting device (Fig. 5, OLED) electrically connected (Fig. 5, CM, connection electrode, [0111]) to the second thin-film transistor (Fig. 5, TFT′).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified AN to incorporate the teachings of LEE, such that a display device comprising: a light-emitting device electrically connected to the second thin-film transistor, so that a connection electrode, CM may connect the thin film transistor, TFT to the organic light-emitting diode, OLED for pixel conversion to electrical power voltage (LEE, [0060], [0111]).
AN as modified by LEE does not explicitly disclose a display device comprising: wherein the semiconductor pattern of the second thin-film transistor is in Schottky contact with the second conductive pattern.
CHEN teaches a display device (TFT-LCD displays, [0005]) comprising: wherein the semiconductor pattern of the second thin-film transistor (Fig. 2, 30, thin film transistor) is in Schottky contact (Fig. 2, [0007], [0043]) with the second conductive pattern (Fig. 2, interface between the source electrode, 42, and the drain electrode, 44, and the amorphous silicon layer, 18, [0007]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have AN as modified by LEE to incorporate the teachings of CHEN, such that a display device comprising: wherein the semiconductor pattern of the second thin-film transistor is in Schottky contact with the second conductive pattern, so that Schottky contact occurs in the interface of the semiconductor layer made of other materials and the metal electrode and thus reduce the current leakage problem (CHEN, [0043]).
AN as modified by LEE and CHEN does not disclose a display device comprising: wherein a lower surface of the semiconductor pattern of the second thin-film transistor is in contact with an upper surface of the conductive pattern.
OH teaches a display device (Figs. 7, 100, display panel) comprising: wherein a lower surface (annotated Figure 7) of the semiconductor pattern (Fig. 7, AC1, active region, a portion of the semiconductor pattern may be an active region of the transistor, [0134]) of the second thin-film transistor (Fig. 7, S-TFT/O-TFT) is in contact with an upper surface (annotated Figure 7) of the conductive pattern (Fig. 7, BML, back metal layer).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have AN as modified by LEE and CHEN to incorporate the teachings of OH, such that a display device comprising: wherein a lower surface of the semiconductor pattern of the second thin-film transistor is in contact with an upper surface of the conductive pattern, so that to improve the transmittance characteristics of a display device and thus improve their reliability (OH, [0002]).
Regarding Claim 12, AN as modified by LEE, CHEN and OH teaches the display device according to claim 11.
AN further teaches a display device (Figs. 5, 10, display panel), wherein the second conductive pattern (Fig. 5, BGE, bottom gate electrode) is electrically connected (Fig. 5, WL, line, [0125]) to a source electrode (Fig. 5, SE2), of the second thin-film transistor (Fig. 5, TFT2).
Claim(s) 13, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over AN, in view of LEE, CHEN, and OH as applied to claims 11, and 12 above and further in view of Kuan-FENG Lee et al, (hereinafter LEE2, US 20170338252 A1.
Regarding Claim 13, AN as modified by LEE, CHEN and OH teaches the display device according to claim 11.
AN as modified by LEE, CHEN and OH does not explicitly disclose the display device, wherein the first thin-film transistor comprises a semiconductor pattern located on a same layer as the second conductive pattern.
LEE2 teaches the display device (Fig. 7, display device), wherein the first thin-film transistor (Fig. 7, 13a/13b, first/second semiconductor layer) comprises a semiconductor pattern (Fig. 7, 111, light shielding layer) located on a same layer as the second conductive pattern (Fig. 7, 112, light shielding layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have AN as modified by LEE, CHEN, and OH to incorporate the teachings of LEE2, such that the display device, wherein the first thin-film transistor comprises a semiconductor pattern located on a same layer as the second conductive pattern, so that the simultaneous formation of the light shielding layers, 111 and 112 thus ensure the uniformity and improve the simplify process for manufacturing thin film transistors and display devices (LEE2, [0006]).
Regarding Claim 15, AN as modified by LEE, CHEN, OH and LEE2 teaches the display device according to claim 13.
LEE2 further teaches the display device (Fig. 7, display device), further comprising:
an upper gate insulating layer (Fig. 5, 112) located on the upper buffer layer (Fig. 5, 111),
wherein the upper gate insulating layer (Fig. 7, 14, gate insulating layer) covers the semiconductor pattern (Fig. 7, 111, light shielding layer) of the first thin-film transistor (Fig. 7, 13a, first semiconductor layer) and the semiconductor pattern (Fig. 7, 13b, second semiconductor layer) of the second thin-film transistor,
wherein each of the first thin-film transistor (Fig. 7, 13a, first semiconductor layer) and the second thin-film transistor (Fig. 7, 13b, second semiconductor layer) comprises a gate electrode (Fig 7, 151/152) located on the upper gate insulating layer (Fig. 7, 14, gate insulating layer), and
wherein the gate electrode (Fig 7, 152) of the second thin-film transistor (Fig. 7, 13a, first semiconductor layer) is located on a same layer as the gate electrode (Fig 7, 151) of the first thin-film transistor (Fig. 7, 13b, second semiconductor layer).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over AN, in view of LEE, CHEN, OH and LEE2 as applied to Claims 11-13 above, and further in view of MOON as applied to claims 5-7 above.
Regarding Claim 14 AN as modified by LEE, CHEN, OH and LEE2 teaches the display device according to claim 13.
AN as modified by LEE, CHEN, OH and LEE2 does not explicitly disclose the display device, wherein the semiconductor pattern of the first thin-film transistor comprises a same material as the semiconductor pattern of the second thin-film transistor.
MOON teaches the display device (Fig. 2, 200, display apparatus), wherein the semiconductor pattern (Fig. 2, 610, first metal pattern) of the first thin-film transistor (Fig. 2, 350, first thin film transistor) comprises a same material as the semiconductor pattern (Fig. 2, 620, second metal pattern) of the second thin-film transistor (Fig. 2, 320, second thin film transistor).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have AN as modified by LEE, CHEN, OH and LEE2 to incorporate the teachings of MOON, such that the display device, wherein the semiconductor pattern of the first thin-film transistor comprises a same material as the semiconductor pattern of the second thin-film transistor, so that the uniformity in terms of material properties are maintained while manufacturing the display device having higher reflection efficiency (MOON, [0096]).
Claim(s) 16-17, 20-21, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hoon Yim et al, (hereinafter YIM), US 20110278565 A1, in view of LEE, and OH as applied to claim 11 above.
Regarding Claim 16, YIM teaches a thin film transistor (Fig. 3, oxide TFT, [0031]) for driving a light-emitting element of a display device (UV light emitting diode (LED), [0046]), the thin film transistor (Fig. 3, oxide TFT, [0031]) comprising:
an oxide semiconductor pattern (Fig. 3, 124, active layer made of oxide semiconductor, [0038]) including oxide semiconductor material (Fig. 3, 124, active layer made of oxide semiconductor, [0038]);
a gate insulation layer (Fig. 3, 115a, gate insulating layer) disposed on a first side of the oxide semiconductor pattern (Fig. 3, 124, active layer made of oxide semiconductor, [0038]);
a gate electrode (Fig. 3, 121) disposed on the gate insulation layer (Fig. 3, 115a, gate insulating layer);
a first electrode (Fig. 3, 122, source electrode) electrically connected (Fig. 3, 125b, contact layers, [0065]) to the oxide semiconductor pattern (Fig. 3, 124, active layer made of oxide semiconductor, [0038]);
a second electrode (Fig. 3, 123, drain electrode) electrically connected (Fig. 3, 125b, contact layers, [0065]) to the oxide semiconductor pattern (Fig. 3, 124, active layer made of oxide semiconductor, [0038]).
YIM does not disclose a thin film transistor for driving a light-emitting element of a display device, the thin film transistor comprising: the second electrode electrically connected to the light-emitting element such that the thin film transistor drives current through the light-emitting element.
LEE teaches a thin film transistor (Fig. 5, TFT′) for driving a light-emitting element of a display device (Fig. 1, 1) comprising: the second electrode (Fig. 5, 216a, second drain electrode) electrically connected (Fig. 5, CM, connection electrode, [0111]) to the light-emitting element (Fig. 5, OLED) such that the thin film transistor (Fig. 5, TFT′) drives current (Fig. 2, [0061]) through the light-emitting element (Fig. 5, OLED).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified YIM to incorporate the teachings of LEE, such that a thin film transistor for driving a light-emitting element of a display device, the thin film transistor comprising: the second electrode electrically connected to the light-emitting element such that the thin film transistor drives current through the light-emitting element, so that the organic light-emitting diode, OLED may emit light having a brightness by using the driving current (LEE, [0061]).
YIM as modified by LEE does not explicitly disclose a thin film transistor for driving a light-emitting element of a display device, the thin film transistor comprising: a conductive pattern made of a metal disposed directly on a second side of the oxide semiconductor pattern, the conductive pattern having a first work function greater than a second work function of the oxide semiconductor pattern, wherein a lower surface of the oxide semiconductor pattern is in contact with an upper surface of the conductive pattern.
OH teaches a thin film transistor (Fig. 7, S-TFT/O-TFT) for driving a light-emitting element (Fig. 7, LD3, third light-emitting elements) of a display device (Figs. 7, 100, display panel), the thin film transistor (Fig. 7, S-TFT/O-TFT) comprising: a conductive pattern (Fig. 7, BML, back metal layer) made of a metal disposed directly on a second side of the oxide semiconductor pattern (Fig. 7, AC1, active region, a portion of the semiconductor pattern may be an active region of the transistor, [0134]; the second semiconductor pattern may include an oxide semiconductor, [0139]), the conductive pattern (Fig. 7, BML, back metal layer) having a first work function greater than a second work function of the oxide semiconductor pattern (work function of the said metals in range of 4.06-5.10 eV compared to metal oxides, according to Wikipedia regarding the work function of metals), wherein a lower surface (annotated Figure 7) of the oxide semiconductor pattern (Fig. 7, AC1, active region, a portion of the semiconductor pattern may be an active region of the transistor, [0134]) is in contact with an upper surface (annotated Figure 7) of the conductive pattern (Fig. 7, BML, back metal layer).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YIM as modified by LEE to incorporate the teachings of OH, such that a thin film transistor for driving a light-emitting element of a display device, the thin film transistor comprising: a conductive pattern made of a metal disposed directly on a second side of the oxide semiconductor pattern, the conductive pattern having a first work function greater than a second work function of the oxide semiconductor pattern. The said arrangement of conductive patterns or back metal layers with greater work function improve the transmittance and reliability of the display device (OH, [0002]).
Regarding Claim 17, YIM as modified by LEE and OH teaches the thin film transistor of claim 16.
OH further teaches a thin film transistor (Fig. 7, S-TFT/O-TFT), wherein the conductive pattern (Fig. 7, BML, back metal layer) is electrically coupled to a DC voltage (Fig. 7, similar to AE1, the third lower electrode, AE3 may be electrically connected to the third pixel circuit, PC3 through a connection electrode, CNE2/CNE1, [0154]) or the second electrode (Fig. 7, DE1, drain region, [0134]) .
Regarding Claim 20, YIM as modified by LEE and OH teaches the thin film transistor of claim 16.
OH further teaches a thin film transistor (Fig. 7, S-TFT/O-TFT), wherein the conductive pattern (Fig. 7, BML, back metal layer) overlaps with the entire oxide semiconductor pattern (Fig. 7, AC1, active region, a portion of the semiconductor pattern may be an active region of the transistor, [0134]; the second semiconductor pattern may include an oxide semiconductor, [0139]) and extends beyond edges of the oxide semiconductor pattern (Fig. 7, AC1, active region, a portion of the semiconductor pattern may be an active region of the transistor, [0134]; the second semiconductor pattern may include an oxide semiconductor, [0139]).
Regarding Claim 21, YIM as modified by LEE and OH teaches the thin film transistor of claim 16.
OH further teaches a thin film transistor (Fig. 7, S-TFT/O-TFT), further comprising another conductive pattern (Fig. 7, BML, back metal layer) disposed beyond edges of the oxide semiconductor pattern (Fig. 7, AC1, active region, a portion of the semiconductor pattern may be an active region of the transistor, [0134]; the second semiconductor pattern may include an oxide semiconductor, [0139]), the source electrode (Fig. 8, SE1/SE2, source region, [0134]) electrically connected (Fig. 8, CPN, connection bridge, [0154]), to the another conductive pattern (Fig. 8, TWL, connection wiring, [0154]).
Regarding Claim 24, YIM as modified by LEE and OH teaches the thin film transistor of claim 16.
OH further teaches a thin film transistor (Fig. 7, S-TFT/O-TFT), wherein the conductive pattern (Fig. 7, BML, back metal layer) comprises one of copper, molybdenum, nickel, cobalt, and platinum ([0173]).
Claim(s) 18-19, and 22-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over YIM, in view of LEE, OH as applied to claim 16, and further in view of MOON as applied to claims 5-7 above.
Regarding Claim 18, YIM as modified by LEE and OH teaches the thin film transistor of claim 16.
LEE further teaches the thin film transistor (Fig. 5, TFT′) wherein:
the oxide semiconductor pattern (Fig. 5, 212, second semiconductor layer, may include an oxide semiconductor, [0128]) includes a source region (Fig. 5, 212b, second source region), a drain region (Fig. 5, 212a, second drain region), and a channel region (Fig. 5, 212c, second channel region) between the source region (Fig. 5, 212b, second source region) and the drain region (Fig. 5, 212a, second drain region), the source region (Fig. 5, 212b, second source region) and the drain region (Fig. 5, 212a, second drain region) including the oxide semiconductor material (Fig. 5, 212, second semiconductor layer, may include an oxide semiconductor, [0128]), and the channel region (Fig. 5, 212c, second channel region) including the oxide semiconductor material free of the dopant (Fig. 5, 212, second semiconductor layer, may include an oxide semiconductor, [0128]),
OH further teaches a thin film transistor (Fig. 7, S-TFT/O-TFT), wherein, the source region and the drain region including the oxide semiconductor material doped with a dopant (first region, doped with p-type or n-type dopant, first region may serve or substantially serve as an electrode or a signal line (e.g., source or drain), [0132]), and the channel region including the oxide semiconductor material free of the dopant (a second region may be an undoped region, the second region may correspond to or substantially correspond to an active region (e.g. channel), [0132]).
YIM as modified by LEE and OH does not explicitly disclose the thin film transistor, wherein, the conductive pattern extends shorter than edges of the oxide semiconductor region, and the conductive pattern overlaps with the channel region but does not overlap with the source region or the drain region.
MOON teaches the thin film transistor (Fig. 2, 330, third thin film transistor), wherein, the conductive pattern (Fig. 2, 630, third metal pattern) extends shorter than edges of the oxide semiconductor region (Fig. 2, 331, third semiconductor pattern), and the conductive pattern (Fig. 2, 630, third metal pattern) overlaps with the channel region (Fig. 2, 331C, third channel region) but does not overlap with the source region (Fig. 2, 331S, third source region) or the drain region (Fig. 2, 331D, third drain region).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YIM as modified by LEE and OH to incorporate the teachings of MOON, such that the thin film transistor, wherein, the conductive pattern extends shorter than edges of the oxide semiconductor region, and the conductive pattern overlaps with the channel region but does not overlap with the source region or the drain region, so that the light transmittance from the light emitting element is improved in terms of brightness and reliability of the display device (MOON, [0043]).
Regarding Claim 19, YIM as modified by LEE, OH, and MOON teaches the thin film transistor of claim 18.
MOON further teaches the thin film transistor (Fig. 2, 330, third thin film transistor), wherein the conductive pattern (Fig. 2, 630, third metal pattern) extends shorter than edges of the oxide semiconductor region (Fig. 2, 331, third semiconductor pattern); and
wherein the oxide semiconductor region (Fig. 2, 331, third semiconductor pattern) has stepped shapes (Fig. 2, 331, third semiconductor pattern demonstrating stepped profile).
Regarding Claim 22, YIM as modified by LEE and OH teaches the thin film transistor of claim 16.
YIM as modified by LEE and OH does not explicitly disclose the thin film transistor, wherein the conductive pattern comprises a first conductive pattern layer and a second conductive pattern layer disposed on the first conductive pattern layer, wherein the oxide semiconductor pattern is in direct contact with the second conductive pattern layer, and wherein the second conductive pattern layer has the first work function greater than the second work function of the oxide semiconductor pattern.
MOON teaches the thin film transistor (Fig. 2, 330, third thin film transistor),
wherein the conductive pattern (Fig. 1, 150, second storage capacitor) comprises a first conductive pattern layer (Fig. 1, 151, lower electrode) and a second conductive pattern layer (Fig. 1, 152, upper electrode) disposed on the first conductive pattern layer (Fig. 1, 151, lower electrode),
wherein the oxide semiconductor pattern (Fig. 1, 331, third semiconductor pattern) is in direct contact (Fig. 1, 170, second connecting electrode) with the second conductive pattern layer (Fig. 1, 152, upper electrode), and
wherein the second conductive pattern (Fig. 1, 152, upper electrode) layer has the first work function greater (work function of the said metals [0056] in range of 4.06-5.10 eV compared to metal oxides, according to Wikipedia regarding the work function of metals) than the second work function of the oxide semiconductor pattern (Fig. 1, 331, third semiconductor pattern).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YIM as modified by LEE and OH to incorporate the teachings of MOON, such that the thin film transistor, wherein the conductive pattern comprises a first conductive pattern layer and a second conductive pattern layer disposed on the first conductive pattern layer, wherein the oxide semiconductor pattern is in direct contact with the second conductive pattern layer, and wherein the second conductive pattern layer has the first work function greater than the second work function of the oxide semiconductor pattern, so that the display device demonstrate with high reflection efficiency (MOON, [0096]).
Regarding Claim 23, YIM as modified by LEE, OH, and MOON teaches the thin film transistor of claim 22.
LEE further teaches the thin film transistor (Fig. 5, TFT′) wherein the second conductive pattern layer (Fig. 5, 212, second semiconductor layer) comprises a conductive metal oxide (the second semiconductor layer, 212, may include an oxide semiconductor, [0128]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220406877 A1 – Figure 6A
STATEMENT OF RELEVANCE – The semiconductor patter, AC1 of S-TFT is in contact with the conductive pattern or BML.
US 20210359057 A1 - Figure 20
STATEMENT OF RELEVANCE – The semiconductor pattern, 131 of the transistor, TRR1, is in contact with the conductive patter, 111
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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